JPS6359342U - - Google Patents
Info
- Publication number
- JPS6359342U JPS6359342U JP1986153842U JP15384286U JPS6359342U JP S6359342 U JPS6359342 U JP S6359342U JP 1986153842 U JP1986153842 U JP 1986153842U JP 15384286 U JP15384286 U JP 15384286U JP S6359342 U JPS6359342 U JP S6359342U
- Authority
- JP
- Japan
- Prior art keywords
- base
- terminal conductor
- emitter
- transistors
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Amplifiers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986153842U JPS6359342U (en:Method) | 1986-10-07 | 1986-10-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986153842U JPS6359342U (en:Method) | 1986-10-07 | 1986-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6359342U true JPS6359342U (en:Method) | 1988-04-20 |
Family
ID=31073089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986153842U Pending JPS6359342U (en:Method) | 1986-10-07 | 1986-10-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6359342U (en:Method) |
-
1986
- 1986-10-07 JP JP1986153842U patent/JPS6359342U/ja active Pending