JPS6359324U - - Google Patents
Info
- Publication number
- JPS6359324U JPS6359324U JP1986153335U JP15333586U JPS6359324U JP S6359324 U JPS6359324 U JP S6359324U JP 1986153335 U JP1986153335 U JP 1986153335U JP 15333586 U JP15333586 U JP 15333586U JP S6359324 U JPS6359324 U JP S6359324U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- terminal
- circuit components
- connection terminals
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図はこの考案の実施例による電子回路部品
の接続状態を示す側面図、第2図は第1図におけ
る回路部品の接続端子部の平面展開図、第3図、
第4図はそれぞれ従来方式による回路部品の接続
状態を示す側面図およびその接続端子部の平面展
開図、第5図は並列電極方式の平面展開図である
。各図において、 1:電子回路部品、2:配線基板、3:配線パ
ターン、4:電極、5:はんだバンプ。
の接続状態を示す側面図、第2図は第1図におけ
る回路部品の接続端子部の平面展開図、第3図、
第4図はそれぞれ従来方式による回路部品の接続
状態を示す側面図およびその接続端子部の平面展
開図、第5図は並列電極方式の平面展開図である
。各図において、 1:電子回路部品、2:配線基板、3:配線パ
ターン、4:電極、5:はんだバンプ。
Claims (1)
- 配線パターンの形成された配線基板上にフリツ
プチツプ方式によりはんだ付けして実装される電
子回路部品のフリツプチツプ接続端子において、
部品側の各端子より引出した電極、並びに該電極
上に形成したはんだバンプの断面寸法を、各端子
毎にその端子の通電電流に対応した断面寸法に選
定して構成したことを特徴とする電子回路部品の
フリツプチツプ接続端子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986153335U JPS6359324U (ja) | 1986-10-06 | 1986-10-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986153335U JPS6359324U (ja) | 1986-10-06 | 1986-10-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6359324U true JPS6359324U (ja) | 1988-04-20 |
Family
ID=31072124
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986153335U Pending JPS6359324U (ja) | 1986-10-06 | 1986-10-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6359324U (ja) |
-
1986
- 1986-10-06 JP JP1986153335U patent/JPS6359324U/ja active Pending