JPS6358485U - - Google Patents

Info

Publication number
JPS6358485U
JPS6358485U JP15218386U JP15218386U JPS6358485U JP S6358485 U JPS6358485 U JP S6358485U JP 15218386 U JP15218386 U JP 15218386U JP 15218386 U JP15218386 U JP 15218386U JP S6358485 U JPS6358485 U JP S6358485U
Authority
JP
Japan
Prior art keywords
grid array
pin
pin grid
surface mounting
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15218386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15218386U priority Critical patent/JPS6358485U/ja
Publication of JPS6358485U publication Critical patent/JPS6358485U/ja
Pending legal-status Critical Current

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  • Connecting Device With Holders (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例であるLSIソケ
ツトによる実装態様を説明するための斜視図、第
2図は従来のピングリツドアレイ用ソケツトによ
る実装態様を説明するための斜視図である。 図において、1―1……ピングリツドアレイL
SIソケツト、1―2……コンタクト、1―3…
…フラツトリード、1―4……ピングリツドアレ
イパツケージ、1―5,2―3……リードピン、
1―6,2―2……プリント印刷配線基板、1―
7……パツド、2―1……ピングリツドアレイ用
ソケツト、2―4……スルーホールである。なお
、各図中、同一符号は同一、又は相当部分を示す
FIG. 1 is a perspective view for explaining the implementation using an LSI socket which is an embodiment of this invention, and FIG. 2 is a perspective view for explaining the implementation using a conventional pin grid array socket. In the figure, 1-1...pin grid array L
SI socket, 1-2...Contact, 1-3...
...Flat lead, 1-4... Pin grid array package, 1-5, 2-3... Lead pin,
1-6, 2-2...Printed wiring board, 1-
7... Pad, 2-1... Pin grid array socket, 2-4... Through hole. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] チツプキヤリヤ、フラツトパツケージ等の表面
実装用のプリント印刷配線基板等にピングリツド
アレイパツケージを実装するためのLSIソケツ
トにおいて、このLSIソケツトに、前記ピング
リツドアレイパツケージのリードピンを挿入する
ためのコンタクトと、表面実装用に形成されたリ
ードとを備えたことを特徴とするLSIソケツト
In an LSI socket for mounting a pin grid array package on a printed wiring board for surface mounting such as a chip carrier or a flat package, a contact for inserting a lead pin of the pin grid array package into the LSI socket. and a lead formed for surface mounting.
JP15218386U 1986-10-03 1986-10-03 Pending JPS6358485U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15218386U JPS6358485U (en) 1986-10-03 1986-10-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15218386U JPS6358485U (en) 1986-10-03 1986-10-03

Publications (1)

Publication Number Publication Date
JPS6358485U true JPS6358485U (en) 1988-04-19

Family

ID=31069934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15218386U Pending JPS6358485U (en) 1986-10-03 1986-10-03

Country Status (1)

Country Link
JP (1) JPS6358485U (en)

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