JPS6357809B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock switching circuit that selects and outputs any one clock from a plurality of input clocks.

A tester that tests semiconductor integrated circuits needs to generate various timings. Therefore, it is common to prepare a plurality of clocks, select a necessary clock from among them, and synthesize a timing waveform. The accuracy of this synthesized timing waveform depends on the accuracy of the original clock. For this reason, the tester accurately adjusts the cable length, or propagation time, for each clock in order to match the skew of multiple clocks. However, differences in cable propagation time are not the only cause of skew. For example, skew also occurs due to variations in propagation time of driver circuits that drive each clock. Moreover, the characteristics of circuits that mainly use semiconductor elements, such as driver circuits, are greatly affected by fluctuations in ambient temperature and power supply voltage. For these reasons, the reality is that conventionally it has not been possible to achieve sufficient skew alignment.

The above-mentioned problems are not limited to semiconductor integrated circuit testers, but also apply to various electronic devices that selectively use multiple clocks.
This has become a major issue.

SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a clock switching circuit which can always provide a clock with the correct phase no matter which one of the clock groups is selected.

However, in the clock switching circuit according to the present invention,
In accordance with the address signal, the clock selection circuit selects one clock of the input clock group and outputs it to the variable delay circuit, while at the same time addressing the memory circuit with this address signal. The delay time in the variable delay circuit is controlled by the output signal of the memory circuit. Further, a phase correction signal related to the phase difference between the input clock or output clock of the variable delay circuit and the reference clock is generated by the phase correction circuit, and this signal is applied to the data input of the memory circuit. According to this configuration, even if a phase variation occurs in each clock of the input clock group, this phase is corrected through the variable delay circuit, and a clock whose phase is always aligned with the reference clock is obtained at the output of the variable delay circuit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a clock switching circuit which is an embodiment of the present invention. The clock selection circuit 1 is supplied with a plurality of input clocks 8 ₁ to 8 _o and an address signal 7 for clock selection. The output clock of the clock selection circuit 1 is input to a digitally controlled variable delay circuit 2. The address signal 7 for clock selection is also supplied to the address input of the memory circuit 3, so that addressing corresponding to the selected clock of the input clocks ₈₁ to _8o is performed. The output signal 9 of the memory circuit 3 is applied to the control input of the variable delay circuit 2.

The time difference measuring circuit 5 and the adder 6 output a phase correction signal 10 related to the phase difference between the output clock 11 of the variable delay circuit 2, that is, the output clock of the clock switching circuit, and the reference clock 12 output from the reference clock generator 4. It constitutes a phase correction circuit that creates The time difference measuring circuit 5 has an output clock 11.
The time difference, that is, the phase difference between the reference clock 12 and the reference clock 12 is detected and a signal corresponding to the detected time difference is output. The adder 6 adds the output signal of the time difference measuring circuit 5 and the output signal 9 of the memory circuit 3, and outputs a phase correction signal 10.

The phase correction signal 10 is applied to the data input of the memory circuit 3 and written to the address designated by the address signal 7. In this embodiment, the memory circuit 3 and each part are of a digital type, and each signal is a digital signal.

Now, suppose that the address signal 7 is switched and the clock selection circuit 1 newly selects one of the input clocks 8 ₁ to 8 _o , 8 _i . At this time, the contents of the corresponding address i of the memory circuit 3 are simultaneously read out, and the variable delay circuit 2 delays the clock 8 _i by a time determined by the memory circuit output signal 9 and sends out the clock 8 i as the output clock 11. And the output clock 11 at that time
The result of adding the signal corresponding to the phase difference between the clock signal and the reference clock 12 and the memory circuit output signal 9 is applied as a phase correction signal 10 to the data input of the memory circuit 3 and written to address i. Then, in the next read cycle, the contents of the address i of the memory circuit 3 are read out, and the delay time of the variable delay circuit 2 is readjusted accordingly. The result is reflected in the phase correction signal 10, and the contents of the address i in the memory circuit 3 are rewritten. In this way, the output clock 11 is phase-aligned with the reference clock 12, and the phase correction signal 10 in this state is stored at address i of the memory circuit 3. The above operation will be explained in detail using FIG. 3. In the following example, for the sake of simplicity, it is assumed that the input clock 8i has the same frequency as the reference clock, but its phase is shifted by 2/8 cycle. It is also assumed that 4 ₈ is initially stored at address i of the memory circuit 3. When address signal 7 is applied to memory circuit 3, the contents of address i are read out, and variable delay circuit 2 receives 4 ₈
control signal is input, input clock 8i is 4/8
It is output as the output clock 11 with a cycle delay. Since the phase difference between the output clock 11 and the reference clock is 6/8 cycles, the time difference measuring circuit 5 outputs ₆₈ . Then, the adder 6 adds this 6 ₈ and the output signal 4 ₈ of the memory circuit 3 to output 2 ₈ (provided that the adder 6 does not have an octal digit). By this data, memory circuit 3
The contents of address i are rewritten to 2 ₈ . Next, the contents of address i in memory circuit 3 are read out, ₂₈ control signals are input to variable delay circuit 2, and input clock 8i is output with a delay of 2/8 cycles. At this time, since the phase difference between the output clock and the reference clock is 4/8 cycle, the time difference measuring circuit 5 outputs ₄₈ . Then, the adder 6 adds this 4 ₈ and 2 ₈ in the memory circuit 3 to output 6 ₈ , and the contents of address i in the memory circuit 3 are rewritten to 6 ₈ . Similarly, variable delay circuit 2 delays input clock 8i by 6/8 cycles and outputs it. Here, the output clock 11 is synchronized with the reference clock, the time difference measuring circuit 5 outputs ₀₈ , the adder 6 outputs ₆₈ , and the contents of address i of the memory circuit 3 are fixed at ₆₈ , and this state becomes stable. In this way, no matter what is initially stored at the address i of the memory circuit 3, the output clock 11 synchronizes with the reference clock after several feedbacks and becomes stable in this state.

Even if the delay characteristics of the driver circuit, etc. of the selected input clock _8i change during the process, the resulting phase shift is automatically corrected by adjusting the delay time of the variable delay circuit 2, and the phase correction signal at that time is 10 will be stored at address i of the memory circuit 3.

Even when the address signal 7 is switched and another input clock is selected, the output clock 11 is phase aligned with the reference clock 12 in the same manner as above.

Once each of the input clocks 8 ₁ to 8 _o is selected and phase-aligned, the phase correction signal 10 at that time is stored at the corresponding address in the memory circuit 3. Therefore, for example, when the input clock 8 _i is selected again, the output clock 11 immediately completes phase alignment unless there is a phase fluctuation of the input clock 8 _i . Of course, even if a phase shift occurs, it can be quickly matched in phase by the above-described procedure.

If the memory circuit 3 is configured using a non-volatile memory element, clock phase alignment can be completed with virtually no time delay when the circuit power is turned off and then turned on again.

FIG. 2 shows a block diagram of another embodiment of the present invention.

This embodiment differs from the previous embodiment in the configuration of the phase correction circuit. That is, the input clock of the variable delay circuit 2 and the reference clock 12 are input to the time difference measuring circuit 5. The circuit 5 measures the time difference with this input clock based on the reference clock, and directly outputs the time as a phase correction signal 10 to correct the lead of the clock as a result. This time difference is stored in the memory circuit 3 and then read out from the same circuit 3 and applied to the variable delay circuit 2, and the input clock is synchronized with the reference clock by delaying the input clock by this time difference. Other than this, this embodiment is the same as the previous embodiment.

In this embodiment, the clock output from the clock selection circuit 1 is directly inputted to the time difference measurement circuit 5 without passing through the delay circuit 2, so the advantage is that phase fluctuations of the input clock can be corrected more quickly. There is. However, since the variable delay circuit 2 is not included in the feedback loop, its delay characteristics should be sufficiently stabilized.

Each of the above embodiments has been described as a digital circuit configuration. However, analog circuit configurations are also possible. In that case, the variable delay circuit 2 may be changed to an analog voltage or current control type circuit, and the memory circuit 3 may be changed to, for example, a sample-hold type analog memory circuit.

The clock switching circuit according to the present invention has the configuration described above, and can obtain an output clock whose phase shift is corrected no matter which one of the input clocks is selected. Therefore, many advantages can be obtained, such as eliminating the need for troublesome phase adjustment for each input clock.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing different embodiments of the clock switching circuit according to the present invention, and FIG. 3 is a time chart showing an example of the operation of the circuit shown in FIG. 1. 1... Clock selection circuit, 2... Variable delay circuit, 3
...Memory circuit, 4.Reference clock generator, 5.Time difference measurement circuit, 6.Adder, 7.Address signal,
8 ₁ to 8 _o ...input clock, 10...phase correction signal,
11...Output clock of the clock switching circuit.

Claims (1)

[Claims] 1 A clock selection circuit that selects and outputs one clock from a group of input clocks according to an address signal, a memory circuit that is addressed by the address signal, and a time controlled by the output of the memory circuit. A variable delay circuit delays and outputs the output clock of the clock selection circuit, and generates a phase correction signal related to the phase difference between the input clock or output clock of the variable delay circuit and a reference clock, and outputs the output clock by delaying the output clock of the clock selection circuit. A clock switching circuit comprising: a phase correction circuit supplied to an input, and configured to output a clock whose phase is aligned with the reference clock from the variable delay circuit no matter which input clock of the input clock group is selected.