JPH11289244A - Method for calibrating variable delay circuit and variable delay circuit performing the calibrating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute the calibration of delay time in a short time by updating a calibration table with a control signal value at which an error becomes smaller whenever the delay time of a variable delay circuit that is set by each control signal is measured. SOLUTION: An integer value k made by dividing a measured delay time Di by a nominal delay step ds and errors Rk ' and Rk+1 ' to two adjacent nominal delays ds k and ds (k+1) are calculated at the same time with measuring a delay time of a variable delay circuit. And, when a constant error Rk ' is an error Rk held in the k-th line of a calibration table or less, the Rk ' and CCi are overwritten as new data Rk and CCi in the k-th line and when it is a measurement error Rk+1 or less, (Rk+1 ' and CCi ) are overwritten an new data (Rk+1 and CCi ) in the (k+1)-th line. According to the processing, the calibration of the delay time that is desired for when the measurement of delay time about the whole control signal values CCi and the update of the calibration table have been finished is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of calibrating a variable delay circuit which can be applied to, for example, a timing generator used in an IC test apparatus, and a variable delay circuit calibrating by the method.

[0002]

2. Description of the Related Art Conventionally, a timing generator is provided in an IC test apparatus, and for example, a rising timing, a falling timing, etc. of a test pattern signal to be given to an IC under test are specified in accordance with a timing signal output from the timing generator. ing. In the IC test apparatus, various items of tests are performed, for example, by gradually shifting the rising and falling timings of the test pattern signal given to the IC under test, and measuring the range of the timing at which the IC under test operates normally. . For this reason, the timing generator is configured so that the generation of the timing can be finely changed.

FIG. 1 shows the basic configuration of a variable delay circuit.
M delay stages DY _{1 to} DY _M are M−1 multiplexers MUX ₁ to
MUX _M-1 are cascade connected via the output of the last delay stage DY _M is connected to the output terminal OUT via the multiplexer MUX _M. The delay amounts of the delay stages DY _{1 to} DY _M are differently weighted. In this example, the m-th delay stage DY _m is weighted by connecting 2 ^m delay elements DE having substantially the same delay amount d in series. Each delay element DE is, for example,
It is composed of an AND gate and has a delay amount of, for example, 1 to 2 psec. The output side and the input side of each of the delay stages DY _{1 to} DY _M are respectively connected to the input terminals A and B of the corresponding multiplexers MUX ₁ to MUX _M. Each of the multiplexers MUX _{1 to} MUX _M is connected to two input terminals A and B. One of the applied signals is selected and output according to the control signals c _{1 to} c _{M applied} to the terminal S. Here, H logic is given to the control terminal S so that the input terminal A
Is switched to the selected state, and when the L logic is applied, the input terminal B can be switched to the selected state. Therefore, when L logic is applied to all of the control input terminals T _{1 to} T _M , all of the multiplexers MUX _{1 to} MUX _M are switched to the input terminal B, and the delay time between the input terminal IN and the output terminal OUT becomes the minimum value. .
This minimum delay time is hereinafter referred to as an offset delay time.

If the delay amounts of all the delay elements DE are ideally equal to each other, according to the variable delay circuit of FIG. 1, the total delay amount from the input terminal IN to the output terminal OUT differs by the delay amount d. Can be set to 2 ^M ways. In that case, the range of the delay amount that can be set is 0 to d (2 ^M −1). Therefore, as shown in row A of FIG. 2, the delay resolution (minimum delay unit) required for the timing setting in the timing generator of the IC test apparatus is d _s = d, and the maximum delay amount is d _s (2 ^M If -1), a desired delay amount can be set over a required range in the minimum delay unit required by the configuration shown in FIG. The scale in d _s shown in row A of FIG. 2 is referred to herein as a nominal delay scale and its value D _s1 , D _s2 , D _s3,.
Is referred to as the nominal delay value.

However, actually, the delay of each delay element DE is
The extension amount d varies, and the portion other than the delay element DE
The delay due to the connection line is also added. So, actually, N
Nominal delay setting by bit delay setting signal CS
Is the nominal delay required for the variable delay circuit.
Ability d_sAnd the nominal maximum delay, that is, the maximum variable delay range d_s(2 ^N-
Regarding 1), as shown in row B of FIG.
The delay amount d of_sMuch smaller, for example less than half
And d (2^M-1)
Maximum delay d_s(2^N-1) Determine the value of M to be larger
M bit 2 of control signal CC^M-1 for all settings
The amount of delay was measured and the nominal delay on the nominal scale in row A of FIG.
Delay value D_s1, D_s2,… And the delay that minimizes the error
The control signal value CC is determined in advance and used.

However, since the delay amount of the delay element DE varies as described above, the nominal delay setting values 0 psed, 10 psec,
It is necessary to determine a control signal value CC that minimizes the error of the actual delay time for 20 psec, 30 psec,. Also,
When the delay stages DY ₁ , DY ₂ , DY ₃ ,... Are composed of semiconductor elements or the like, the delay time changes according to the temperature change. Therefore, to interrupt the tests each time a predetermined time has elapsed since startup or activation of the conventionally IC tester, measures the delay time by all combinations of delay stages DY ₁ ~DY _M while the interruption Then, an optimum delay stage combination (ie, control signal value CC) that minimizes the error with respect to the nominal set delay amount is determined from the measured delay times, and the relationship between the actual delay time and the nominal delay amount is as linear as possible. It is calibrated to be close to.

FIG. 3 shows an example. In the example shown in FIG. 3, a converter 11 is provided for a control signal or the like, and the converter 11 converts a nominal delay setting signal CS into a control signal value CC for selecting a combination of delay stages obtained by measurement, which minimizes an error. Converted,
Multiplexer MUX ₁ by this converted control signal value CC
This shows a case where a configuration is made such that ~ MUX _M is controlled. FIG. 4A shows an example of the measurement result of the delay time corresponding to the value of each control signal CC. In this example, the required nominal minimum delay step (resolution) _ds is 10 psec, and the delay time up to a maximum of 1 nsec can be set in a nominal 10 psec step. The delay amount of each delay element DE is about 2 psec, and the multiplexers MUX ₁ to MUX _M are controlled by controlling the control signal value CC = (c ₁ , c ₂ , c ₃ ,..., C ₁₀ ) of M = 10 bits. Signal value CS from 0 to 2 ¹⁰ -1
, And the delay time was measured. When the control signal value CC is 7 and 8, and 23 and 24, the magnitude of the delay time is reversed. Conventionally, when the measured value of the delay time is obtained, sorting (reordering) is performed in the direction of increasing the delay time from the smaller value to the larger value, and the arrangement is changed as shown in FIG. 4B. The value of the control signal CC to which each delay time is given at the time of executing the sorting is also rearranged in accordance with each delay time.

[0008] From the rearranged delay times, a delay time arranged in a state close to a required interval of, for example, d _s = 10 psec is selected, and the value of the control signal CC accompanying the selected delay time is determined. In order, the nominal delay set value CS of the calibration table (Fig. 4C)
And the calibration table of CS vs. CC is converted to the converter 11
To memorize. That is, the nominal delay setting signal CS is connected to the converter 1
If you enter a 1, the nominal delay setting signal value control signal CC converted by output of CS, by controlling the multiplexer MUX ₁ ~MUX _M by the control signal CC, the delay time closest to the ideal value at the time Is given.

[0009]

[SUMMARY OF THE INVENTION After Conventionally, as described above of measuring the delay time of each delay stage DY ₁ ~DY _M, performs reordering to sort the delay time, reordering sequence of the delay time The method of obtaining the conversion data CC by selecting an array of delay times that change at a predetermined pitch from among them has the disadvantage that the processing takes time.

That is, since an actual IC test apparatus is provided with a large number (1500 to 2000) of variable delay circuits 100 shown in FIG. 3, it takes time to calibrate the delay time of each variable delay circuit. Become. Further, an array of measured delay times,
Since a processing method of obtaining the converted data CC while storing the array of the delay times after the rearrangement and the array of the delay times arranged at a predetermined pitch from the array is employed, for example, 10
If it is attempted to simultaneously calibrate the delay times of about zero variable delay circuits, the processing cannot be performed unless the storage area of the memory is occupied significantly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a calibration method and a variable delay circuit capable of performing a calibration operation in which the calibration of the delay time of the variable delay circuit can be completed in a short time and the memory area is not occupied widely. It is.

[0012]

According to the present invention, according to the present invention,
Different weighted cascades through a multiplexer
Cascade connection of M delay stages controlled by control signal value
The predetermined minimum nominal delay step d_sNominal delay varies with
Quantity D_sVariable delay circuit that generates the calibration delay amount corresponding to
In the calibration method, each given control signal value CC_i Against
Measured delay amount D_iThe minimum nominal delay step of the variable delay circuit.
D_s, And the value k of the integer part of the obtained quotient
Two nominal delays D_sk, D_{sk + 1}And second error R with_k= D
_i-d_sk, R _{k + 1}= d_s-R_kAnd calculate the first error R_kIs the first in the calibration table
The k-th row is held corresponding to the nominal setting signal value CS = k
It is determined whether the error is less than or equal to the error.
The first error R calculated in the column of_kAnd the control signal that gave it
Signal value CC_i , And the second error R_{k + 1}Is in the calibration table
In the k + 1th row, the nominal setting signal value is held corresponding to CS = k + 1.
It is determined whether the error is less than or equal to
The second error R calculated in the column of one row_{k + 1}And gave it
Control signal value CC_i From i = 0 to i = 2^M-1
By executing the above, from the 0th line to the Kth line of the calibration table
Control to minimize the error with respect to the above nominal delay
A signal value is generated corresponding to the nominal setting signal value CS.

As described above, according to the present invention, each calibration signal is applied, and every time the delay time of the variable delay circuit set by the control signal is measured, the calibration table is updated with the control signal value that reduces the error. Therefore, the sorting process does not need to be performed, and therefore, the calibration of the delay time can be executed in a short time. Further, since the calibration table is directly updated, the data storage area is only required to hold the error value and the control signal value. Furthermore, since it is sufficient to provide an address for the number K of the nominal setting signal value CS _i give nominal delay amount, area of the storage area be small compared with the prior art.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, two adjacent nominal delay values D _sk , D used in the principle of the calibration method according to the present invention.
error R _k of the measurement delay time D _i for _{sk + 1,} will be described with reference to FIG. 5 R _{k + 1.} As shown in FIG. 5, row A, the nominal delay value D _s1 , D _s2 , D _s3 , for each nominal delay step d _s (constant value)
… Is set by an M-bit control signal CC,
5, to measure the delay time D _i of sufficiently small minimum variable delay per step d from d _s as shown in row B. The delay time D _i
The nominal delay values D _sk and D _{sk + 1} (D _sk ≦ D _i ≦
Error R _k for D _s and _{k + 1),} obtained by the R _{k + 1} as given below.

K = int [D _i / d _s ] (1) Here, int [a / b] means a value of an integer part of a / b. Error with respect to D _sk : R _k ′ = D _i −d _sk (2) Error with respect to D _{sk +1} : R _{k +1} ′ = D _{sk +1} −D _i = d _s −R _k ′ (3) The magnitude of the delay time of the variable delay circuit 100 set by the signal is almost equal to the control signal value CC _i = i = 0, 1, 2,
Perform ..., becomes larger in the order of 2 ^M -1, delay stages DY ₁ is actually a delay time D _i obtained having a delay with a variation deviates from the ideal value, DY _2, ..., a combination of DY _M So
i values order does not coincide with the order of D _i necessarily the entire region.

[0016] The error R _k 'is also the remainder of the time obtained by dividing the D _i in d _s. The value k (= 0, 1, 2,…, K) is the nominal delay value D _s0 , D
_s1 , _Ds2 , ..., _DsK correspond to the numbers. When the minimum variable delay step of the variable delay circuit can be set by the M-bit control signal CC _i and d, and has a ^{_{Kd s <(2 M -1)}} d. FIG. 6 is a flowchart showing the procedure of the delay calibration method according to the present invention applied to the variable delay circuit shown in FIG. 10 described later.
In the present invention, as shown in FIG. 7, K + 1 nominal delay values 0,
_{d s, 2d s, 3d s} , ..., error R _k between the respective nominal delay value to the nominal setting signal value CS = 0 to K of Kd _s D _k = kd _s and the measured delay value D _i
When, the measured delay value D control signal _i is set to the delay stage DY ₁ ~DY _M that caused the value _{CC i = (c 1, c} 2, ..., c M) prepared in advance calibration table for writing . That is, CS = k = 0, 1, 2,..., K in a memory (memory 12B in FIG.
In response to setting the area of the calibration table to write the error R _k and sets the control signal value CC _i. Further, in this embodiment, to the control signal value CC _i set in the variable delay circuit of FIG. 3, input terminal IN of the variable delay circuit 100 shown in FIG. 10, OU
The measured delay time between T is represented by t _di , and the measured delay time t _{di is} subtracted from the offset delay time t _d0 (control signal value CC ₀ = 0
The delay value obtained by removing the measurement delay time when
Calibration shall be performed for D _i = t _di -t _do .

[0017] Step S1: is written to any initial value R _s column above pre d _s corresponds to the value of all k is the error R of the calibration table. Step S2: M-bit control signal CC ₀ = 0 when i = 0
(= 0, 0, 0, ..., 0) is set to the multiplexer MUX ₁ ~MUX _M,
The delay time at that time is measured as an offset delay t _d0 .

[0018] Step S3: Set the control signal value CC _i,
The delay time t _di is measured. Step S4: Obtain a measured delay value D _i = t _di -t _d0 . Step S5: The measurement delay value D _i is divided by the nominal delay resolution (minimum variable delay step) d _s, obtaining a remainder R _k '= D _i -kd _s and the quotient _{k = int [D i / d} s]. As shown in FIG.
R _k ′ is the error of the measured value D _i with respect to the CS = k th nominal delay value D _sk = k d _s . Further, CS = k + 1th nominal delay value _{Dsk + 1}
= (K + 1) d _s An error R _{k + 1} '= d _s -R _k ' is obtained.

Step S6: The error R is read from the CS = kth row of the calibration table. Step S7: It is determined whether R _k ′ ≦ R and 0 ≦ k ≦ K. If the result of the determination is YES, the process proceeds to step S8, and if NO, the process proceeds to step S9. Step S8: If the judgment result is YES, CS = k in the calibration table
Overwriting the error R 'as a new error R in the column of row error, overwriting the control signal value CC _i in the column of the control signal value.

Step S9: The error R is read from the (k + 1) th row of the calibration table. Step S10: Determine whether R _{k + 1} ′ ≦ R and 0 ≦ k + 1 ≦ K. If the result of the determination is YES, the process proceeds to step S11, and if NO, the process proceeds to step S12. Step S11: If the judgment result is YES, k + 1 of the calibration table
Overwriting the error R _{k + 1} 'as a new error R in the column of row error, overwriting the control signal value CC _i in the column of the control signal value.

Step S12: It is determined whether CC = i has reached 2 ^M -1. If it has reached, the calibration process ends, and if it has not reached, the process proceeds to step S13. Step S13: Step i and return to step S3. With the above calibration processing, all M-bit control signal values CC _i =
(c ₁ , c ₂ ,…, c _M ) (i = 0,1,2,…, I, where I = 2 ^M -1) delay time measurement result, calibration to minimize error is completed I do. As a result, the calibration table of FIG.
d _s K control signal value CC _i which the smallest error with respect to the nominal delay value D _s k for each nominal delay resolution d _s to obtain. Usually Yes choose the delay amount d of the delay element DE to less than half compared to the delay resolution d _s, the number of steps by the delay resolution d _s to cover the maximum delay range of the variable delay circuit shown in calibration table of FIG. 7 K
Compared to the total set number of control signal values for the delay stages DY ₁ ~DY _M
2 ^M -1 is a very large value. Therefore, as shown in FIG. 4A, the conventional calibration method requires a large-sized table for holding the measured delay time with respect to the setting of 2 ^M -1 control signal values. Calibration tables require only tables of very small size. Moreover, in this invention, if necessary to sort the measurement delay time, it is not necessary to sample at a nominal delay resolution d _s.

FIG. 8 shows an example of processing performed according to the procedure shown in FIG. The nominal delay value step (delay resolution) d _s to be calibrated is d _s = 10 psec, and the delay stages DY ₁ to DY ₅ are as follows: DY ₁ : 3.1 psec DY ₂ : 4.7 psec DY ₃ : 8.8 psec DY ₄ : 14.3 psec DY ₅ : Assume that it is 33.1 psec. The delay stages DY _{6 to} DY _M have arbitrary values. On the other hand, it is assumed that the error R _k as the offset delay d _of held in the k = 0th row of the calibration table to be created is zero.

[0023] The measurement delay time D _i was 10psec division, the integer part of the quotient and k. Nominal delay value 10k measured delay time D _i (pse
is shown in each column of the table of Figure 8 'error R _{k + 1} and for the nominal delay value 10 (k + 1)' error R _k for c). As described above, by the method of the present invention, if the error R _k or less that measured for the control signal value CC _i the error R _k 'is held in the k-th row of the calibration table, k rows of the calibration table The eye error R _k and the control signal value CC _i are updated with the measurement error and the control signal value, and the measurement error R _{k + 1} ′ is the error held in the k + 1 row of the calibration table.
If R _{k + 1} or less, and updates the error R _{k + 1} and the control signal value CC _i in calibration table k + 1 th row in the measurement error and the control signal value.

[0024] In FIG. 8, a k = 0 in the control signal value CC _i is 0 to 4, delay in CC _i = 0 (offset delay)
Is assumed to be 0, the error R _k = 0 at this time and the control signal value
CS _i is held in the k = 0th row of the calibration table. FIG.
Are repeated from i = 0 to i = 4, R _{k + 1} = 1.2 and CC _i = 4 are held in the k + 1 = 1st row of the calibration table. When CC _i = 5 (i.e., i = 5), k = 1, and the error R _k '=
Comparing 1.9 with R _{k +1} = 1.2 when k = 0, the latter is smaller, so the data in the k = 1 row of the calibration table is not updated, but k + 1 = the second row is R _{k + 1} '= 10 (initial value), so R _{k + 1} ' = 8.1
And CC _i = 5 are overwritten.

In the measurement of CC _i = 5 to 10, all errors R _k are 1.2
Because it is larger, the k = 1 row of the calibration table is not updated. On the other hand, the row k + 1 = 2 is sequentially updated by the measurement of CC _i = 5 to 7, but at CC _i = 8, the measured error R _{k + 1} '= 5.7 is the value of k + in the calibration table. Update is not performed because it is larger than R _{k + 1} = 3.4 held in the first row. Due to the measurement of CC _i = 9, 10, the update occurs again in the row k + 1 = 2. Eventually, CC _i = 10 and R _{k + 1} = 1.0,
CC _i = 10 is stored in the calibration table at row k + 1 = 2. CC _i = 11-14
In k = 2 and is made, the data R when the k = 1 error R _k 'are both in the meantime is already held in the second row _{k + 1} =
Since it is larger than 1.0, the data in the k = 2nd row (R _{k + 1} =
1.0, CC _i = 10) is held in the k = 2nd row, but an update occurs in the k + 1 = 3rd row. At CC _i = 15, k = 3. The error R _k '= 0.9 at this time is the error R when k = 2 held in the k = 3rd row.
_{k + 1} '= 2.2, so the row k = 3 in the calibration table has data (R _k
= 0.9, CC _i = 15). Thereafter, the data of the k = 3rd row is retained until CC _i = 18, but the data R _{k + 1} ,
CC _i is updated sequentially.

The calibration table shown in FIG. 9 is obtained as a result of the processing of FIG. The table in FIG. 8 is shown for explaining the process of creating the calibration table in FIG. 6, and a memory area corresponding to such a table is not required. The required memory area corresponds to the calibration table in FIG.
A characteristic of the present invention is that the calibration table of FIG. 9 is automatically obtained by repeatedly executing the comparison determination and the update described with reference to FIGS.

FIG. 10 shows an embodiment of the variable delay circuit 100 using the above-described calibration method. The delay time measuring unit 13 measures the time difference between the input signal supplied to the input terminal IN of the variable delay circuit 100 and the signal output to the output terminal OUT to measure the delay time of the variable delay circuit. Controller 1
Enter 2 The controller 12 is constituted by, for example, a microcomputer, and has an arithmetic unit 12A and a memory 12B. The memory 12B is provided with an area for creating the above-mentioned calibration table. Also in the memory 12B, is applied to the program for executing the calibration method is stored, the arithmetic unit 12A measures a delay time given by the delay time measuring unit 13 D _i shown in FIG. 6, the calibration according to the program Execute the process. That is, the arithmetic unit 12A divides the delay time D _i by the minimum resolution d _s of the variable delay circuit 100 which is set in advance, the integer value k and the error value R _k, to calculate the R _{k +1.} And the calculated value, writes the value of the control signal CS _i in calibration table of Figure 7 provided in the memory 12B, creating a calibration table. After the completion of the calibration table, the relationship between the input control signal value CS _i (that is, the value of k) and the control signal value CC that minimizes the error is read out from the calibration table and written into the converter 11.

When the timing of the IC test pattern is set as desired using the variable delay circuit 100 shown in FIG. 10, when a control signal CSi designating the desired timing is applied to the terminals T1 to TN, the converter 11 controls the corresponding control. reads the signal CC, supplied to the multiplexer MUX ₁ ~MUX _M, it can be set with high accuracy delay amount.

[0029]

As described above, according to the present invention,
At the same time as measuring the delay time of the variable delay circuit,
Delay time D_iThe nominal delay step d_sInteger k divided by
Two adjacent nominal delays d_sk, d_sError R for (k + 1)_k', R
_{k + 1}'And determine the measurement error R_k'Is stored in row k of the calibration table
Error R_kR if_k', CC_iThe new data R_k,
CC _i To the k-th line, and the measurement error R_{k + 1}'Is the calibration table
Error R held in the k + 1th row of_{k + 1}If (R
_{k + 1}', CC_i) With new data (R_{k + 1}, CC_iLine k + 1
Overwrite According to this processing, all control signal values CC
_i Measurement of delay time and update of calibration table have been completed
The calibration of the delay time required for the stage has been completed, and
The delay time of each switching state of the variable delay circuit
And then sort the delay time in ascending order.
Since there is no need to do this, even if there are many variable delay circuits,
Correct operation can be completed in a short time.

Further, in order to store the error R _k and the control signal CC _i shown in FIG. 9 in the memory 12B of the controller 12 in correspondence with k is the nominal minimum delay corresponding to the k = 0 to k = K the number K of step d _s may be provided address. For example, as described above, the variable delay circuit starts at 0 in steps of 10 psec.
When changing to 1nsec, K = 100. Therefore, even if the calibration of many variable delay circuits is performed, the storage area used as a whole can be reduced. On the other hand, in the conventional method, M
Since it is necessary to hold the measured data for all the values of the bit control signal values in the memory, at least 2 ^M -1 addresses are required. For example, in the case of a control signal of M = 10 bits, the required number of addresses is about 1000.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional variable delay circuit.

FIG. 2 is a diagram for explaining a conventional method of calibrating a variable delay circuit.

FIG. 3 is a block diagram for explaining an example of a conventional variable delay circuit provided with a converter having a calibration table.

FIG. 4 is a table for explaining a processing example according to a conventional variable delay circuit calibration method.

FIG. 5 is a diagram for explaining a delay error used in the present invention.

FIG. 6 is a flowchart for explaining a calibration processing procedure of the variable delay circuit according to the present invention.

FIG. 7 is a diagram showing a calibration table created by the present invention.

FIG. 8 is a table for explaining a processing example according to the calibration method of FIG. 5;

FIG. 9 is a view showing an example of a calibration table created by the processing of FIG. 8;

FIG. 10 is a block diagram showing an embodiment of a variable delay circuit including a controller for executing a calibration operation according to the method of calibrating a variable delay circuit according to the present invention.

Claims (8)

[Claims] The desired control signal value CC _i from claim 1] 0 to K, and the switching control cascaded state of M different weighted delay stage, a variable delay circuit for setting a desired delay amount, Nominal delay amount D _sk = d _s k, for each nominal minimum delay step d _s
k = 0, 1, 2,..., K, M and K are methods for calibrating for integers greater than or equal to 2 and include the following steps: (a) An error in memory and a control signal giving the error in advance defining a calibration table of at least K rows having a field for holding values, respectively, to measure the delay amount D _i of the variable delay circuit which is set by (b) control signal value CC _i, is measured (c) the delay amount D _i divided by the minimum nominal step d _s, and the integer part k of the quotient of the measured delay amount D _i, two adjacent nominal delay amount D _sk, the first and for the D _{sk + 1} Calculate the second error R _k = D _i -d _sk , R _{k + 1} = d _s -R _k , and (d) the calculated first error R _k is stored in the k-th row of the calibration table. It is determined whether or not the error is equal to or less than the first error _Rk, and if so, the first error R _k calculated in the column of the k-th row and the control signal value CC _i given thereto are overwritten, and (e) the second error R _{k + 1} K-th of the calibration table + 1
It is determined whether the error is equal to or less than the error held in the row, and if it is, the second error R _{k + 1} calculated in the column of the k + 1th row is determined.
And overwriting the control signal value CC _i gave it, (f) the step (b) ~ a (e), by executing the i = 0 to i = 2 ^M -1, the K from row 0 In each row, a control signal value that minimizes an error with respect to the nominal delay amount is obtained. 2. A calibration method according to claim 1, the step the step (a) is to be written a certain value or more in advance the nominal delay step d _s in the column of the error of the calibration table as the initial value Including. 3. The calibration method according to claim 1, wherein the control signal value CS ₀ causes all the delay stages to be bypass-connected.
If the delay time t _do between the input and output of the variable delay circuit when is given as an offset delay, the above step (b)
, For each said control signal value CS _i, the delay time t _di between the input and output of the variable delay circuit is measured, comprising the steps obtained by the following equation D _i = t _di -t _do the delay amount D _i . 4. The calibration method according to claim 1, wherein the weight of the delay of the m-th stage, m = 1, 2,..., M, is approximately 2 ^m-1. I have. 5. A minimum nominal delay step according to a control signal value.
a variable delay circuit for generating a delay that is calibrated to correspond to the nominal delay delay D _sk for each d _s, and M delay stages having a delay amount that is weighted differently, the output side of the M delay stages And M multiplexers for selecting and outputting an input and an output to each delay stage, and a set of the M delay stages and multiplexers are cascade-connected. depending nominal delay amount for each minimum nominal delay step to the M delay stages given to the generated the multiplexer the desired control signal value from 0 to K and D _sk = d _s k,
k = 0, 1, 2,..., K, M and K are control signal conversion means for setting a desired delay amount corresponding to an integer of 2 or more, each time the control signal value is changed from 0 to K A delay time measuring means for measuring a delay time between input and output of the variable delay circuit, and at least K rows of calibration tables each having a column for holding an error and a control signal value giving the error in advance are defined therein. a memory, for each control signal value CC _i given, the delay amount D _i measured by the delay time measuring means is divided by the minimum nominal delay step d _s of the variable delay circuit, the resulting quotient integer Of the value k of the part and two adjacent nominal delay amounts D _sk and D _{sk +} 1
And second error _{R k = D i -d s k} , calculates a _{R k + 1 = d s -R} k, error below said first error R _k are held in the k-th row of the calibration table And if it is the following, the first error R _k calculated in the column of the k-th row and the control signal value CC _i given the first error R _k
And the second error R _{k +1} is the same as the k +
It is determined whether the error is equal to or less than the error held in the first row, and if it is, the second error R calculated in the column of the (k + 1) th row is determined.
By overwriting _{k + 1} and the control signal value CC _i given the same from i = 0 to i = K, the above-mentioned nominal delay amounts are respectively changed from the 0th row to the Kth row of the calibration table. On the other hand, a control signal value that minimizes the error is generated, and the control signal value held in each row k, k = 0, 1, 2,... And an arithmetic means for storing in the control signal converting means. 6. The variable delay circuit according to claim 5, wherein a fixed value of the nominal delay step _ds or more is previously written as an initial value in an error column of the calibration table in the memory. 7. The variable delay circuit according to claim 5, wherein a control signal value for bypass-connecting all the delay stages.
Assuming that the delay time t _do between the input and output of the variable delay circuit when CC ₀ is given is an offset delay, the delay time measuring means inputs the variable delay circuit with respect to each of the control signal values CC _i. measuring the delay time t _di between the outputs, the arithmetic means obtains the delay amount D _i as the following equation D _i = t _di -t _do. 8. The variable delay circuit according to claim 5, wherein the weight of the delay of the m-th stage, m = 1, 2,..., M, is approximately 2 ^{m -1.} ing.