JPS6355100B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In order to process image information at high speed, a device that performs parallel processing using a plurality of processors is generally used. In this case, the target image information is divided into several areas, and each processor is in charge of each area, and processes are performed in parallel while performing synchronous communication and information transfer with each other, but the information transferred here The amount is relatively large. The present invention does not relate to a parallel processing device itself, but rather to a high-speed information transfer device between processors that perform parallel processing.

In image processing, an apparatus having the configuration shown in FIG. 1 is generally used. An image captured by an imaging device 1 such as a television camera is sampled by a sample hold circuit 2, quantized, and stored in an image memory 3.
is stored in After the parallel image processing device 4 performs processes such as differentiation, smoothing, and thinning on the image information in the image memory 3, the results are stored in the image memory 5. The information in the image memory 5 is displayed on a monitor television 7 via a digital-to-analog converter 6, for example.

Conventionally, high-speed image information transfer devices within the parallel image device 4 can be roughly divided into (1) devices that transfer data from a processor via an input/output port, etc., and (2) devices that transfer information between memories without going through a processor. A device that performs DMA transfer is used. The device (1) is not practical when the amount of information is large because it takes time. Further, typical devices in (2) include those that use a common bus and those that use a ring data bus. In a transfer device using a common bus, each memory is usually coupled to the common bus via a buffer, and a bus controller or a bus management processor manages the common bus. Since priority occurs in communication between processors, there is a drawback that as the number of processors increases, the waiting time of each processor increases. Furthermore, as the number of processors increases, the amount of management function information such as information transfer requests and synchronization handled by the bus controller or management processor increases, and the processing of this information by the bus controller becomes considerably complex. Transfer devices using a ring data bus have simple communication procedures, but the amount of information that can be transferred per unit time is limited.As the number of processors increases, the information that can be transferred between processors without waiting time is The amount of data decreases, making it unsuitable for high-speed transfer of large amounts of information such as image information.

In the present invention, when transferring image information, information on management functions is transferred via a ring data bus,
It is an object of the present invention to improve the above drawbacks by transferring image information via a common bus.

The present invention includes a first image memory 3 in which image information to be processed is stored, a parallel image processing device 4 that processes the image information in the first image memory 3, and results processed by the parallel image processing device 4. In this device, the parallel image processing device 4 transfers image information and connects to the first and second image memories 3 and 5. a circular common bus 16 for transferring management function information such as synchronization and transfer requests; and a plurality of units coupled to the common bus 16 and the ring data bus 15. 13a to 13d, and each unit 13a to 13d has an internal bus 12a connected to the common bus 16 and the ring data bus 15, and an internal bus 12a interposed between the internal buses 12a and the common bus 1
a buffer 19a that can be separated into the ring data bus 15 side and the ring data bus 15 side; a processor 8a that is connected to the internal bus 12a on the ring data bus 15 side from the buffer 19a;
unit image memory 10a for storing image information stored in each area 29a to 29d divided into a number equal to the number of units of the first image memory 3, and a common bus than the buffer 19a. Internal bus 1 on the side
2a, and stores image information of boundary areas 301 to 308 near the boundaries among the areas 29a to 29d.
The communication memory 11a is
Such a communication memory 11a has the same capacity for each unit and stores the same contents at the corresponding address, and the internal bus 1 on the common bus side of the buffer 19a.
It has a DMA controller 22a that is connected to the unit 2a and operates according to instructions from the processor 8a, and stores the processing results in the unit image memory 10a for parallel processing by the processor 8a of each unit 13a to 13d. The processor 8a transfers management function information via the ring data bus 15. All units 13a to 13d
A high-speed method for transmitting image information, etc., to the communication memory 11a of the unit, opening the buffer 19a, and processing the image information using the unit image memory 10a and the communication memory 11a by the processor 8a. It is a transfer device.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a diagram illustrating the configuration of the parallel image processing device 4 shown in FIG. 1. This device 4
are four units 13a, 13b, 13c, 1
3d is the ring data bus 15 and the common bus 16
The image memories 3 and 5 of FIG. 1 are each coupled to the common bus 16 by bus buffers 17 and 18, respectively. Unit 13a
are a processor 8a, a system memory 9a, an image memory 10a, a communication memory 11a,
It is composed of a ring controller 14a, a DMA controller 22a, and bus buffers 19a, 20a, and 21a. 12a is an internal bus. The other units 13b to 13d are also connected to the unit 13a.
It has the same configuration as . Units 13a-13d
Components related to are given subscripts a to d,
The explanation will be given below. DMA stands for Direct Memory
It is an abbreviation of Access.

In the following description of the embodiment, the unit 13
Regarding each component a to 13d, reference numerals may be used for easy understanding of the explanation even if it is not illustrated.

FIG. 3 is a diagram illustrating the configuration of the ring controller 14a. Information that the processor 8a wants to transmit is input to the ring controller 14a through an input buffer (hereinafter referred to as a transmission mailbox) 2
4a, the selector 23a checks whether the ring data bus 15 is free, and if it is, selects the information in the transmission mailbox 24a and inputs it to the shift register 25a. On the other hand, information on the ring data bus 15 is transmitted to the discriminator 2.
6a, and takes in the mail addressed to itself into the receiving mail box 28a. The processor 8a checks the status of the output buffer 28a (hereinafter referred to as a reception mailbox) of the ring controller 14a and takes in information. The remaining ring controllers 14b to 14d also have the same configuration as the ring controller 14a.

The image memory 3 has four areas 2 as shown in FIG.
9a, 29b, 29c, 29d, and the image memories 10a, 1 in each unit 13a to 13d
It is distributed to 0b, 10c, and 10d. For example, when the area 29a of the image memory 3 is transferred to the image memory 10a of the unit 1, the DMA controller 22a becomes the bus controller of the common bus 16 and operates according to instructions from the processor 8a. DMA
The controller 22a can be easily configured using a commercially available DMA controller IC (integrated circuit), and the processor 8a only needs to provide it with information necessary for DMA transfer. By closing buffer 19a and opening buffers 20a and 21a,
Image memory 10a is connected to internal bus 1 of unit 13a.
Since the processor 8a is separated from the processor 2a, the processor 8a can proceed with processing independently of the transfer, and the same is true for the units 13b to 13d.

On the other hand, divided regions 29a to 2 shown in FIG.
Information on areas 301 to 308 near the boundary in 9d is collected and used as a communication memory shown in FIG. Areas 311 to 318 of the communication memory 11a store the store contents of areas 301 to 308, respectively. The communication memory 11a stores the remaining units 13b to 13.
It has the same capacity as each communication memory 11b to 11d provided in d, and the stored contents at the corresponding addresses are the same. That is, these units 13a to 13
Each communication memory 11a to 11d of d
The store contents of areas 301 to 308 are similarly stored. Therefore, from now on, each unit 13a-1
When performing image processing independently within 3d, image areas 29a to 29a owned by each unit 13a to 13d
In addition to the information on 29d, other units 13a to 13d
When the information in the areas 301 to 308 owned by the unit 13a to 13d is needed, the corresponding area 311 of the communication memory provided in the unit 13a to 13d is
- 318 may be referred to.

When one stage of parallel processing is completed, the following operations are performed for the next parallel processing. First, in the unit 13a, the processing result is stored in the image memory 10a, the buffer 19a is closed, and the buffer 20a,
By opening 21a, the image memory 10a and the communication memory 11a are connected to the internal bus 1.
Separate from 2a. After performing the above operations in the same way for the units 13a to 13d, the unit 13a to 13d
Then, predetermined information is transmitted via the ring data bus 15 to notify the completion of the above operation. The transmission procedure is as shown in FIG. The unit 13a receives the information according to the procedure shown in FIG.
Confirm that the above operation in step d is completed. Then internal bus 1
2a to the DMA controller 22a, and the areas 301 and 302 in the image memory 10a are
is transferred to areas 311 and 312 in communication memories in all units 13a to 13d. When the DMA controller 22a completes the transfer, it notifies the processor 8a of the completion of the transfer via an interrupt, and the processor 8a sends information indicating the completion of the transfer to the processor 8b of the unit 13b via the ring data bus 15 as shown in FIG. However, the processor 8b of the unit 13b receives this information in the manner shown in FIG. 8, and the above procedure is then transferred in the unit 13b. Unit 1 below
3c and 13d are also transferred according to the above procedure, and finally unit 13d is transferred to units 13a to 13d.
13c is notified of completion of processing preparation via the ring data bus. Each unit 13a to 13d opens the bus buffer 19 and opens the bus buffer 20, 21.
, the image memory 10 and the communication memory 11 are connected to the internal bus 12 by closing the
Start processing. FIG. 9 shows a simplified information transfer route.

When all the processing is completed, the unit 13a issues a command to the DMA controller 22a, and the image memories 10a, 10 of the units 13a to 13d are
The contents of b, 10c, and 10d are transferred to the image memory 5. Note that the DMA transfer method via a common bus can be easily implemented using a commercially available general-purpose module such as a GPiB adapter (trade name manufactured by Texas Instruments, Inc., USA). The required transfer times for this method and the conventional method shown in FIG. 10 will be described below.
The number of units 13a to 13d is N, and the amount of information transferred by each unit 13a to 13d at one time is M.
Let t ₀ be the time required for the procedure required to acquire the common bus, t ₁ be the time required for the procedure to transmit information to the ring data bus 15, and the transfer time per word be t ₂ . Then, since the bus controller 32 processes transfer requests serially, _{the required time T 0 for} transfer according to the conventional _method shown in _FIG . The required time T ₁ is
According to the above explanation, T ₁ =L(t ₁ +Mt ₂ ) (2). Here, t ₁ is approximately the same as t ₀ , so in this method, the time required for transfer is reduced by L(N-1) t ₀ time than in the conventional method. Therefore, units 13a-1
As the number N of 3d units increases, the effect of this method becomes even greater.

In the above embodiment, the following effects can be obtained.

(1) Since the processor can continue processing locally even while image information is being transferred, information can be transferred using the ring data bus if necessary during this time.

(2) Since the information transfer path is dual, a highly reliable device can be realized.

(3) The unit is expandable.

(4) There is no need to install a dedicated bus controller, and the DMA controller of any unit can function as a bus controller.

(5) Since the ring bus controller exchanges information (mail) between the transmitting/receiving mailbox and the ring data bus, the program load on the processor is low.

According to the present invention, the following effects are achieved.

In the present invention, the processor 8a can proceed with processing locally even while image information is being transferred, and can transfer management information using the ring data bus.

Further, according to the present invention, since the common bus 16 and the ring data bus 15 are used, a highly reliable device can be realized.

Moreover, according to the present invention, the units 13a to
13d is easy to expand.

In the present invention, each unit 13a to 13d has a communication memory 11a for storing image information.
is provided and connected to the processor 8a via the buffer 19a and connected to the common bus 16,
By making the capacity and address of each communication memory 11a the same, image information to be divided and processed can be sent to each processing device at once, which is advantageous in smoothing processing and the like. That is, the communication memory 11a is the unit 13.
Since there are as many units as a to 13d, and each can be connected to the internal bus 12a, the same image information can be simultaneously transmitted to the processor 8a of each unit in one DMA transfer. Furthermore, since each unit can refer to the information in the communication memory in parallel, only the internal bus 12a needs to be referenced in parallel, and bus traffic problems can be avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of the configuration of the image processing device, FIG. 2 is a block diagram showing the parallel image processing device 4, FIG. 3 is a block diagram of the ring controller 14a, and FIG. 4 shows divided image information. diagram showing,
FIG. 5 is a diagram showing boundary image information, FIG. 6 is a diagram showing the communication memory 11a, FIG. 7 is a flowchart for explaining the transmission operation, and FIG. 8 is a diagram showing the communication memory 11a.
The figure is a flowchart to explain the reception operation.
FIG. 9 is a diagram showing a transfer path of image information, and FIG. 10 is a block diagram showing a conventional system. 4... Parallel image processing device, 10a... Image memory, 11a... Communication memory, 13
a to 13d...unit, 15...ring data bus, 16...common bus, 17, 18...buffer, 19a, 20a, 21a...bus buffer,
22a...DMA controller.

Claims (1)

[Claims] 1. A first image memory 3 in which image information to be processed is stored, a parallel image processing device 4 that processes the image information in the first image memory 3, and a process performed by this parallel image processing device 4. The parallel image processing device 4 transfers image information to and from the second image memory 5 that stores the resulting image information, and the parallel image processing device 4 transfers the image information to the first and second image memories 3, a circular common bus 16 connected to the common bus 16, a circular ring data bus 15 for transferring management function information such as synchronization and transfer requests, and a plurality of buses connected to the common bus 16 and the ring data bus 15 Each unit 13a to 13d includes an internal bus 12a connected to a common bus 16 and a ring data bus 15, and a common bus 1
a buffer 19a that can be separated into the ring data bus 15 side and the ring data bus 15 side; a processor 8a that is connected to the internal bus 12a on the ring data bus 15 side from the buffer 19a;
unit image memory 10a for storing image information stored in each area 29a to 29d divided into a number equal to the number of units of the first image memory 3, and a common bus than the buffer 19a. Internal bus 1 on the side
2a, and stores image information of boundary areas 301 to 308 near the boundaries among the areas 29a to 29d.
The communication memory 11a is
Such a communication memory 11a has the same capacity for each unit and stores the same contents at the corresponding address, and the internal bus 1 on the common bus side of the buffer 19a.
2a and a DMA controller 22a that operates according to instructions from the processor 8a, and for parallel processing by the processor 8a of each unit 13a to 13d, the processing result is stored in the unit image memory 10a, and the processing result is stored in the buffer 19a. The processor 8a transfers management function information via the ring data bus 15. All units 13a to 13
d's communication memory 11a,
A high-speed transfer device for image information, etc., characterized in that a buffer 19a is opened and image information is processed using a unit image memory 10a and a communication memory 11a by a processor 8a.