JPS6354239B2 - - Google Patents

Info

Publication number
JPS6354239B2
JPS6354239B2 JP9928881A JP9928881A JPS6354239B2 JP S6354239 B2 JPS6354239 B2 JP S6354239B2 JP 9928881 A JP9928881 A JP 9928881A JP 9928881 A JP9928881 A JP 9928881A JP S6354239 B2 JPS6354239 B2 JP S6354239B2
Authority
JP
Japan
Prior art keywords
conductor
press
ceramic substrate
substrate
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9928881A
Other languages
Japanese (ja)
Other versions
JPS582278A (en
Inventor
Hirozo Yokoyama
Koichi Niwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9928881A priority Critical patent/JPS582278A/en
Publication of JPS582278A publication Critical patent/JPS582278A/en
Publication of JPS6354239B2 publication Critical patent/JPS6354239B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明はIC、LSI等の素子を搭載する高密度回
路基板の製法に関し、特に前記素子接続に係る導
体端子形成手段を提示する多層セラミツク基板の
製造方法に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-density circuit board on which elements such as ICs and LSIs are mounted, and more particularly to a method for manufacturing a multilayer ceramic substrate that provides means for forming conductor terminals for connecting the elements.

アルミナセラミツク系等組成を具えるセラミツ
ク基板は機械的強度が高く、熱伝導率が大きくか
つ電気的・化学的特性に秀れているため、近時ピ
ン数の多いLSIチツプの実装組立にも広く使用さ
れている。本発明はかかるセラミツク基板を対象
とし、未焼成セラミツク基板(いわゆるグリーン
シート)を80枚又はそれ以上に積層しこれを焼成
した所謂立体化回路形成の基板につき、積層体の
各面方向に効率よく導体端子を形成することがで
きる方法を提供しようとするものである。
Ceramic substrates with compositions such as alumina ceramics have high mechanical strength, high thermal conductivity, and excellent electrical and chemical properties, so they are now widely used for mounting and assembling LSI chips with a large number of pins. It is used. The present invention is directed to such ceramic substrates, and relates to a so-called three-dimensional circuit-forming substrate in which 80 or more unfired ceramic substrates (so-called green sheets) are laminated and fired. It is an object of the present invention to provide a method by which conductor terminals can be formed.

係る多層セラミツク基板は、通常積層の各回路
間の何層かを導体接続するためバイアホールを設
けると共に、積層体の各面には搭載する機能素子
(IC、LSI等)接続用外部露出の導体端子を設け
るのが一般的である。従来、前記バイアホールの
形成は金属性の導体ボールの圧入あるいは充填に
より行なわれ、前記層間接続回路並びに外部端子
の形成は次のような手段がとられていた。
Such multilayer ceramic substrates usually have via holes for conductive connections between several layers of laminated circuits, and externally exposed conductors for connecting functional elements (IC, LSI, etc.) to be mounted on each surface of the laminated body. It is common to provide a terminal. Conventionally, the via holes have been formed by press-fitting or filling metal conductor balls, and the interlayer connection circuits and external terminals have been formed by the following means.

即ち、第1図は導体ボール圧入方式により、シ
ート体にバイアホール形成の状況を示す断面図で
ある。図中、1はグリーンシートあるいはシー
ト、2はバイアホール配列の位置を規正、また配
列の導体ボール5を押型4で圧入する貫通孔6を
具える配列治具である。図の3は前記押型4に対
する受型である。かかる圧入方式によるバイヤホ
ール形成の詳細については特願昭54―13011(昭和
54年10月9日付出願)がある。
That is, FIG. 1 is a sectional view showing how via holes are formed in a sheet body by the conductor ball press-fitting method. In the figure, 1 is a green sheet or a sheet, and 2 is an arrangement jig provided with through holes 6 for regulating the position of the via hole arrangement and for press-fitting the arranged conductor balls 5 with a press die 4. 3 in the figure is a receiving mold for the pressing mold 4. For details on via hole formation using such a press-fitting method, please refer to Japanese Patent Application No. 13011 (Showa 54).
(filed on October 9, 1954).

第1図下方は前記導体ボール圧入後の単シート
1及び1′が示され、これらシートの表・裏面7
と8間は例えばマスクパターンにより導体回路が
形成された回路と導体5がバイアホールされる。
これら単シート体の複数を位置決めして積層し、
これを所定温度で焼成して多層セラミツク基板と
するが、対象とする導体端子は前記焼成後の基板
エツヂ(斜線部)を研削してA―A指標線位置ま
で切除することにより形成することが出来る。換
言すればシート端に近い配置のボール導体5を露
出させて端子としていた。
The lower part of FIG. 1 shows the single sheets 1 and 1' after the conductor balls have been press-fitted, and the front and back surfaces 7 of these sheets are shown.
and 8, a via hole is formed between the conductor 5 and a circuit in which a conductor circuit is formed by, for example, a mask pattern.
A plurality of these single sheets are positioned and stacked,
This is fired at a predetermined temperature to form a multilayer ceramic board, and the target conductor terminals can be formed by grinding the board edge (shaded area) after the firing and cutting it to the A-A index line position. I can do it. In other words, the ball conductor 5 located near the edge of the sheet is exposed and used as a terminal.

しかしながら、ボール配列治具(第2図のA図
2と10参照)とシート体1との高精度位置合わ
せに拘らず端子該当導体は球状であること、又前
記の導前露出をなす側面研削作業において基板保
持治具及び研削条件に偏りがあると積層の上・下
基板間で端子面にバラツキを生じ不都合である。
偏研削の場合、例図の如く下方基板1′側では導
体の露出がない事態となる(図は問題点明示のた
め誇大表示してある。) 本発明の目的は前記の不都合を解消することに
ある。目的達成に当り本発明では、未焼成セラミ
ツク基板に円柱状導体部材を該円柱状導体部材の
軸と未焼成セラミツク基板表面とがほぼ平行にな
る様圧入する行程と、前記未焼成セラミツク基板
を積層し焼成する行程と、及び前記焼成基板の側
面研削により前記円柱状導体部材を露出せしめる
行程とからなることを特徴とする多層セラミツク
基板の製造方法である。
However, despite the high precision alignment between the ball arrangement jig (see Figures 2 and 10 in A of Figure 2) and the sheet body 1, the conductor corresponding to the terminal is spherical, and the side surface grinding that exposes the conductor is difficult. If the substrate holding jig and grinding conditions are uneven during the work, the terminal surfaces will vary between the upper and lower laminated substrates, which is inconvenient.
In the case of uneven grinding, the conductor is not exposed on the lower substrate 1' side as shown in the example diagram (the diagram is exaggerated to make the problem clearer).The purpose of the present invention is to eliminate the above-mentioned disadvantages. It is in. To achieve the object, the present invention includes a step of press-fitting a cylindrical conductor member into a green ceramic substrate so that the axis of the cylindrical conductor member and the surface of the green ceramic substrate are approximately parallel, and a step of laminating the green ceramic substrates. This method of manufacturing a multilayer ceramic substrate is characterized by comprising a step of pre-firing, and a step of exposing the columnar conductor member by grinding the side surface of the fired substrate.

以下、本発明の一実施例を例示した第2図及び
第3図に従がいこれを説明する。第2図は係る基
板製作の作業行程を順次説明する斜視図及び第3
図は端子露出の研削手段を説明する斜視図であ
る。
An embodiment of the present invention will be explained below with reference to FIGS. 2 and 3, which illustrate one embodiment of the present invention. Fig. 2 is a perspective view and Fig.
The figure is a perspective view illustrating a grinding means for exposing terminals.

第2図においてA図は、グリーンシート1上に
載置の前記せる配列治具2及び治具固定枠10を
用い、ボール導体5を枠内位置決めする圧入前の
状態、又B図は前記導体ボール5がシート1中に
充填された圧入後のシート状態を示す。該ボール
のサイズは高密度配線パターン等を考慮し、例え
ば径0.34mm程度のものが用いられる。
In Fig. 2, Fig. A shows the state before press-fitting, in which the ball conductors 5 are positioned within the frame using the arrangement jig 2 and the jig fixing frame 10 placed on the green sheet 1, and Fig. B shows the state before press-fitting, in which the ball conductors 5 are positioned within the frame. The state of the seat after the balls 5 are press-fitted into the seat 1 is shown. The size of the ball is, for example, about 0.34 mm in diameter, taking into account high-density wiring patterns and the like.

C図はB図行程に続き本発明の要部をなす端子
導体としての円柱状導体、例えば径0.34mm、及び
長さ1mm程度のAu導体がA図同様シート1に対
して枠11により配列位置決めして円柱状導体1
2が圧入される前状態を示している。シートの四
辺側に導体12の配列完了時点で、図示しない油
圧プレス装置により導体圧入したものがD図であ
る。導体5並びに12の配列構成は一例に過ぎ
ず、図示の如くバイヤホール形成部はシート央部
に多数高密度配列して設けられ、他方シート外側
辺には外部露出をなす導体端子が多数配列させて
設けられる。
Figure C is a continuation of the process in Figure B, in which a cylindrical conductor as a terminal conductor, which is the essential part of the present invention, for example, an Au conductor with a diameter of 0.34 mm and a length of about 1 mm, is arranged and positioned by the frame 11 on the sheet 1 as in Figure A. Cylindrical conductor 1
2 is shown before being press-fitted. Figure D shows the conductors press-fitted by a hydraulic press device (not shown) at the time when the arrangement of the conductors 12 is completed on the four sides of the sheet. The arrangement of the conductors 5 and 12 is merely an example, and as shown in the figure, a large number of via hole forming portions are arranged in a high-density arrangement in the center of the sheet, and on the other hand, a large number of externally exposed conductor terminals are arranged on the outer side of the sheet. It will be established.

第3図は前記第2図D行程を経たシート13
に、前記の回路パターン付4したものを多数積み
重ね加圧して多層化し、900℃の炉中で焼成した
多層積層体14の斜視図である。
Figure 3 shows the sheet 13 that has undergone the step D in Figure 2.
FIG. 2 is a perspective view of a multilayer laminate 14 obtained by stacking a large number of the above-mentioned circuit patterned products 4 and pressurizing them to form a multilayer, and then firing in a furnace at 900°C.

積層体14の各面15乃至19(5面ある)
は、面研削あるいは面研磨がされ、円柱端子導体
による端子を形成する。例えば図示では基板側面
15にその導体2の露出がなされた状況を示す。
他の側面16乃至19の各面にも面研磨がされる
はもちろんである。かくして底面を除く基板体1
4のあらゆる面は、外部露出になる機能素子の搭
載面となり、該面内にパツド状導体端子が形成さ
れることになる。導体端子の配列例(図示15の
面はDIP端子構成である)は一例に過ぎない。例
えばフラツトパツク構造の配列端子に対する導体
端子を形成することも可能である。
Each side 15 to 19 of the laminate 14 (there are 5 sides)
is surface ground or surface polished to form a terminal with a cylindrical terminal conductor. For example, the figure shows a situation in which the conductor 2 is exposed on the side surface 15 of the substrate.
Of course, each of the other side surfaces 16 to 19 is also surface polished. Thus, the substrate body 1 excluding the bottom surface
All sides of 4 serve as mounting surfaces for functional elements that are exposed to the outside, and pad-shaped conductor terminals are formed within these surfaces. The arrangement example of the conductor terminals (the surface 15 shown in the figure is a DIP terminal configuration) is only one example. It is also possible, for example, to form conductor terminals for array terminals of flat pack construction.

以上説明した本発明になる多層セラミツク基板
の製造方法によれば、球状導体端子の形状的欠陥
に基因する基板側面研削作業の困難さがなくな
る、併せて研削時における作業性も向上するため
製造容易にして、安価なセラミツク基板が提供可
能となる。
According to the method for manufacturing a multilayer ceramic substrate according to the present invention as described above, the difficulty in grinding the side surface of the substrate due to the shape defect of the spherical conductor terminal is eliminated, and the workability during grinding is also improved, making manufacturing easier. As a result, an inexpensive ceramic substrate can be provided.

かかる観点から本発明の工業的効果は大きい。 From this point of view, the industrial effects of the present invention are significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のセラミツク基板製造方法を示す
側断面図、第2図と第3図は本発明にかかる多層
セラミツク基板製造方法説明のための斜視図及び
仝基板完成体実施例としての斜視図である。 図中、1は焼成前シート、3と4は共にボール
等導体5のシート圧入の押型、9は基板シートの
側面、12は円柱状導体、13は導体5と12を
圧入したシート完成体、14は多層セラミツク基
板体、15,16,17,18及び19は共に焼
成基板の側面である。
FIG. 1 is a side sectional view showing a conventional ceramic substrate manufacturing method, and FIGS. 2 and 3 are perspective views for explaining the multilayer ceramic substrate manufacturing method according to the present invention, and perspective views as an example of the completed substrate. It is. In the figure, 1 is a sheet before firing, 3 and 4 are both press molds for press-fitting a conductor 5 such as a ball, 9 is a side surface of a substrate sheet, 12 is a cylindrical conductor, 13 is a completed sheet into which conductors 5 and 12 are press-fitted, 14 is a multilayer ceramic substrate body, and 15, 16, 17, 18 and 19 are side surfaces of the fired substrate.

Claims (1)

【特許請求の範囲】[Claims] 1 導体端子及び層間接続用のバイヤホールを複
数個具備する多層セラミツク基板の製造方法にお
いて、未焼成セラミツク基板に円柱状導体部材を
該円柱状導体部材の軸と未焼成セラミツク基板表
面とがほぼ平行になる様圧入する行程と、前記未
焼成セラミツク基板を積層し焼成する行程と、及
び前記焼成基板の側面研削により前記円柱状導体
部材を露出せしめる行程とからなることを特徴と
する多層セラミツク基板の製造方法。
1. In a method for manufacturing a multilayer ceramic substrate having a plurality of via holes for conductor terminals and interlayer connections, a cylindrical conductor member is placed on an unfired ceramic substrate so that the axis of the cylindrical conductor member and the surface of the unfired ceramic substrate are approximately parallel to each other. A multilayer ceramic substrate comprising: a step of press-fitting the unfired ceramic substrates so that Production method.
JP9928881A 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate Granted JPS582278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9928881A JPS582278A (en) 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9928881A JPS582278A (en) 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate

Publications (2)

Publication Number Publication Date
JPS582278A JPS582278A (en) 1983-01-07
JPS6354239B2 true JPS6354239B2 (en) 1988-10-27

Family

ID=14243454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9928881A Granted JPS582278A (en) 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate

Country Status (1)

Country Link
JP (1) JPS582278A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61212101A (en) * 1985-03-15 1986-09-20 Murata Mfg Co Ltd Dielectric resonator
JP2553307Y2 (en) * 1991-09-10 1997-11-05 日野自動車工業株式会社 rivet

Also Published As

Publication number Publication date
JPS582278A (en) 1983-01-07

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