JPS582278A - Manufacture of multi-layer ceramic substrate - Google Patents

Manufacture of multi-layer ceramic substrate

Info

Publication number
JPS582278A
JPS582278A JP9928881A JP9928881A JPS582278A JP S582278 A JPS582278 A JP S582278A JP 9928881 A JP9928881 A JP 9928881A JP 9928881 A JP9928881 A JP 9928881A JP S582278 A JPS582278 A JP S582278A
Authority
JP
Japan
Prior art keywords
conductor
ceramic substrate
substrate
sheet
press
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9928881A
Other languages
Japanese (ja)
Other versions
JPS6354239B2 (en
Inventor
横山 博三
丹羽 紘一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9928881A priority Critical patent/JPS582278A/en
Publication of JPS582278A publication Critical patent/JPS582278A/en
Publication of JPS6354239B2 publication Critical patent/JPS6354239B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は10.LSI等の素子を搭載する高密度回路基
板の表法に関し、特に前記素子接続に係る導体へ−f形
成手段を提示する多層セラミック基板の製造方法4こ関
す。
DETAILED DESCRIPTION OF THE INVENTION The present invention consists of 10. The present invention relates to a method for manufacturing a high-density circuit board on which elements such as LSI are mounted, and in particular to a method for manufacturing a multilayer ceramic substrate that provides means for forming -f on conductors for connection of the elements.

アルミナセラミック系等組成を具えるセラミック基板は
機械的強度が高(、熱伝導率が丙きくかつ電気的・化学
的特性に秀れているため、近時ビン数の多いL8Iチッ
プの実装組立にも広く使用されている。本発明はかかる
セラミック基板を対象とし、未焼成セラミック基板(い
わゆるグリーンシート)を80枚又はそれ以上に積層し
これを焼成した所謂立体化回路形成の基板につき、積層
体の各面方向に効率よく導体端子を形成することができ
る方法を提供しようとするものである。
Ceramic substrates with compositions such as alumina ceramics have high mechanical strength (high thermal conductivity, and excellent electrical and chemical properties), so they are suitable for mounting and assembling L8I chips, which have recently become popular in large numbers. The present invention is directed to such ceramic substrates, and relates to a so-called three-dimensional circuit-forming substrate in which 80 or more unfired ceramic substrates (so-called green sheets) are laminated and fired. The object of the present invention is to provide a method that can efficiently form conductor terminals in each surface direction.

係る多層セラミック基板は、通常積層の各回路間の何層
かを導体接続するためバイアホールを設けると共に、積
層体の各面には搭載する機能素子(IC,LSI蝙)接
続用外si1出の導体端子を設けるのが一般的である。
Such multilayer ceramic substrates usually have via holes for conductive connection between several layers between each layered circuit, and each side of the layered body has an external Si1 output for connecting functional elements (IC, LSI) to be mounted. It is common to provide a conductor terminal.

従来、前記バイアホールの形成は金概性の導体ボールの
圧入あるいは充填により行なわれ、前記層間接続回路並
びに外部端子の形成は次のような手段がとられていた。
Conventionally, the via holes have been formed by press-fitting or filling metal conductor balls, and the interlayer connection circuits and external terminals have been formed by the following means.

即ち、第1図は4体ボール圧入方式により、シート体に
パイヤホール形成の状況を示す断面図である。図中、l
はグリーンシートあるいはシート、2はパイヤホール配
列の位置を規正、また配列の導体ボール5を押!lf4
で圧入する貫通孔6を具える配列治具である。図の3は
前記押型4に対する受型である。かかる圧入方式による
パイヤホール形成の詳細については特願昭54−130
11(昭和54年lθ月9日付出願廼Sある。
That is, FIG. 1 is a sectional view showing how a pie hole is formed in a sheet body by a four-ball press-fitting method. In the figure, l
is the green sheet or sheet, 2 is the position of the pie hole array, and the conductor ball 5 of the array is pressed! lf4
This is an arrangement jig equipped with a through hole 6 that is press-fitted. 3 in the figure is a receiving mold for the pressing mold 4. As shown in FIG. For details on forming a pie hole using this press-fitting method, please refer to Japanese Patent Application No. 1983-130.
11 (filed on September 9, 1978).

第1図下方は前記導体ボール圧入後の単シートl及び1
′が示され、これらシートの表・裏面7と8間は例えば
マスクパターンにより導体回路が形成された回路と導体
5がバイアホールされる。
The lower part of Figure 1 shows the single sheets 1 and 1 after the conductor balls are press-fitted.
' is shown, and between the front and back surfaces 7 and 8 of these sheets, a circuit having a conductor circuit formed by a mask pattern and a via hole are formed for the conductor 5.

これら単シート体の複数を位置決めして積層し、これを
所定@薇で燐酸して多層セライック基板とするが、対象
とする導体端子は前記燐酸後の基板エッチ(斜線部)を
研削してλ−人指標線位置談で切除することにより形成
することが出来る。換言すればシート端に近い配置のボ
ール導体5を露出させて端子としていた。
A plurality of these single sheets are positioned and laminated, and this is phosphoricated at a predetermined temperature to form a multilayer Ceric substrate. - Can be formed by cutting at the position of the human index line. In other words, the ball conductor 5 located near the edge of the sheet is exposed and used as a terminal.

し力)しながら、ボール配列治具(第2図の囚図2とl
O参照)とシート体1との高精度位置合わせに拘らず端
子[導体は球状であること、又前記の導体霧出をなす側
面研削作業において基板保持治具及び研削条件に偏りが
あると積層の上・下基板間で端子面にバラツキを生じ不
都合である。
2 and l of the ball arrangement jig (Fig. 2).
Regardless of the high-precision alignment between the terminal (see O) and the sheet body 1, the conductor must be spherical, and if the substrate holding jig and grinding conditions are uneven during the side grinding work that produces the conductor mist, the lamination may occur. This is inconvenient because it causes variations in the terminal surfaces between the upper and lower boards.

偏研削の場合、倒閣の如く下方基板1′側では導体の露
出がない事態となる(図は問題点明示のため誇大表示し
である)。
In the case of uneven grinding, there is a situation where the conductor is not exposed on the lower substrate 1' side (the diagram is exaggerated to clarify the problem).

本発明の目的は前記の不都合を解消することにある。目
的達成に当り本発明では、未燐酸セラiツク基板に円柱
状導体部材を骸円柱状導体部材の軸と未燐酸セランツク
基板表面とがほぼ平行になる様圧入する行程と、前記未
焼成セラミック基板を積層し燐酸する行程と、及び前記
焼成基板の側面研削により前記円柱状導体部材を露出せ
しめる行程とからなることを特徴とする多層セラ(ツク
基板の製造方法である。
An object of the present invention is to eliminate the above-mentioned disadvantages. In order to achieve the object, the present invention includes a step of press-fitting a cylindrical conductor member into an unphosphorized ceramic substrate so that the axis of the cylindrical conductor member and the surface of the unphosphorized ceramic substrate are approximately parallel; A method of manufacturing a multilayer ceramic substrate is characterized by comprising a step of laminating and phosphoricating the fired substrate, and a step of exposing the columnar conductor member by grinding the side surface of the fired substrate.

以下、本発明の一実施例を例示した第2図及び第3図に
従かいこれを説明する。第2図は係る基板製作の作業行
程を順次説明する斜視図及び第3図は端子露出の研削手
段を説明する斜視図である。
An embodiment of the present invention will be explained below with reference to FIGS. 2 and 3, which illustrate one embodiment of the present invention. FIG. 2 is a perspective view sequentially illustrating the work steps of manufacturing the board, and FIG. 3 is a perspective view illustrating a grinding means for exposing terminals.

第2図において囚図は、グリーンシー)1上に載置の前
記せる配列治具2及び治具固定枠10を用い、ボール導
体5を枠内位置決めする圧入前の状態、又の)図は前記
導体ボール5がシート1中に充填された圧入後のシート
状態を示す。該ボールのサイズは高密度配線パターン等
を考慮し、例えば径0.34w1@度のものが用いられ
る。
In Fig. 2, the figure shows the state before press-fitting, in which the ball conductor 5 is positioned within the frame using the arrangement jig 2 and the jig fixing frame 10 placed on the green sea) 1. The state of the sheet after the conductor balls 5 are press-fitted into the sheet 1 is shown. The size of the ball is, for example, a ball with a diameter of 0.34 w1 degrees, taking into account high-density wiring patterns and the like.

0図は■図行程に続き本発明の要部をなす端子導体とし
ての円柱状導体、例えば径0.34■、及びu 長さ1間程度のム臆導体が四回同様シート1に対して粋
11により配列位置決めして円柱状導体12が圧入され
る前状態を示している。シートの四辺側に導体12の配
列完了時点で、図示しない油圧プレス装置により導体正
大したものが0図である。
Figure 0 is a continuation of the process shown in Figure ■, where a cylindrical conductor as a terminal conductor, which is the essential part of the present invention, for example, a diameter of 0.34■, and a conductor with a length of about 1 inch are similarly applied to sheet 1 four times. This figure shows the state before the cylindrical conductors 12 are press-fitted after being aligned and positioned by the guides 11. When the arrangement of the conductors 12 on the four sides of the sheet is completed, the conductors are enlarged using a hydraulic press (not shown) in Figure 0.

導体5並びに12の配列構成は一例に過ぎず、図示の如
くパイヤホール形成部はシート央部に多数高密度配列し
て設けられ、他方シート外側辺には外部露出をなす導体
端子が多数配列させて設けられる。
The arrangement of the conductors 5 and 12 is merely an example, and as shown in the figure, a large number of pie hole forming portions are arranged in a high-density arrangement in the center of the sheet, and on the other hand, a large number of externally exposed conductor terminals are arranged on the outer side of the sheet. provided.

第3図は前記第210行程を経たシート13に、前記の
回路パターン付4したものを多数積み重ね加圧して多層
化し、900Cの炉中で燐酸した多層積層体14の斜視
図である。
FIG. 3 is a perspective view of a multilayer laminate 14 in which a large number of sheets 13 with the circuit pattern 4 which have undergone the 210th step are piled up and pressed to form a multilayer, and phosphoricated in a 900C furnace.

積層体14の各雨15乃Ml 9 (5Thある)は、
面研削あるいは面研磨がされ、円柱端子導体による端子
を形成する。例えば図示では基板側面15にその導体2
の露出がなされた状況を示す。他の側面16乃至19の
各面にも内研磨かされるはもちろんである。かくして底
面を診く基板体14のあらゆる面は、外部露出になる機
能素子の搭載面となり、該面内にパッド状導体端子が形
成されることになる。導体端子の配列例(図示15の面
はDIPfi♀構成である)は−例に退きない。例′え
ばフラットパック構造の配列重子に対する導体端子を形
成することも可能である。
Each rain 15~Ml 9 (there are 5Th) of the laminate 14 is
Surface grinding or surface polishing is performed to form a terminal using a cylindrical terminal conductor. For example, in the illustration, the conductor 2 is placed on the side surface 15 of the board.
Indicates the situation in which the exposure was made. Of course, the other side surfaces 16 to 19 are also internally polished. In this way, all surfaces of the substrate body 14, including the bottom surface, become surfaces on which functional elements are mounted and exposed to the outside, and pad-shaped conductor terminals are formed within these surfaces. The arrangement example of the conductor terminals (the surface 15 shown in the drawing has a DIPfi♀ configuration) is not limited to the - example. It is also possible, for example, to form conductor terminals for array elements of flat-pack construction.

以上軌間した本発明になる多層上うきツク基板の製造方
法によれば、球状導体端子の形状的欠陥に基因する基板
側面研削作業の困離さがなくなる、併せて研削時におけ
る作業性も同上するため製造容易にして、安価なセラミ
ック基板が提供可能とする。
According to the method for manufacturing a multilayer top-floated board according to the present invention having the above-mentioned trajectory, the difficulty of grinding the board side surface due to the shape defect of the spherical conductor terminal is eliminated, and the workability during grinding is also improved. To easily manufacture and provide an inexpensive ceramic substrate.

力)かる観点から本発明の工業的効果は太さい・From this perspective, the industrial effects of the present invention are significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のセラ建ツタ基板製造方法を示す側断面図
、第2図と第3図は本発明にかかる多層セラミック基板
製造方法説明のための斜視図及び尤 仝基板彫成体−実施例としての斜視図である。 図中、1は燐酸前シート、3と4は共にボール醇導体5
のシート圧入の押型、9は基板シートの側面、12は円
柱状導体、13は導体5と12を圧入したシート完成体
、14は多層セラミック基板体、15.16.17.1
8及び19は共に燐酸基板の側面である。 第1閃 第3(2) ♀Z fXl (A)
FIG. 1 is a side sectional view showing a conventional method for manufacturing a ceramic ceramic board, and FIGS. 2 and 3 are perspective views for explaining the method for manufacturing a multilayer ceramic board according to the present invention, and examples of carved substrates. FIG. In the figure, 1 is the phosphoric acid front sheet, 3 and 4 are both the ball conductor 5
9 is a side surface of the substrate sheet, 12 is a cylindrical conductor, 13 is a completed sheet into which conductors 5 and 12 are press-fitted, 14 is a multilayer ceramic substrate body, 15.16.17.1
Both 8 and 19 are the side surfaces of the phosphoric acid substrate. 1st flash 3rd (2) ♀Z fXl (A)

Claims (1)

【特許請求の範囲】[Claims] 導体端子及び層間接続用のパイヤホールを複数個具備す
る多層セライック基板の製造方法において、未焼成セラ
ミツク基板に円柱状導体部材を該円柱状導体部材の軸と
未焼成セラミツク基板表面とがはは平行になる様圧入す
る行程と、前記未焼成セラミック基板を積層し焼成する
行程と、及び前記焼成基板の一面研へ〇により前記円柱
状導体部材を露出せしめる行程とからなることを特徴と
する多層セラミンク基板の製造方法。
In a method for manufacturing a multilayer ceramic substrate having a plurality of conductor terminals and a plurality of wire holes for interlayer connection, a cylindrical conductor member is placed on an unfired ceramic substrate so that the axis of the cylindrical conductor member and the surface of the unfired ceramic substrate are parallel to each other. A multilayer ceramic board characterized by comprising a step of press-fitting the unfired ceramic substrates so that the substrates are formed, a step of laminating and firing the unfired ceramic substrates, and a step of exposing the cylindrical conductive member by one-sided polishing of the fired substrate. manufacturing method.
JP9928881A 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate Granted JPS582278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9928881A JPS582278A (en) 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9928881A JPS582278A (en) 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate

Publications (2)

Publication Number Publication Date
JPS582278A true JPS582278A (en) 1983-01-07
JPS6354239B2 JPS6354239B2 (en) 1988-10-27

Family

ID=14243454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9928881A Granted JPS582278A (en) 1981-06-26 1981-06-26 Manufacture of multi-layer ceramic substrate

Country Status (1)

Country Link
JP (1) JPS582278A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61212101A (en) * 1985-03-15 1986-09-20 Murata Mfg Co Ltd Dielectric resonator
JPH0525012U (en) * 1991-09-10 1993-04-02 日野自動車工業株式会社 Rivet

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61212101A (en) * 1985-03-15 1986-09-20 Murata Mfg Co Ltd Dielectric resonator
JPH0525012U (en) * 1991-09-10 1993-04-02 日野自動車工業株式会社 Rivet

Also Published As

Publication number Publication date
JPS6354239B2 (en) 1988-10-27

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