JPS6352484A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize an ultra-high-speed operation by a method wherein a cyclic structure is provided along at least one layer among a semiconductor layer, an insulating layer and a conductive layer and, at this cyclic structure, the effective mass of an electron which is related to the movement in the direction along the direction of this layer can be either positive or negative depending on the energy of the electron. CONSTITUTION:The cross section parallel to the source-drain direction, i.e., the channel direction, at an n type GaAs layer 6 is shaped like a cyclic structure along the same direction. The concentration of electrons in a two-dimensional electron layer 12 appearing near the interface between an undoped GaAs layer 4 and an n type Al0.3Ga0.7As layer 5 is modulated by the cycle, and the potential applied to these electrons becomes a cyclic potential. If a gate voltage is scanned at this time, the Fermi level is increased gradually and reaches an inflection point as shown by A, A', B, B', etc. Before and after the inflection point the effective mass of the electron changes from a positive state to a negative one. Therefore, when the Fermi level passes through the inflection point, the electron which has been accelerated so far is affected by the acceleration acting in the reverse direction and the speed is slowed down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that operates at ultra-high frequencies.

[Conventional technology]

The idea of an ultra-high mobility FET that exceeds the operating limits of conventional field effect transistors (hereinafter abbreviated as FET) was developed by Sakaki (
H, 5akaki), Javanese Journal of Applied Physics Letters No. 2
Volume 1, page L381 (1982) (Jpn, J.
Appl, Phys, Lett, 2 (1982
) L 381). They proposed a transistor structure in which the traveling speed (or mobility μ) of the FET could be changed in response to an external signal without changing the electron density N in the channel, and called this a speed modulation transistor VMT. I named it. According to them, this transistor does not require changing the number of electrons in the channel, which eliminates transit time constraints and enables high-speed response. Furthermore, they demonstrated a method for achieving this by making full use of the double Peter structure, creating two parallel channels with different mobilities, and allowing electrons to move between these two channels.

[Problem that the invention seeks to solve]

However, in the structure considered by them, in order for electrons to move between the above two channels, they must either pass through a layer with a high energy barrier by tunneling, etc., or be accelerated by an electric field and overcome this energy barrier. It is necessary to obtain as much energy as possible, and it is thought to be extremely difficult to create a situation where the expected high-speed operation can be achieved.

An object of the present invention is to provide a means for eliminating the above-mentioned coupling and effectively modulating the mobility of electrons within a channel.

[Means for solving problems]

First, in order to explain the present invention in detail, two types of semiconductor layers 1 having different electron affinities χ are used as shown in FIG.
, 2 are stacked in a superlattice.

The electron affinity χ and the thickness of the semiconductor layer 1.2 are respectively,
χ1. When χ1+a*b, the effective electrostatic potential felt by conduction electrons in the stacked semiconductor layer is shown in Figure 2 (b
). In other words, its potential is
The depth V o ”χ along the thickness direction (direction of arrow A)
It is a periodic potential of 1-χ2. It is well known that the electron energy E has a structure as schematically shown in FIG. 3, as discussed by Kronig and Benny. (Proceedings of the Royal Society of London by R. de L. Kronig and W. G. Panney)
of Royal Society of London
n), Vol. A130 (1931, p. 499)) As is clear from Figure 3, which shows the relationship between electron energy E and electron wave number, A in the figure.

It can be seen that the points indicated by A', B, B', etc. are the inflection points of the curve at E-. (Luck with this wave number #J:i
P uses h=h/2π, which is obtained by dividing the blank constant ri by 2π, and has the relationship P=hk. ) - Method, Solid State Physics Textbook 1 For example, Kittal (C, Kittal)
As discussed in "Introduction to Solid State Physics" (Translated by Uno, Tsuya, and Yamashita), page 205 (published by Maruzen Co., Ltd., 1981), the effective mass of electrons in a solid, ms, is expressed by the curve E-. It is given by the following relational expression.

1 1 82E me h"ak" From this relational expression, the effective quality of electrons i m * becomes very large near the points of inflection A and A' shown in FIG. 3. Furthermore, at points where the energy is greater than these inflection points A and A', the curve at E- is upwardly convex, and in the range where the curve at E- is upwardly convex, from the above equation, the effective mass of electrons mm* It turns out that is negative.

That is, it can be seen that the sign of the effective mass of the electron changes before and after the inflection points A and A'. Similar situation is inflection point B
, B' also occur before and after.

If we return to the M'EJ equation for electrons, we get
It is easy to see that when the same electric field acts, the accelerations experienced by electrons with energies above and below this inflection point are of opposite sign.

The above discussion concerns the movement of electrons in the direction of the thickness of the stack of semiconductor layers, and it should be noted that in the two-dimensional direction of the stack, the movement of electrons is equivalent to that of free electrons. I'll add that.

As is clear from the above explanation using the semiconductor layers laminated in a superlattice shape, the present invention is capable of accelerating electrons in a certain energy range by forming a periodic lattice. This takes advantage of the fact that electrons in different energy ranges have different signs. That is, the present invention has a periodic frW structure along at least one of the semiconductor layer, the insulating layer, or the dedicated layer, and the periodic structure is such that the effective mass of the electrons in the direction along the above direction is It is characterized by being formed so that it can be either positive or negative depending on the energy of the electrons.

The L periodic structure is formed, for example, by processing the above layer into a striped shape.

[Effect]

The effective mass of electrons in a solid can be positive or negative along a certain direction depending on its energy value.
This means that when an electric field is applied to the nanofibers that exist here, the energy of the electrons causes acceleration in the opposite direction.

The present invention utilizes the fact that these electrons have effective masses of different signs depending on their energy to effectively perform the velocity modulation of electrons as proposed by Sakaki et al. It provides:

〔Example〕

Embodiment 1 FIG. 1(a) is a cross-sectional view of the FET of the first embodiment of the present invention, and FIG. 1(b) is a plan view of the FET of FIG.
FIG. 1A is a view taken in the direction of arrow B in FIG.

In the figure, 3 is a semi-insulating GaAs substrate, 4 is a GaAs layer not doped with impurities, 5 is an n-type A Qo,
aGa 0.7A 8 layers, 6 is an n-type GaAs layer (in this example, an n-type as shown in the figure) having a periodic structure in the source and drain direction, that is, the direction perpendicular to the channel direction (in the direction of the arrow). 10.11 is a source and drain region, 7.8 is a source and drain electrode, 9 is a gate electrode, and 12 is a G a
A s layer 4 and n-type A Do, aGao, 7A s
Two-dimensional electrons are generated near the interface of layer 5.

A method of manufacturing this FET will be explained. First, as shown in FIG. 4, a 500 nm thick GaAs layer 4, which is not intentionally doped with impurities, is epitaxially grown on a semicytotic GaAs substrate 3 by molecular beam epitaxy (MBE). , Si on top of it 2×10”a
Containing n-type Afio, 5Gao, 7As at a concentration of n-3
Layer 5 was grown to a thickness of 30 nm (thickness in the range 10-100 nm) and further Si was grown at 2 × 10
An n-type Ga As layer 6 containing a concentration of "am-" is 3
Grow to a thickness of 0 nm (10-100 nm thickness).

Next, using a combination of an electron beam lithography method and a dry etching method, the n-type GaAs layer 6 is formed to have a width of 25 nm and a spacing of 25 r, as schematically shown in FIG.
Process into m stripes.

Next, using photolithography, the photoresist was removed only at the locations where the source and drain of the field effect transistor were to be formed, and then 2 layers of Au containing 8% Ge were removed.
After depositing 20 nm of Ni and 200 nm of Au, the source and drain electrodes 7 were formed by lift-off method.
, 8. (The drawing is a schematic diagram, and the film thickness in the drawing does not match the actual film thickness.) Furthermore, when heating at 450°C for 1 minute in a hydrogen atmosphere, the source and drain electrodes 7 and 8 Impurities diffuse from
As shown by the broken line in FIG. 6, the source and drain regions 10
．． 11 is formed.

The process of forming the source and drain electrodes 7.8 and the source and drain regions 10.11 may be performed before the process of forming the n-type GaAs)i 6 in a striped shape in FIG. That is, source, drain fit17.8 and source, drain region 10.1
1 may be formed, and then n-type GaAs 7J6 may be formed in a striped pattern.

Next, 20 nm thick Ti, 20 nm Pt, and 300 nm thick Au were deposited on the region where the gate electrode was to be formed using the same photolithography method used to form the source and drain electrodes 7 and 8, and lift and Gate electrode 9 is formed by an off method.

In the FET manufactured in this way, n-type Ga
The cross section of A s W 6 parallel to the source and drain directions, that is, the channel direction, is as shown in FIG. 1(a).
It has a periodic structure along the same direction, and has a G a As layer 4 that is not doped with impurities and an n-type A (l o, a
G a 0. The concentration of electrons in the two-dimensional electron layer 12 induced near the interface of the TA three layer 5 is modulated with this period, and the potential felt by these electrons is equal to the potential shown in FIG. 2(b) above. It becomes a similar periodic potential.

In FETs with conventional structure, G is not doped with impurities.
a A SW and n-type A U o, aG a 0.7
Electrons induced at the A3p interface are confined in a deep potential well created by an electric field perpendicular to the interface, and are free to move like children only in a plane parallel to the interface. Although it behaves as a gas, in the FET of this example, the movement of electrons in this direction due to the periodic potential due to this periodic structure is defined by the relationship between momentum and electron energy shown in Figure 3 above. It becomes like this.

Here, when the gate voltage is swept in the positive direction, the Fermi degree gradually increases to A, A'.

An inflection point, denoted B, B', etc., is reached. Before and after this inflection point, the effective mass of the electron changes from positive to negative, as described above. Therefore, when the Fermi level passes through the inflection point, the electrons that had been accelerated until then receive acceleration in the opposite direction and are decelerated.

In this case, there is no need to pass through the barrier between the two channels as in the case of the transistor proposed by Sakaki et al., so a very fast response can be expected.

The transistor of this example was heated at liquid helium temperature (4,2'
When the gate voltage was increased from 0.3 V to 0.5 V while keeping the drain voltage at 0.5 V, the drain current decreased by half, showing the expected characteristics. . Further, the response time of the measurement system at this time was 100 picoseconds or less.

Note that in the above embodiments, a metal organic chemical vapor deposition method (MO-CVD method) may be used instead of the single molecular beam epitaxial method. In addition, 1 type Ano, 3 Gao, 7As layer 5
is a 6-layer m-thick A Q o,s that is not doped with impurities.
G a O, 7A 8 layers and 24 nm thick n-type A Q
When the FET was replaced with a superimposed one of o, aG a 0.7A SM, the transconductance of the FET was further improved and the noise figure was reduced. Furthermore, this n-type A 41
o, aG a 0.7A 8 layers 5 are effectively n
GaAs may be replaced with a superlattice structure in the thickness direction which has a smaller electron affinity than GaAs.
Although the explanation has been made using the A s / A Q o, aG a 0.7A S system, the same thing can be done with a system having a similar relative electron energy relationship.

Embodiment 2 FIG. 6 is a new view of the FET of the second embodiment of the present invention. In FIG. 0, which is a drawing corresponding to FIG. ? Ga without doping 5
AsM, 5 is n-type A+IQ, 3G, :1o, 7Asye
j, 6 is n-type Ga As PIj having a periodic structure in the direction perpendicular to the channel direction, 13 is n-type Ga
These are Zn-doped regions formed in periodic stripes in the As layer. Although not shown again, in this embodiment, as shown in FIG. 1(a), source and drain regions and source and drain electrodes are formed, and a gate electrode is also formed.

In this way, in this example, n-type GaAs was etched using a combination of electron beam lithography and dry etching in Example 1.
Instead of processing layer 6 into stripes, a focused ion beam accelerated to 50 kV is used to process Zn into stripes in 2X10”■-2
The FET of this example, which was manufactured by ion implantation under the following conditions, also has a periodic structure that reduces the electron mobility in the channel direction.
By improving MI, we were able to realize an FET with ultra-high mobility.

Embodiment 3 FIG. 7 is a sectional view of a MOSFET according to a third embodiment of the present invention, and in FIG. 0, which is a drawing corresponding to FIG.
14 is a Si substrate, 15 is a SiO processed into periodic stripes.
2 is a gate insulating film made of AQ, and 16 is a gate electrode made of AQ. Note that the source, drain region and source,
The drain electrode is a MOSFE of this embodiment (not shown).
Also in T, by forming a periodic structure in the gate insulating film 15, the mobility of electrons in the channel direction was dramatically improved, and an ultra-high mobility MOSFET was realized.

[Effects of the Invention] As explained above, the present invention forms a periodic structure r A negative region can appear, and large velocity modulation can be achieved by changing the acceleration that electrons receive in the channel direction due to the external electric field from positive to negative. Therefore, it is possible to realize an ultra-high speed FET that exceeds the operating limits of conventional FETs.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional view of the FET of the first embodiment of the present invention, FIG. 1(b) is a plan view of the FET shown in FIG. 1(a), and FIG. 2(a) is the main A schematic diagram of semiconductor layers laminated in a superlattice shape to explain the principle of the invention, FIG. 2(b) is a schematic diagram of its potential, and FIG. 3 shows the relationship between electron energy and wave number in the semiconductor device of the present invention. 4 and 5 are diagrams for explaining the manufacturing process of the FET according to the first embodiment of the present invention, and FIG. 6 is a diagram showing the FET manufacturing process according to the second embodiment of the present invention.
A cross-sectional view of the ET, FIG. 7 is a MOS of the third embodiment of the present invention.
It is a sectional view of FET. 1... Semiconductor layer 1.2... Semiconductor layer 2.3... Semi-insulating GaAs substrate, 4... GaAsJl not doped with impurities, 5- n-type A Q o, aG a
0.7A 3 layers, 6- n-type GaAs layer, 7... drain electrode, 8... source lN4i, 9... gate l
Electrode, 10... Drain region, 11... Source region, 12... Two-dimensional electronic layer, 13... Zn doped region, 14... Si substrate, 15... Gate insulating film (S
i 02 2nd ward (CL) grass 2 hard (b) (=) (d) (I) (ff) (1) 3rd
Tsumei 4 Ward D ~ Co-j Man 5 Z

Claims (1)

[Claims] 1. At least one of the semiconductor, insulating layer, or conductive layer has a periodic structure extending in the same direction, and the periodic structure has an effective electron effect related to interlocking in the above-mentioned direction. 1. A semiconductor device, characterized in that the mass is formed so that it can be positive or negative depending on its energy, and has at least one pair of carrier transmitting/receiving means and means for controlling the concentration of carriers on the periodic structure. 2. In the above semiconductor device, the period of the periodic structure is about 50
The semiconductor device according to claim 1, characterized in that the thickness is 5000 Å.