JP2609587B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2609587B2 JP2609587B2 JP61089961A JP8996186A JP2609587B2 JP 2609587 B2 JP2609587 B2 JP 2609587B2 JP 61089961 A JP61089961 A JP 61089961A JP 8996186 A JP8996186 A JP 8996186A JP 2609587 B2 JP2609587 B2 JP 2609587B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrons
- semiconductor
- conductivity type
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims 4
- 230000000737 periodic effect Effects 0.000 description 16
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/158—Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係り、特に超高周波で動作する
半導体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that operates at a very high frequency.
従来の電界効果トランジスタ（以下、FETと略記す
る）の動作限界を超える超高移動度FETが、榊（H.Sakak
i）らによって、ジャパニーズ・ジャーナル・オブ・ア
プライド・フィジックス第19巻 第94頁（1980年）（Jp
n.J.Appl.Phys.19（1980）94）に提案されている。この
FETはチャネル層の幅を十分に細くし、このチャネル内
に閉じ込められた電子が実効的にはチャネル方向にのみ
運動の自由度を有する量子井戸細線の条件を満たすよう
にした場合、チャネル内の電子が散乱される確率が極端
に小さくなり、その移動度は107〜108cm2/V・ｓにも達
するとされている。An ultra-high mobility FET that exceeds the operating limit of a conventional field-effect transistor (hereinafter abbreviated as FET) has been developed by H. Sakak
i) et al., Japanese Journal of Applied Physics, Vol. 19, p. 94 (1980)
nJAppl.Phys. 19 (1980) 94). this
In the FET, the width of the channel layer is made sufficiently thin so that electrons confined in the channel can effectively satisfy the condition of a quantum well wire having a degree of freedom of movement only in the channel direction. The probability that electrons are scattered becomes extremely small, and the mobility is said to reach 10 7 to 10 8 cm 2 / V · s.
しかしながら、上記FETにおいては、チャネルの側面
での電子の散乱の確率を小さくできる微細な幅を持った
チャネル層を作製することは、現在の微細加工技術によ
っては困難であり、実現性に乏しい。However, in the above-mentioned FET, it is difficult to fabricate a channel layer having a fine width that can reduce the probability of scattering of electrons on the side surface of the channel by the current fine processing technology, and the feasibility is poor.
本発明の目的は、上記の困難を取り除き、チャネル内
の電子が実効的にチャネル方向のみに運動の自由度を有
するFETを提供することにある。An object of the present invention is to eliminate the above-mentioned difficulties and to provide an FET in which electrons in a channel effectively have a freedom of movement only in a channel direction.
まず、本発明の原理を説明するために、第２図（ａ）
に示すように、電子親和度ｘの異なる二種類の半導体層
１、２を超格子状に積層した場合を考える。First, in order to explain the principle of the present invention, FIG.
Let us consider a case where two types of semiconductor layers 1 and 2 having different electron affinities x are stacked in a superlattice pattern as shown in FIG.
半導体層１、２の電子親和度ｘおよび厚さをそれぞ
れ、x1、x2、ａ、ｂとした場合、積層半導体層内の伝導
電子の受ける実効的な静電ポテンシャルは、第２図
（ｂ）に示すようになる。すなわち、そのポテンシャル
は、上記半導体層の厚さ方向（矢印Ａ方向）に沿って深
さVD＝x1−x2の周期的ポテンシャルである。その電子エ
ネルギーＥは、第３図に模式的に示すような構造になる
ことは、クローニッヒおよびペニーによって論じられて
いるように周知のことである。（アール・ドゥ・エル・
クローニッヒ（R.de L.Kronig）およびダブリュー・ジ
ー・ペニー（W.G.Penney）によるプロスィーディングス
オブ ロイアル ソサイエティ オブ ロンドン）
（Proceedings of Royal Society of London）、第A130
巻（1931年）第499頁） 電子エネルギーＥと電子の波数ｋの関係を示す第３図
から明らかなように、図中、Ａ、Ａ′、Ｂ、Ｂ′等で示
した点が、Ｅ−ｋ曲線の変曲点になっていることがわか
る。（この波数ｋと運動量Ｐは、プランクの定数ｈを２
πで除した を用い、 の関係にある。）一方、固体物理学の教科書、例えば、
シー・キッテル（C.Kittel）著（宇野、津屋、山下訳）
「固体物理学入門上」（丸善株式会社、1981年出版）第
205頁に論じられているように、固体内の電子の有効質
量ｍ＊は、Ｅ−ｋ曲線を用い、次の関係式で与えられ
る。When the electron affinity x and the thickness of the semiconductor layers 1 and 2 are x 1 , x 2 , a, and b, respectively, the effective electrostatic potential received by the conduction electrons in the stacked semiconductor layers is shown in FIG. As shown in b). That is, the potential is a periodic potential having a depth V D = x 1 −x 2 along the thickness direction (the direction of arrow A) of the semiconductor layer. It is well known that the electron energy E takes on a structure as shown schematically in FIG. 3, as discussed by Kronig and Penny. (Art de El
Proseedings of Royal Society of London by R.de L.Kronig and WGPenney
(Proceedings of Royal Society of London), A130
As shown in FIG. 3, which shows the relationship between the electron energy E and the electron wave number k, the points indicated by A, A ', B, B', etc. in FIG. It can be seen that the point is an inflection point of the −k curve. (The wave number k and momentum P are represented by Planck's constant h being 2
divided by π Using In a relationship. On the other hand, solid state physics textbooks, for example,
Written by C. Kittel (Uno, Tsuya, Yamashita translation)
"Introduction to Solid State Physics" (Maruzen Co., 1981)
As discussed on page 205, the effective mass of electrons m * in a solid is given by the following relationship using the Ek curve.
この関係式から、第３図に示すＡ、Ａ′、Ｂ、Ｂ′等
変曲点の近くでは、電子の有効質量ｍ＊が非常に大きく
なり、Ａ、Ａ′、Ｂ、Ｂ′等の変曲点において、電子の
有効質量ｍ＊が無限大になることがわかる。すなわち、
第２図（ｂ）において、矢印Ａ方向に沿って電子の有効
質量が大きくなり、チャネル層Ｉおよびバリヤ層IIの繰
返しとなる。 From this relational expression, near the inflection point such as A, A ', B, B' shown in FIG. 3, the effective mass m * of the electron becomes very large, and A, A ', B, B', etc. At the inflection point, it can be seen that the effective mass m * of the electrons becomes infinite. That is,
In FIG. 2B, the effective mass of electrons increases along the direction of arrow A, and the channel layer I and the barrier layer II are repeated.
上記説明においては、半導体層の積層の厚さの方向の
電子の運動に関するものであり、積層の面方向の二次元
については、電子の運動は自由電子のそれと同等のもの
である。The above description relates to the movement of electrons in the direction of the thickness of the stack of semiconductor layers, and in two dimensions in the plane direction of the stack, the movement of electrons is equivalent to that of free electrons.
本発明は、上記の超格子状に積層した半導体層を用い
て説明したことから明らかなように、周期的構造を形成
することにより、周期的に繰返しのあるポテンシャルの
方向に沿って、ある点で、電子の有効質量が非常に大き
くなることを利用したものである。すなわち、本発明
は、半導体層、絶縁層もしくは導電層の少なくとも一層
に、同一方向に沿う周期的構造を有し、かつ該周期的構
造は、上記方向に沿った方向の運動に係る電子の有効質
量が大きいことにより電子が実効的に上記方向と垂直な
方向にのみ運動の自由度を有するように形成されている
ことを特徴とする。上記周期的な構造というのは、例え
ば上記層を周期50〜５、000Åの縞状に加工することに
よって形成される。As is apparent from the above description of the present invention using the semiconductor layers stacked in a superlattice pattern, by forming a periodic structure, a certain point along a periodically repeated potential direction can be obtained. This utilizes the fact that the effective mass of electrons becomes very large. That is, the present invention has a periodic structure in at least one of the semiconductor layer, the insulating layer and the conductive layer along the same direction, and the periodic structure is effective for electrons related to the movement in the direction along the direction. The feature is that electrons are formed so as to have a freedom of movement only in a direction perpendicular to the above-mentioned direction due to the large mass. The periodic structure is formed, for example, by processing the layer into a stripe shape having a period of 50 to 5,000 °.
固体内電子の有効質量がある方向に沿って非常に大き
くなるということは、この方向に向かっては電子は非常
に散乱され難いということを意味する。The fact that the effective mass of electrons in a solid becomes very large along a certain direction means that electrons are very hard to be scattered in this direction.
本発明は、この電子がある方向に向かっては、散乱さ
れ難いという現象を用いて、上述の榊らによる量子井戸
細線におけるのと同様な理由により、この方向に垂直な
方向の電界に対し、電子の移動度が非常に大きくなるこ
とを利用した半導体装置を提供するものである。The present invention uses the phenomenon that electrons are hardly scattered in a certain direction, and for the same reason as in the quantum well wire by Sakaki et al. An object of the present invention is to provide a semiconductor device utilizing the fact that the mobility of electrons becomes extremely large.
実施例１ 第１図（ａ）は、本発明の第１の実施例のFETの断面
図、第１図（ｂ）は、第１図（ａ）のFETの平面図（第
１図（ａ）のＢ方向矢視図）である。第１図（ａ）のＣ
方向矢視断面図を第６図に示す。Embodiment 1 FIG. 1 (a) is a cross-sectional view of an FET according to a first embodiment of the present invention, and FIG. 1 (b) is a plan view (FIG. 1 (a)) of the FET of FIG. 1 (a). FIG. C in FIG. 1 (a)
FIG. 6 is a sectional view taken in the direction of the arrow.
図において、３は半絶縁性GaAs基板、４は不純物をド
ープしないGaAs層、５はｎ形Al0.3Ga0.7As層、６はソー
ス、ドレイン方向すなわちチャネル方向と垂直な方向
（矢印Ａ方向）に周期的な構造を有するｎ形GaAs層（本
実施例では図示のごとくｎ形GaAs層が縞状に形成してあ
る。）、10、11はソース、ドレイン領域、７、８はソー
ス、ドレイン電極、９はゲート電極、12はGaAs層４とｎ
形Al0.3Ga0.7As層５の界面近くに誘起される二次元電子
層である。In the figure, 3 is a semi-insulating GaAs substrate, 4 is a GaAs layer not doped with impurities, 5 is an n-type Al 0.3 Ga 0.7 As layer, and 6 is a source and drain direction, that is, a direction perpendicular to the channel direction (arrow A direction). An n-type GaAs layer having a periodic structure (in this embodiment, the n-type GaAs layer is formed in stripes as shown), 10, 11 are source and drain regions, and 7, 8 are source and drain electrodes. , 9 is a gate electrode, 12 is a GaAs layer 4 and n
This is a two-dimensional electron layer induced near the interface of the Al 0.3 Ga 0.7 As layer 5.
このFETの製造方法について説明する。まず、第４図
に示すように、半絶縁性GaAs基板３の上に、分子線エピ
タキシ（MBE）法により、意識的には不純物をドープし
ないGaAs層４を厚さ500nmエピタキシャル成長させ、そ
の上にSiを２×1018cm-3の濃度で含むｎ形Al0.3Ga0.7As
層５を30nmの厚さで成長させ、さらにSiを２×1018cm-3
の濃度で含むｎ形GaAs層６を30nmの厚さで成長させる。A method for manufacturing this FET will be described. First, as shown in FIG. 4, a GaAs layer 4 not intentionally doped with impurities is epitaxially grown to a thickness of 500 nm on a semi-insulating GaAs substrate 3 by molecular beam epitaxy (MBE). N-type Al 0.3 Ga 0.7 As containing Si at a concentration of 2 × 10 18 cm -3
Layer 5 was grown to a thickness of 30 nm, and Si was added to 2 × 10 18 cm −3.
Is grown to a thickness of 30 nm.
次に、電子線描画法と、ドライエッチング法を組合せ
て用い、ｎ形GaAs層６を第４図のＤ−Ｄ断面を示す第５
図に模式的に示すように幅25nm、間隔25nmの縞状に加工
する。Next, an electron beam lithography method and a dry etching method are used in combination to form the n-type GaAs layer 6 on the fifth section shown in FIG.
As schematically shown in the figure, it is processed into a stripe shape having a width of 25 nm and an interval of 25 nm.
次いで、フォトリソグラフィを用いて、電界効果トラ
ンジスタのソースおよびドレインが形成される箇所のみ
のフォトレジストを除去した後、Geを８％含むAuを200n
m、Niを20nmさらにAuを200nm蒸着した後、リフト・オフ
法によりソース、ドレイン電極７、８を第６図に示した
ように形成する。（なお、図面は概略図であり、図面の
膜厚と実際の膜厚とは一致していない。） さらに、水素雰囲気中で450℃１分間の加熱を行なう
と、ソース、ドレイン電極７、８から不純物が拡散し、
第６図の破線で示すように、ソース、ドレイン領域10、
11が形成される。Next, after removing the photoresist only at locations where the source and the drain of the field-effect transistor are formed by using photolithography, Au containing 8% of Ge is replaced by 200 n of Au.
After depositing 20 nm of m and Ni and 200 nm of Au, source and drain electrodes 7 and 8 are formed as shown in FIG. 6 by a lift-off method. (Note that the drawing is a schematic diagram and the film thickness in the drawing does not match the actual film thickness.) Further, when heating is performed at 450 ° C. for 1 minute in a hydrogen atmosphere, the source and drain electrodes 7 and 8 are heated. Impurities diffuse from
As shown by the broken lines in FIG. 6, the source and drain regions 10,
11 is formed.
このソース、ドレイン電極７、８およびソース、ドレ
イン領域10、11を形成するプロセスは、第５図における
ｎ形GaAs層６を縞状に形成するプロセスの前に行なって
も良い。すなわち、ソース、ドレイン電極７、８および
ソース、ドレイン領域10、11を形成してからｎ形GaAs層
６を縞状に形成してもよい。The process of forming the source and drain electrodes 7 and 8 and the source and drain regions 10 and 11 may be performed before the process of forming the n-type GaAs layer 6 in stripes in FIG. That is, the n-type GaAs layer 6 may be formed in stripes after the source and drain electrodes 7 and 8 and the source and drain regions 10 and 11 are formed.
次いで、先にソース、ドレイン電極７、８を形成した
のと同様なフォトリソグラフィ法により、ゲート電極を
形成すべき領域に厚さ20nmのTi、20nmのPtおよび300nm
のAuを蒸着し、リフト・オフ法によりゲート電極９を形
成する。Next, by a photolithography method similar to that in which the source and drain electrodes 7 and 8 were previously formed, a 20 nm thick Ti, 20 nm Pt and 300 nm
Is deposited, and a gate electrode 9 is formed by a lift-off method.
このようにして作製したFETにおいては、ｎ形GaAs層
６のソース、ドレイン方向すなわちチャネル方向に垂直
な断面は、第１図（ａ）に示すように、同一方向に沿う
周期的な構造になっており、不純物をドープしないGaAs
層４とｎ形Al0.3Ga0.7As層５の界面近くに誘起される二
次元電子層12の電子の濃度は、この周期で変調され、か
つこれらの電子が感じるポテンシャルは、上記の第２図
（ｂ）に示したポテンシャルと同様な周期的ポテンシャ
ルとなる。In the FET fabricated in this manner, the cross section of the n-type GaAs layer 6 perpendicular to the source and drain directions, that is, the channel direction has a periodic structure along the same direction as shown in FIG. GaAs without impurity doping
The concentration of electrons in the two-dimensional electron layer 12 induced near the interface between the layer 4 and the n-type Al 0.3 Ga 0.7 As layer 5 is modulated at this period, and the potential felt by these electrons is as shown in FIG. A periodic potential similar to the potential shown in FIG.
従来構造のFETにおいては、不純物をドープしないGaA
s層とｎ形Al0.3Ga0.7As層の界面に誘起される電子は、
界面に垂直な方向の電界により生じる深いポテンシャル
の井戸の中に閉じ込められて、界面に平行な面内のみ自
由電子のように運動する二次元電子ガスとして振る舞う
が、本実施例のFETでは、この周期的構造による周期的
ポテンシャルによりこの方向の電子の運動は、上記の第
３図で示される運動量と電子エネルギーの関係で規定さ
れるようになる。In a conventional FET, GaAs without impurities is used.
The electrons induced at the interface between the s layer and the n-type Al 0.3 Ga 0.7 As layer are
It is confined in a well of deep potential generated by an electric field in a direction perpendicular to the interface, and behaves as a two-dimensional electron gas that moves like free electrons only in a plane parallel to the interface. Due to the periodic potential due to the periodic structure, the movement of the electrons in this direction is defined by the relationship between the momentum and the electron energy shown in FIG.
ここで、ゲート電圧を正の方向に掃引すると、フェル
ミ準位は、だんだんと上昇し、Ａ、Ａ′、Ｂ、Ｂ′等で
示される変曲点に到達する。この変曲点の近傍では、先
に述べたように、電子の有効質量が非常に大きくなり、
この有効質量が大きくなる方向に向かう電子の運動は止
まり、この運動は、ほぼ完全に一次元的になり、先の榊
らの提案の量子井戸細線の場合と同様に、チャネル方向
に向かう電子の移動度は非常に大きくなる。Here, when the gate voltage is swept in the positive direction, the Fermi level gradually rises and reaches inflection points indicated by A, A ', B, B', and the like. Near this inflection point, as mentioned earlier, the effective mass of the electrons becomes very large,
The movement of the electrons in the direction in which the effective mass becomes larger stops, and the movement becomes almost completely one-dimensional. As in the case of the quantum well wire proposed by Sakaki et al., The movement of the electrons in the channel direction is reduced. The mobility becomes very large.
第７図は、本実施例のFETの4.2゜Kにおける動作特性
の例を示す図である。図から明らかなように、このFET
の特性は、ゲート電圧VG＝0.4Vの付近で移動度が飛躍的
に大きくなり、相互コンダクタンスの顕著な増大が認め
られる。一般には、相互コンダクタンスがゲート電圧の
関数として、単調でないFETは、使い難いデバイスであ
るが、この相互コンダクタンスが異常に増大する付近に
バイアスとして使用することにより、非常に高い周波数
まで大きな増幅率を有するトランジスタとして使用でき
る。FIG. 7 is a diagram showing an example of operating characteristics of the FET of this embodiment at 4.2 ° K. As is clear from the figure, this FET
In the characteristics of (1), the mobility increases remarkably near the gate voltage V G = 0.4 V, and a remarkable increase in the mutual conductance is recognized. In general, FETs whose transconductance is not a function of gate voltage as a function of gate voltage are difficult devices to use.However, when this transconductance is used as a bias near an abnormal increase, a large amplification factor can be obtained up to very high frequencies. It can be used as a transistor having
なお、上記実施例において、分子線エピタキシャル法
の代わりに有機金属気相成長法（MO−CVD法）を用いて
もよい。また、ｎ形Al0.3Ga0.7As層５は、不純物をドー
プしない厚さ6nmのAl0.3Ga0.7As層と厚さ24nmのｎ形Al
0.3Ga0.7As層を重ね合せたもので置き代えたところ、FE
Tの相互コンダクタンスは更に向上し、雑音指数が減少
した。さらに、このｎ形Al0.3Ga0.7As層５は、実効的に
は、ｎ形でかつ電子親和度がGaAsより小さい厚さ方向の
超格子構造で置き変えても良い。また、ここでは、GaAs
/Al0.3Ga0.7As系を用いて説明したが、相対的な電子エ
ネルギーの関係が、これと類似の系でも同様のことが可
能である。In the above embodiment, a metal organic chemical vapor deposition method (MO-CVD method) may be used instead of the molecular beam epitaxial method. The n-type Al 0.3 Ga 0.7 As layer 5 is composed of a 6-nm thick Al 0.3 Ga 0.7 As layer not doped with impurities and an n-type Al
When the 0.3 Ga 0.7 As layer was replaced with a superposed layer, the FE
The transconductance of T further improved and the noise figure decreased. Furthermore, the n-type Al 0.3 Ga 0.7 As layer 5 may be replaced with an effective n-type superlattice structure having a lower electron affinity than GaAs. Also, here, GaAs
Although the description has been made using the / Al 0.3 Ga 0.7 As system, the same can be achieved with a system having a relative electron energy relationship similar thereto.
実施例２ 第８図は、本発明の第２の実施例のFETの断面図であ
り、第１図に対応する図面である。図において、３は半
絶縁性GaAs基板、４は不純物をドープしないGaAs層、５
はｎ形Al0.3Ga0.7As層、６はチャネル方向と垂直な方向
に周期的な構造を有するｎ形GaAs層、13はｎ形GaAs層に
周期的な縞状に形成したZnドープｐ型領域、９はゲート
電極である。本実施例においても、図示はしないが、第
６図に示すように、ソース、ドレイン領域およびソー
ス、ドレイン電極が形成されている。Embodiment 2 FIG. 8 is a sectional view of an FET according to a second embodiment of the present invention, and corresponds to FIG. In the figure, 3 is a semi-insulating GaAs substrate, 4 is a GaAs layer not doped with impurities, 5
Is an n-type Al 0.3 Ga 0.7 As layer, 6 is an n-type GaAs layer having a periodic structure in a direction perpendicular to the channel direction, and 13 is a Zn-doped p-type region formed in the n-type GaAs layer in a periodic stripe. , 9 are gate electrodes. Also in this embodiment, although not shown, source and drain regions and source and drain electrodes are formed as shown in FIG.
このように、本実施例は、実施例１において、電子線
描画法とドライエッチングの組合せにより、ｎ形GaAs層
６を縞状に加工する代りに、50kVに加速した集束イオン
ビームを用いて、Znを縞状に２×1012cm-2の条件でイオ
ン打ち込みしてその領域をｐ型に変換することにより作
製したものである。本実施例のFETにおいても、周期的
な構造を有することにより、チャネル方向の電子の移動
度を飛躍的に向上させ、超高移動度のFETを実現でき
た。As described above, in the present embodiment, the focused ion beam accelerated to 50 kV is used instead of processing the n-type GaAs layer 6 into stripes by the combination of the electron beam writing method and the dry etching in the first embodiment. It is manufactured by ion-implanting Zn in a striped condition under the condition of 2 × 10 12 cm −2 and converting the region to p-type. Also in the FET of the present example, by having a periodic structure, the mobility of electrons in the channel direction was dramatically improved, and an ultra-high mobility FET could be realized.
実施例３ 第９図は、本発明の第３の実施例のMOSFETの断面図で
あり、第１図に対応する図面である。図において、14は
Si基板、15は周期的な縞状に加工したSiO2から成るゲー
ト絶縁膜、16はAlから成るゲート電極である。なお、ソ
ース、ドレイン領域およびソース、ドレイン電極は、図
示省略する（第６図参照。）。本実施例のMOSFETにおい
ても、ゲート絶縁膜15に周期的な構造を形成したことに
より、チャネル方向の電子の移動度を飛躍的に向上さ
せ、超高移動度のMOSFETを実現できた。Embodiment 3 FIG. 9 is a sectional view of a MOSFET according to a third embodiment of the present invention, and is a drawing corresponding to FIG. In the figure, 14 is
An Si substrate, 15 is a gate insulating film made of SiO 2 processed into a periodic stripe, and 16 is a gate electrode made of Al. The illustration of the source and drain regions and the source and drain electrodes is omitted (see FIG. 6). Also in the MOSFET of the present embodiment, by forming a periodic structure in the gate insulating film 15, the mobility of electrons in the channel direction is dramatically improved, and an ultra-high mobility MOSFET can be realized.
以上説明したように、本発明は、同一方向に沿う周期
的構造を形成し、この方向に沿う電子の有効質量を大き
くすることにより、電子の運動を一次元的にすることが
可能であり、チャネル方向の電子の移動度を飛躍的に向
上させることができる。従って、従来のFETの動作限界
を超える超高移動度FETを実現することができる。As described above, the present invention can form a periodic structure along the same direction and increase the effective mass of electrons along this direction, so that the movement of electrons can be made one-dimensional. The mobility of electrons in the channel direction can be dramatically improved. Therefore, an ultra-high mobility FET exceeding the operation limit of the conventional FET can be realized.
第１図（ａ）は本発明の第１の実施例のFETの断面図、
第１図（ｂ）は第１図（ａ）に示したFETの平面図、第
２図（ａ）は本発明の原理を説明するための超格子状に
積層した半導体層の模式図、第２図（ｂ）はそのポテン
シャルの模式図、第３図は本発明の半導体装置における
電子エネルギーと波数の関係を示す図、第４図〜第６図
は、本発明の第１の実施例のFETの製造プロセスの説明
図、第７図は本発明の第１の実施例のFETの動作特性を
示す図、第８図は本発明の第２の実施例のFETの断面
図、第９図は本発明の第３の実施例のMOSFETの断面図で
ある。 １……半導体層１、２……半導体層２ ３……半絶縁性GaAs基板 ４……不純物をドープしないGaAs層 ５……ｎ形Al0.3Ga0.7As層 ６……ｎ形GaAs層、７……ドレイン電極 ８……ソース電極、９……ゲート電極 10……ドレイン領域、11……ソース領域 12……二次元電子層、13……Znドープ領域 14……Si基板 15……ゲート絶縁膜（SiO2膜） 16……Alゲート電極FIG. 1A is a sectional view of a FET according to a first embodiment of the present invention,
FIG. 1 (b) is a plan view of the FET shown in FIG. 1 (a), FIG. 2 (a) is a schematic view of a semiconductor layer stacked in a superlattice for explaining the principle of the present invention, and FIG. 2 (b) is a schematic diagram of the potential, FIG. 3 is a diagram showing the relationship between electron energy and wave number in the semiconductor device of the present invention, and FIGS. 4 to 6 are diagrams of the first embodiment of the present invention. FIG. 7 is an explanatory view of a manufacturing process of the FET, FIG. 7 is a view showing the operating characteristics of the FET according to the first embodiment of the present invention, FIG. 8 is a cross-sectional view of the FET according to the second embodiment of the present invention, FIG. FIG. 6 is a sectional view of a MOSFET according to a third embodiment of the present invention. 1 ...... semiconductor layer 1, 2 ...... semiconductor layer 2 3 ...... semi-insulating GaAs substrate 4 is not doped with ...... impurity GaAs layer 5 ...... n-type Al 0.3 Ga 0.7 As layer 6 ...... n-type GaAs layer, 7 ... Drain electrode 8 Source electrode 9 Gate electrode 10 Drain region 11 Source region 12 Two-dimensional electron layer 13 Zn-doped region 14 Si substrate 15 Gate insulation Film (SiO 2 film) 16 ... Al gate electrode
フロントページの続き (56)参考文献 特開 昭57−27073（ＪＰ，Ａ) 特開 昭57−71184（ＪＰ，Ａ) 特開 昭58−148463（ＪＰ，Ａ) 特開 昭60−241272（ＪＰ，Ａ) 特公 昭42−4704（ＪＰ，Ｂ１) 特公 昭50−31435（ＪＰ，Ｂ１)Continuation of the front page (56) References JP-A-57-27073 (JP, A) JP-A-57-71184 (JP, A) JP-A-58-148463 (JP, A) JP-A-60-241272 (JP) , A) JP-B-42-4704 (JP, B1) JP-B-50-31435 (JP, B1)
Claims (2)
該基板上に順次積層して形成された不純物がドープされ
ていない化合物半導体からなる第１の半導体膜、第１導
電型を有する化合物半導体からなる第２の半導体膜、第
１導電型を有する化合物半導体からなる第３の半導体膜
と、当該第３の半導体膜上に形成されたゲート電極およ
び当該ゲート電極とはそれぞれ所定の間隔を介して互い
に対向して形成されたソース電極およびゲート電極を具
備し、上記第３の半導体膜には、第１導電型を有する線
状の領域と上記第１導電型とは逆の第２導電型を有する
線状の領域が、チャネル方向とは垂直な方向に、互いに
隣接して周期50〜５、000Åで交互に繰返し形成されて
いることを特徴とする半導体装置。1. A substrate made of a semi-insulating compound semiconductor, a first semiconductor film made of a compound semiconductor not doped with impurities and formed sequentially on the substrate, and a compound semiconductor having a first conductivity type. A second semiconductor film made of, a third semiconductor film made of a compound semiconductor having the first conductivity type, a gate electrode formed on the third semiconductor film, and the gate electrode are spaced apart from each other by a predetermined distance. And a source electrode and a gate electrode formed to face each other, and the third semiconductor film has a linear region having a first conductivity type and a second conductivity type opposite to the first conductivity type. The semiconductor device is characterized in that linear regions having the following are alternately formed at intervals of 50 to 5,000 ° adjacent to each other in a direction perpendicular to the channel direction.
上記第２導電型を有する線状の領域は、上記第３の半導
体膜の所定部分にZnをドープして形成されたｐ型領域で
あることを特徴とする特許請求の範囲第１項記載の半導
体装置。2. The semiconductor device according to claim 1, wherein the third semiconductor film is an n-type GaAs film,
2. The linear region having the second conductivity type is a p-type region formed by doping Zn in a predetermined portion of the third semiconductor film. Semiconductor device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089961A JP2609587B2 (en) | 1986-04-21 | 1986-04-21 | Semiconductor device |
| US07/040,123 US4796068A (en) | 1986-04-21 | 1987-04-20 | Semiconductor device having ultrahigh-mobility |
| EP87303474A EP0244140A3 (en) | 1986-04-21 | 1987-04-21 | A semiconductor device with periodic structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089961A JP2609587B2 (en) | 1986-04-21 | 1986-04-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62248261A JPS62248261A (en) | 1987-10-29 |
| JP2609587B2 true JP2609587B2 (en) | 1997-05-14 |
Family
ID=13985284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61089961A Expired - Lifetime JP2609587B2 (en) | 1986-04-21 | 1986-04-21 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4796068A (en) |
| EP (1) | EP0244140A3 (en) |
| JP (1) | JP2609587B2 (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63316484A (en) * | 1987-06-19 | 1988-12-23 | Fujitsu Ltd | Quantum effect semiconductor device |
| JPH0812913B2 (en) * | 1988-11-07 | 1996-02-07 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| DE59010851D1 (en) * | 1989-04-27 | 1998-11-12 | Max Planck Gesellschaft | Semiconductor structure with a 2D charge carrier layer and manufacturing method |
| US5385865A (en) * | 1990-04-26 | 1995-01-31 | Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften | Method of generating active semiconductor structures by means of starting structures which have a 2D charge carrier layer parallel to the surface |
| EP0535293A1 (en) * | 1991-01-29 | 1993-04-07 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. | A method of fabricating a compositional semiconductor device |
| US6242765B1 (en) * | 1991-05-21 | 2001-06-05 | Nec Corporation | Field effect transistor and its manufacturing method |
| DE69219688T2 (en) * | 1991-06-24 | 1997-12-18 | Sharp Kk | Semiconductor device and method of manufacturing the same |
| JPH0575139A (en) * | 1991-09-12 | 1993-03-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH05114615A (en) * | 1991-10-21 | 1993-05-07 | Rohm Co Ltd | Compound semiconductor device and manufacture of the same |
| US5283445A (en) * | 1991-11-29 | 1994-02-01 | Fujitsu Limited | Quantum semiconductor device employing quantum boxes for enabling compact size and high-speed operation |
| US5274246A (en) * | 1992-05-04 | 1993-12-28 | The United States Of America As Represented By The Secretary Of The Air Force | Optical modulation and switching with enhanced third order nonlinearity multiple quantum well effects |
| JP2748797B2 (en) * | 1992-10-06 | 1998-05-13 | 三菱電機株式会社 | Semiconductor device |
| US5908306A (en) * | 1993-01-29 | 1999-06-01 | Sony Corporation | Method for making a semiconductor device exploiting a quantum interferences effect |
| KR0137601B1 (en) * | 1994-09-16 | 1998-04-28 | 양승택 | Quantum interference transistor |
| RU2141699C1 (en) * | 1997-09-30 | 1999-11-20 | Закрытое акционерное общество Центр "Анализ Веществ" | Process of formation of solid nanostructures |
| AUPR157500A0 (en) * | 2000-11-20 | 2000-12-14 | Silverbrook Research Pty. Ltd. | An apparatus and method (bin02) |
| US8829336B2 (en) | 2006-05-03 | 2014-09-09 | Rochester Institute Of Technology | Nanostructured quantum dots or dashes in photovoltaic devices and methods thereof |
| KR101388721B1 (en) | 2012-10-26 | 2014-04-25 | 삼성전기주식회사 | Semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2261527C2 (en) * | 1972-12-15 | 1983-04-21 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V., 3400 Göttingen | Semiconductor body with alternately successive n- and p-doped zones in a predetermined direction, method for its production and uses of the semiconductor body |
| DE2338388C2 (en) * | 1973-07-28 | 1982-04-15 | Ibm Deutschland Gmbh, 7000 Stuttgart | Field effect semiconductor device |
| JPS5727073A (en) * | 1980-07-25 | 1982-02-13 | Nippon Telegr & Teleph Corp <Ntt> | Normally off tipe schottky gate filed-effect transistor |
| JPS5771184A (en) * | 1980-10-22 | 1982-05-01 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS58148463A (en) * | 1982-02-26 | 1983-09-03 | Mitsubishi Electric Corp | Mes type field effect transistor |
| JPS609174A (en) * | 1983-06-29 | 1985-01-18 | Fujitsu Ltd | Semiconductor device |
| GB8409316D0 (en) * | 1984-04-11 | 1984-05-23 | Gen Electric Co Plc | Semiconductor structures |
| JPS60241272A (en) * | 1984-05-15 | 1985-11-30 | Nippon Telegr & Teleph Corp <Ntt> | High-mobility transistor |
| US4733282A (en) * | 1985-08-13 | 1988-03-22 | International Business Machines Corporation | One-dimensional quantum pipeline type carrier path semiconductor devices |
| US4654090A (en) * | 1985-09-13 | 1987-03-31 | Xerox Corporation | Selective disordering of well structures by laser annealing |
-
1986
- 1986-04-21 JP JP61089961A patent/JP2609587B2/en not_active Expired - Lifetime
-
1987
- 1987-04-20 US US07/040,123 patent/US4796068A/en not_active Expired - Fee Related
- 1987-04-21 EP EP87303474A patent/EP0244140A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0244140A3 (en) | 1988-02-10 |
| US4796068A (en) | 1989-01-03 |
| EP0244140A2 (en) | 1987-11-04 |
| JPS62248261A (en) | 1987-10-29 |
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