JP3102475B2 - Tunnel element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET type tunnel device, and more particularly to a device having a fine gate length.
The present invention relates to a tunnel element having a large current driving capability and capable of performing a multifunctional operation.

[0002]

2. Description of the Related Art FIG. 3 (a) shows a planar structure of a tunnel element described in Japanese Patent Application No. 58-96766, and FIG. 3 (b) is a sectional view taken along line AA 'in FIG. 3 (a). .

An insulating film 307 exists in an element forming region on a semiconductor substrate 301, and the insulating film 307 exists in an element non-forming region.
Is thicker. A gate 308 exists on the insulating film 307. A source 302 and a drain 303 exist in an element formation region adjacent to the gate, and have opposite conductivity types.

Now, the conductivity type of the source 302 is n-type,
The conductivity type of 3 is p-type. When a positive voltage is applied to the gate 308 to induce a channel 304 made of electrons on the surface of the semiconductor substrate 301, the source 302 and the channel 304 are electrically connected because they have the same conductivity type. On the other hand, the channel 304 and the drain 303 form a PN junction because of the opposite conductivity type.

Here, when the impurity concentration is so high that the drain 303 is electrically degenerated and the impurity profile is steep,
The electrons in the channel 304 can be tunneled into the drain 303.

FIG. 3C shows that the drain 303 is
FIG. 4 is a band diagram along line BB ′ in FIG. 3B when is biased in the forward direction. Inversion layer 304 and drain 3
Since 03 is degenerated, electrons can flow from the inversion layer 304 to the drain 303 by tunneling. In this case, a negative differential characteristic is obtained as in the case of the forward bias in the tunnel diode. Further, the inversion layer 30
The electron concentration in 4 can be modulated by the voltage applied to the gate 308, and accordingly, the tunnel current value is also modulated. As a result, the transistor can be operated.

FIG. 3D shows that the source 303 is connected to the drain 303.
FIG. 4 is a band diagram along line BB ′ in FIG. 3 (b) when is biased in the reverse direction. In this case, source 302
On the other hand, when a positive voltage is applied to the drain 303, a non-saturated characteristic appears with respect to the drain voltage as in the case of the reverse bias in the tunnel diode. Also in this case, the current value can be modulated by the voltage applied to the gate 308,
Transistor operation can be realized.

[0008]

In the conventional tunnel element, the operation principle utilizes the inter-band tunneling phenomenon between the conduction band and the valence band. Therefore, in the case of an indirect band gap type semiconductor such as silicon or the like, At the time of band-to-band tunneling, interaction with the lattice is required, so that the tunnel probability is small and the current driving capability (several 10 nA) is poor.

Accordingly, a main object of the present invention is to greatly improve the poor current driving capability of a conventional tunnel element and realize a high-speed operation. Another object is to realize a significant reduction in the number of elements in a memory or a logic circuit.

[0010]

[0011]

[0012]

According to the present invention, there is provided a semiconductor device comprising: a first insulating film on a semiconductor substrate; a first gate electrode on the first insulating film; A second insulating film, a second gate electrode on the first and second insulating films, and first and second diffusion layers having the same conductivity type on the surface of the semiconductor substrate. A region exists with the second gate electrode interposed therebetween, and these diffusion layer regions are in contact with the second gate electrode.
A first gate electrode which has a portion which overlaps in a plane and does not overlap with the first gate electrode, wherein the gate length of the first gate electrode is about the wavelength of electrons; And a region having a length equal to or longer than the wavelength of electrons longer than the region, wherein the width of the region where the gate length of the first gate electrode is short is 0.1 to 50 nm. Related to the element.

In the present invention, the gate length of the first gate electrode in the region where the gate length is short is preferably 0.1 to 50 nm.

Further, the present invention relates to a memory and a logic circuit having the above-mentioned tunnel element.

[0015]

FIG. 1 (a) is a plan view of a reference example of a tunnel element . FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG.

An insulating film 107 exists on a semiconductor substrate 101 containing a p-type impurity of about 10 ¹⁴ to 10 ¹⁹ cm ⁻³ , and the insulating film 107
There is a lower gate 105 above. On this lower gate 105, there is an upper gate 106 via an insulating film 107.

The thickness of the insulating film 107 under the lower gate 105 is several nm.
The thickness of the insulating film 107 on the lower gate 105 is also about several nm to several tens nm.

Insulating film 107 in a region where no element is formed
Has a thickness of several tens nm to avoid electrical interference between devices.
It is as thick as several hundred nm.

On the surface of the semiconductor substrate 101 , an n-type impurity
Source 102 and drain 103 containing more than ¹⁹ cm ^-3 are upper gate
The upper gate 106 partially overlaps with the upper gate 106. The gate length of the lower gate 105 is as short as about the wavelength of electrons (up to 10 nm).

Next, the device operation in the present embodiment will be described.

By applying a positive voltage to the upper gate 106, an inversion layer 104 is induced on the surface of the semiconductor substrate 101. When the potential of the lower gate 105 is 0 V, the inversion layer 104 becomes a semiconductor.
It is formed on the surface of the body substrate 101 with the lower gate 105 interposed therebetween, and is not formed below the lower gate 105.

FIG. 1C shows a band diagram along the line BB 'in FIG. 1B. Since the inversion layer is not formed below the lower gate 105, a potential barrier is formed on the surface of the semiconductor substrate 101 below the lower gate. Since the lower gate length is about the wavelength of electrons, the potential barrier width is also about this, and when a positive voltage is applied to the drain 103 with respect to the source 102, electrons tunnel from the source side inversion layer to the drain side inversion layer. It becomes possible to do. Since the tunneling probability of electrons depends on the potential barrier height, the transistor operation becomes possible by modulating the potential barrier height by the lower gate 105.

The above structure can be formed by the following method.

A 100 nm silicon oxide film is grown on a silicon substrate containing about 10 ¹⁸ cm ^-3 boron by a CVD method. The oxide film is removed only in the element formation region by photolithography and wet etching.
Thereafter, a silicon oxide film having a thickness of about 3 nm is grown in the element formation region by thermal oxidation.

Subsequently, polysilicon is grown to a thickness of 30 nm by the CVD method.
After growing, this polysilicon is subjected to phosphorus diffusion at 900 ° C.
Next, polysilicon is processed by electron beam lithography and RIE to form a lower gate 105 having a gate length of 10 nm and a gate width of 10 μm.

Next, arsenic is irradiated with energy of 50 KeV to 10 ¹⁶ cm by photolithography technology and ion implantation technology.
^-2 Selectively implant into the substrate, source 102, drain 1
Form 03. Subsequently, after depositing a silicon oxide film having a thickness of 20 nm by the CVD method, annealing is performed at 900 ° C. in a nitrogen atmosphere to activate the ion implantation region.

Next, the semiconductor substrate 101 and the source 10 are formed by photolithography and wet etching.
2. A part of the insulating film on the drain 103 and the lower gate 105 is removed, and a contact hole is opened.

Finally, about 500 nm of aluminum is sputtered, and an electrode and an upper gate 106 are formed by photolithography and RIE.

In the device fabricated as described above, the upper gate 106 has 15 V, the source 102 has 0 V, and the drain 103
When 1 V was applied to the lower gate 105 and 0 V was applied to the lower gate 105, a drain current was observed at room temperature. Further, since this current is not observed in a device having a gate length of 100 nm, and the magnitude of the current does not change so much with a temperature change, it is considered that this current is a source-drain tunnel current. This current increased with an increase in the lower gate 105 voltage, and reached 1 μA at the lower gate voltage of 0.5 V.

FIG. 2A is a plan view of one embodiment of the tunnel element of the present invention. FIG. 2B is a cross-sectional view taken along the line AA ′ in FIG.

An insulating film 207 exists on a semiconductor substrate 201 containing a p-type impurity of about 10 ¹⁴ to 10 ¹⁹ cm ^-3.
There is a lower gate 205 above. On this lower gate 205, there is an upper gate 206 via an insulating film 207.

The thickness of the insulating film 207 under the lower gate 205 is several nm.
The thickness of the insulating film 207 on the lower gate 205 is also several nm to several tens nm.

Insulating film 107 in a region where no element is formed
Has a thickness of several tens nm to avoid electrical interference between devices.
It is as thick as several hundred nm.

On the surface of the semiconductor substrate 201 , an n-type impurity
Source 202 and drain 203 containing more than ¹⁹ cm ^-3 are upper gate
It is located across 206 and partially overlaps the upper gate 206. The gate length of the lower gate 205 is composed of two types of regions: a region having a short length of about the wavelength of electrons (up to 10 nm) and a region having a length equal to or longer than the wavelength of electrons. nm.

Next, the device operation in this embodiment will be described.

By applying a positive voltage to the upper gate 206, an inversion layer 204 is induced on the surface of the semiconductor substrate 201. When the potential of the lower gate 205 is 0 V, the inversion layer 204 becomes a semiconductor.
It is formed on the surface of the body substrate 201 with the lower gate 205 interposed therebetween, and is not formed below the lower gate 205.

FIG. 2 (c) shows a band diagram along the line BB 'in FIG. 2 (b). Since the inversion layer is not formed below the lower gate 205, a potential barrier is formed on the surface of the semiconductor substrate 201 below the lower gate. Since the lower gate length is about the wavelength of electrons, the potential barrier width is also about this. When a positive voltage is applied to the drain 203 with respect to the source 202, electrons tunnel from the source-side inversion layer to the drain-side inversion layer. It becomes possible to do. In this case, since the width of the region having a small gate length contributing to the tunneling current is about several tens of nm, the electrons in the inversion layer 204 on both sides of this region are quantized into a one-dimensional state, and the discrete energy Rankings are formed.

Now, as shown in FIG. 2C, energy levels E _S1 , E _S2 , and E _S3 are formed in the inversion layer on the source 202 side.
The energy order E _D1 in the inversion layer on the drain 203 side,
Shall E _D2, E _{D 3} are formed. The Fermi energies in the inversion layers on the source and drain sides are defined as energy orders E _{FS and} E _FD , respectively. When the drain voltage is low, the tunnel current does not flow because E _D1 <E _S1 <E _D2 , but when the drain voltage increases and E _S1 = E _D2 holds, the tunnel current flows. Further, when the drain voltage is increased and E _D2 <E _S1 <E _D3 , the tunnel current decreases. However, when E _S1 = E _D3 holds, the tunnel current increases again. As described above, in the present embodiment, it is possible to obtain a current-voltage characteristic in which the current periodically increases and decreases as the drain voltage increases. Further, since the tunneling probability of electrons depends on the potential barrier height, the transistor operation becomes possible by modulating the potential barrier height by the lower gate 205. In a region having a long gate length, tunneling between the source and the drain is impossible, so that a tunnel current does not flow in this region.

The above structure can be formed by the following method.

On a silicon substrate containing about 10 ¹⁸ cm ^-3 boron, a 100 nm silicon oxide film is grown by CVD. The oxide film is removed only in the element formation region by photolithography and wet etching.
Thereafter, a silicon oxide film having a thickness of about 3 nm is grown in the element formation region by thermal oxidation.

Subsequently, the polysilicon is grown to a thickness of 30 nm by the CVD method.
After growing, this polysilicon is subjected to phosphorus diffusion at 900 ° C.
Next, the lower gate 205 is formed by processing the polysilicon by electron beam lithography and RIE. This lower gate has two types of gate lengths (10 nm and 100 nm), and the width of the region having a short gate length is 30 nm.

Next, arsenic is irradiated with energy of 50 KeV to 10 ¹⁶ cm by photolithography technology and ion implantation technology.
^-2 Selectively implant into the substrate, source 202, drain 2
Form 03. Subsequently, after depositing a silicon oxide film having a thickness of 20 nm by the CVD method, annealing is performed at 900 ° C. in a nitrogen atmosphere to activate the ion implantation region.

Next, the semiconductor substrate 201 and the source 20 are formed by photolithography and wet etching.
2. A part of the insulating film on the drain 203 and the lower gate 205 is removed, and a contact hole is opened.

Finally, about 500 nm of aluminum is sputtered, and an electrode and an upper gate 206 are formed by photolithography and RIE.

In the device manufactured as described above, the upper gate 206 was set to 15 V, the source 202 was set to 0 V, and the lower gate 2 was set to 0 V.
When 05 is set to 0V and the drain voltage is applied,
Two drain current peaks were observed at drain voltages of 52 mV and 124 mV. In addition, since this current is not observed in a device having a uniform gate length of 100 nm, and the magnitude of the current does not significantly change with temperature,
This current is considered to be a tunnel current between the source and the drain. Also, this current increases as the lower gate 205 voltage increases, and the drain voltage is 50 mV and the lower gate voltage is 0.
It reached 10nA at 5V.

[0046]

As described above, in the tunnel element of the present invention, the in-band tunneling phenomenon is used. Therefore, even in an indirect band gap type semiconductor such as silicon, the conventional interband tunneling is used. In comparison with this, a larger tunnel current can be secured, and the driving capability is excellent. Further, the number of elements in a memory or a logic circuit can be significantly reduced by multi-valued logic using the negative differential resistance characteristic.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a reference example of a tunnel element .

FIG. 2 is an explanatory diagram of a tunnel element of the present invention.

FIG. 3 is an explanatory diagram of a conventional tunnel element.

[Explanation of symbols]

 101,201,301 Semiconductor substrate 102,202,302 Source 103,203,303 Drain 104,204,304 Inversion layer 105,205 Lower gate 106,206 Upper gate 107,207,307 Insulating film 308 Gate

Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/788 29/792

Claims (4)

(57) [Claims] 1. A semiconductor device comprising: a first insulating film on a semiconductor substrate;
A first gate electrode is provided on the first insulating film;
A second insulating film is present on the first gate electrode, a second gate electrode is present on the first and second insulating films, and a first and a second conductive film having the same conductivity type are formed on the surface of the semiconductor substrate . 2
Diffusion layer regions are present across the second gate electrode, and these diffusion layer regions overlap the second gate electrode in a planar manner.
A portion having an overlapping portion, and having a structure not overlapping the first gate electrode in a plan view, wherein the first gate electrode has a region whose gate length is about the wavelength of electrons, A region having a length equal to or longer than the wavelength of electrons longer than the region, wherein the width of the region where the gate length of the first gate electrode is short is 0.1
A tunnel element having a thickness of about 50 nm. Wherein said first tunnel device of claim 1, wherein the gate length of a short region of the gate length of the gate electrode is 0.1 to 50 nm. 3. A memory having the tunnel element according to claim 1. 4. A logic circuit comprising the tunnel element according to claim 1.