JPS6352261A - Management system for allocation of memory address - Google Patents

Abstract

PURPOSE:To reduce the area for access of main memory of each processor unit set in a common bus address space regardless of the capacity of the main memory, by providing an address conversion memory to each processor unit. CONSTITUTION:When a processor (Pro)41 of a processor unit (ProU)1a gives access to a main memory in a unit ProU1d, the Pro4a is connected to a common bus 2 owing to a fact that a buffer gate 22a becomes enable and outputs an address indicating a window area for access of the main memory onto the bus 2. The units ProU1b-1d compare high-order 4 bits of a common bus address with the contents of registers 25b-25d through common bus address comparators 24b-24d. In this case, however, coincidence is secured with the comparator 24d. At the same time, 8 bits (19-12) of the common bus address received by the ProU1d are given to an address conversion memory 27d and the page information is outputted. This page information and all 12 bits (11-0) of the common bus address are given to a main memory 6d.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a management system for memory address allocation, and particularly relates to a memory address allocation system in which a processor unit consisting of a processor and a main memory and other device modules are In a multiprocessor system to which a plurality of processor units can be connected, memory address allocation to the main memory in each processor unit, when viewed from the common bus side, is related to the management method.

[Conventional technology]

In the multiprocessor system described above, the processor in each processor unit can of course access the main memory within its own unit, but it can also access other processor units and other devices connected to the common bus. A module can be accessed using exactly the same procedure as accessing the main memory within its own unit, that is, with a single machine language instruction of the processor, and the main memory within the processor unit is In some cases, it is required to be accessible in some way not only by the processor to which it belongs, but also by other processor units or other device modules connected to a common bus.

As a method that can meet such demands, in conventional technology, a certain common address space range is fixedly allocated to the main memory of each processor unit among the address spaces of the processors in each processor unit. , the remaining portion of the processor address space is commonly allocated to each processor as a common bus address space, and the common bus address bits are allocated to address areas occupied by various device modules and to each processor unit. A method is used to allocate address areas for main memory according to the memory capacity of the actual device so as to avoid duplication.

FIG. 4 shows a method for address assignment, taking as an example a system consisting of three processor units. This diagram shows the space below address A (from address O to (A-
1) An example is shown in which addresses A and C are allocated as a common bus address space (addresses A to C).

An area corresponding to the capacity (M+bytes) of the main memory installed in processor unit a is allocated to A in the common bus address space.
The area (a',) from address to (A+M, -1) is filled with the capacity of the main memory installed in processor unit b (
M2 bytes) in the common bus address space (A+M
, ) address to (A+M, +M2-1) address area (b vehicle)
Then, an area corresponding to the capacity of the main memory (M3 bytes) installed in processor unit C is allocated to addresses (A+M, 4M2) to (A+M, +M2 + M3 1) in the common bus address space.
) address area (C'M). In addition, the area occupied by various device modules other than the processor unit is the area from address B to address C of the common bus address space (n
).

From the perspective of the processor in each processor unit, the address allocation described above means that not only the main memory in its own unit but also the areas for all the main memories and other device modules installed in other processor units 7) are This means that it is located in an address space that can be directly accessed by the own processor. This allows the processor in each processor unit to access the main memory installed in other processor units in exactly the same way as it accesses the main memory in its own unit. Other device modules with common bus mask functionality are also provided with access to main memory within each processor unit by accessing areas allocated within the common bus address space.

FIG. 5 shows an example of the configuration of a system for realizing the above method. Processor unit 1a to IC are connected to common bus 2
Each connected to each process.

Processors 4a to 4c and main memories 6a to 4c in the subunit
6c and the common bus 2 are connected via bus switches 5a to 5c, and the bus switches 5a to 5c are configured to select any pair of connections. The internal address comparison circuits 7a to 7C are connected to the processors 42 to 4C.
If the address value output from the processors 4a to 4C and the main memory 6
bus switches 5a to 5C to connect buses a to 6C;
bus switches 5a to 5C to control the processors 4a to 4C and otherwise connect the processors 4a to 4C to the common bus 2.
This is a circuit that controls the

Registers 9a to 9C correspond to processor units 1a to 1c.
The main memories 6a to 6c of each of the processors are stored in the register 9a (as shown in FIG. is “A”
”, register 9b has A+M,” and register 9C has “
Registers 83 to 8C are registers that store the final address of the above area (as shown in FIG. 4, register 8a is assigned
"A+M++1" in register 8b, "A+Ml+" in register 8b.
M2-1”, register 8C has “A” M (+M
2 + M3 1″ are assigned respectively)
This is a register that stores .

Note that here, both of the registers 9a to 9c and 8a to 8C may be switches.

Common bus address comparison circuits 103-10C compare the address value given from common bus 2 with the contents of registers 9a-9C and registers 8a-8C, and the address value given from common bus 2 is compared with the contents of registers 9a-9C. If the content is within the range specified by the contents of the registers 8a to 8C, the bus switches 5a to 5C are controlled to connect the common bus and the main memories 6a to 6C, and the bus switches 5a to 5C are If not, it has the function of not performing the above control. (Based on FIG. 4, the common bus address comparison circuit 10
Regarding a, the common bus address value is '''A~(A
+ M r 1 )'', a command is given to the bus switch 5a to couple the common bus 2 and the main memory 6a.)Address subtraction circuits 113 to 11
C is a circuit that subtracts the contents of the registers 9a-9C from the address value given from the common bus 2 and converts it into a relative address starting from O to be given to the main memories 63-6C. The converted value is converted into a common bus address when the common bus 2 and the main memories 6a to 6C are connected by the bus switches 5a to 5C, and is given to the main memories 6a to 6C.

Now, processor 4a in processor unit la
However, when an address is output in an attempt to make some kind of access, the address value is compared with a hardware fixed value (the value "A" shown in FIG. 4) in the internal address comparison circuit 7a, and the address value is compared with this fixed value. If the bus switch 5a is smaller than the value, the bus switch 5a connects the processor 4a and the main memory 6a based on the command from the comparator circuit 7a, and gives the address output by the processor 4a to the main memory 6a. This allows access to a predetermined address.

On the other hand, if the comparison result in the comparison circuit 7a is that the address value is greater than or equal to this fixed value, the comparison circuit 7a instructs the bus switch 5a to connect the processor 4a and the common bus 2, and the processor 4a The output address will be output to the common bus 2. The processor unit 1b and the IC receive the address of the common bus, and the common bus address comparison circuit 10b and IOC compare the values to the contents of registers 9b and 9c and register 3b, respectively.
, 3c.

Now, if the common bus address comparison circuit 10b determines that the common bus address value is within the range determined by the registers 9b and 8b, the bus switch 5b of the processor unit 1b will change the value based on the command from the common bus address comparison circuit 10b. The common bus 2 and the main memory 6b are connected, and the address converted by the address subtraction circuit 11b is given to the main memory 6b as a main memory address, so the processor 4a of the processor unit 1a uses the bus switch 5a41'. A predetermined address in the main memory 6b can be accessed via the communication bus 2° and the bus switch 5b.

On the other hand, the common bus address comparison circuit 10C of the processor unit 1c naturally determines that the common bus address value is not within the range determined by the registers 9c and 8c, and therefore the bus switch 5c does not receive the bus switching command and does not receive any accesses. No action is taken. Processor unit 1a
The various device modules 3a, 3b other than ~1c also receive the common bus address, and the one selected thereby is accessed by the processors 4a~4C.

Here, registers 9 of each processor unit 1a to IC
It is assumed that the range of common bus address bits determined by the contents of registers 3 to 9c and registers 8a to 8c, and that the areas occupied by common bus address bits by other equipment modules must not overlap. You should be careful.

[Problem that the invention seeks to solve]

The address allocation method described above allocates an area equivalent to the capacity of the main memory installed in each processor unit into a common bus address space among the address spaces of the processors in each processor unit. Therefore, the total capacity of main memory that can be implemented in each processor unit is limited by the size of the common bus address space.

For example, in FIG. 4, the total capacity of the main memory of each processor unit is limited as shown in the following equation.

M, +M2+M3≦B-A This depends on the size of the internal address space for main memory so that the processor can directly access the main memory in its own unit without going through the common bus, the capacity of the main memory installed in each processor unit, etc. This imposes a large restriction on the number of processor units that make up a multiprocessor system, which poses a problem in constructing the system.

An object of the present invention is to provide a main memory internal address space (size common to each processor unit) for the processor of each processor unit to directly access the main memory within its own unit when constructing a multiprocessor system. Each processor has access to a common bus address space, which is a part of the address space of the processor in each processor unit, so that restrictions regarding the main memory capacity that can be implemented in each processor unit and the number of connected processor units are extremely small. The object of the present invention is to provide a unit main memory address assignment and its management method.

[Means for solving problems]

A plurality of processor units having a processor and main memory are connected to a common bus together with other equipment modules,
In a multiprocessor system configured so that the processor in each processor unit can access the common bus side using exactly the same procedure as when accessing the main memory within its own unit, that is, with one machine language instruction of the processor, In addition, in addition to providing an area that occupies a limited address range corresponding to each processor unit in the address bits of the bus without overlapping, It stores a value corresponding to the upper bits of a predetermined length in the address that addresses the memory, and is addressed at the upper focus of a predetermined range of the common bus address information, and the address information 11 output by the processor in its own unit.
is also addressed and output to the processor within its own unit, and the processor sets its contents,
A changeable address translation memory is provided so that the value of common bus address information output by a certain processor unit or other device module on the common bus falls within the address range set for the own processor unit on the common bus. In this case, the output value from the address translation memory selected by the upper bits of a certain predetermined range of the common bus address information is used as the upper part of the main memory address information, and the output value of the address translation memory of the common bus address information is The main memory in the processor unit outputs common bus address information by removing the part used for addressing (using the address bit as the lower position of main memory address information, generating main memory address information and giving it to main memory. It also allows access from processor units or other equipment modules via a common bus.

[For production]

According to the present invention, by providing an address conversion memory in each processor unit, it is possible to convert a given common bus address to any main memory address within the unit. There is no need to allocate an area equivalent to 1 in the common bus address space for main memory access within the processor unit from the common bus, and it is only necessary to allocate a smaller area, regardless of the capacity of each main memory. O
Therefore, restrictions on the capacity of main memory installed in one processor unit, the number of processor units connected to a common bus, etc. are extremely relaxed, making it possible to construct a multiprocessor system with a large degree of freedom.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and exemplifies a method for allocating addresses in the main memory of each processor unit according to the present invention when applicable to a multiprocessor system consisting of four processor units. This diagram shows the address space of the processor in each processor unit as 1
6 megabytes (addresses 0 to J), of which 8 megabytes from addresses O to (D-1) are allocated as internal address space for main memory, and the remaining 8 megabytes (addresses D to J) are allocated as common bus addresses. An example of allocation as space is shown.

Processor unit a has area aM with capacity Mu bytes,
Processor unit) b is the capacity of the area M1. Hyde's processor unit lc is the area CM's capacity iMIJ Hyde's processor unit d is the area dM's capacity itM++
Hyde main memory is installed, and the processors in each processor unit can directly access the main memory within their own unit by accessing the main memory internal address space below address D. When each processor accesses with an address equal to or higher than address D, the access is to a common bus address space.

For the common bus address bits, a certain area is allocated to each processor unit without duplication, and this area is used to access the main memory in each processor unit from the common bus side. Hereinafter, this will be referred to as a window area, and the window area for processor unit C will be referred to as aH''.

The window area for processor unit b is bM”.

CM” for the window area for processor unit C.

Let the window area for processor unit d be dM''.

In FIG. 1, each window area provided for each processor unit occupies a 1 megabyte area in the common bus address space. In addition, the portions occupied by various device modules other than the processor unit are allocated to addresses ■ to J in area n of the common bus address space.

Now, when a processor in a processor unit attempts to access the main memory in another processor unit, it accesses the window area for the desired processor unit in the common bus address space. It is also assumed that other device modules can access the main memory in a desired processor unit by accessing the window area.

FIG. 2 shows an embodiment of a system configuration according to the present invention that enables the address allocation described above, and particularly mainly shows the address bus system within the processor unit. In addition, in FIG. 2, the processor unit 1b
and 1c are omitted.

The processors 22)la to 1d are connected to the common bus 2, respectively, and the processors 4a to 4 in the processor unit
d are connected to the main memories 6a to 6b via the Huffer gates 21a to 21C, and are connected to the Huffer gates 223 to 22d.
It is connected to the common bus 2 via. In addition, the main memory 6a
-6d are also connected to the common bus 2 via address translation memories 27a-27d and buffer gates 23a-23d.

Buffer gates 21a to 21d, buffer gate 223
22d, and the gate enable/disable in the breadth gates 23a to 23d is controlled by the bus switching control circuit 2.
Controlled by 03-20d.

The internal address comparison circuits 73 to 7d are connected to the processors 4a to 7d.
The value of the address output from the bus switching control circuit 202 is compared with a fixed value determined in advance by hardware (the value "D" in FIG. 1).
Give ~20d.

When the address value of the processor output is smaller than this fixed value, the bus switching control circuits 20a to 20d enable the amplifier gates 21a to 21d, and the processors 43 to
4d and the main memories 6a to 6d are coupled. Otherwise, the bus switching control circuits 20a-20d enable the buffer gates 22a-22d to couple the processors 43-4d to the common bus 2. (In addition, the main memory 6 in the own unit from the processors 4a to 4d
Access to a to 6d and the common bus 2 is basically the same as in the prior art. ) register 252
~25d is the number of bits determined by the size of the window area divided by the upper few bits of the common bus address information indicating the window area for the own processor unit among the window areas provided in the common bus address space for each processor unit. This is a register that stores the values of (Note that the registers 25a to 25d may be switches.) The common bus address comparison circuits 24a to 24d compare the address value given from the common bus 2 and the registers 25a to 25d.
If they match, the bus switching control circuits 20a to 20d are provided with buffer gates 233 to 23.
d is enabled, and a command is given to connect the main memories 6a to 6d and the address translation memories 27a to 27d. The address conversion memories 27a to 27d are connected to the selector 2.
Common bus 2 and processor 4a via 63-26d
- Connected to 4d. Address conversion memory 27a-27
d is allocated to a predetermined area in the main memory internal address space of the processor's address space, and when the processors 4a to 4d access this area, the selectors 263 to 26 are activated by the signal SEL.
d represents processors 4a to 4d and address translation memory 27;
a to 27d are switched, and the address of the processor output is given to the address conversion memory side.

This allows processors 4a to 4d to access address translation memories 27a to 27d.

Processors 4a to 4d are address translation memories 27a to 2
7d, the signal SEL is invalid, and the selectors 26a to 26d operate to connect the common bus 2 and the address translation memories 27a to 27d, and supply the common bus address to the address translation memories. The address conversion memories 27a to 27d have a predetermined capacity depending on the size of the internal address space for main memory,
Converted address values are stored in the memory by proseno +4, 1 to 4d, and output values from memory cells corresponding to addresses given to the address conversion memory are transmitted via Huffer gates 232 to 23d to main memories 6a to 6a. 6
It is designed to be given to d.

FIG. 3 explains the process of address translation,
This figure corresponds to the address assignment shown in FIG. First, it is assumed that the main memory internal address space (8 megabytes) in the processor unit is managed by paging in units of 4 kilobytes per page. The upper 4 bits of the common bus address consisting of 24 pins (bits 23 to 2).

20) is used to determine whether a window area for main memory access within the own unit has been selected;
All 8 bits from bit 19 to bit 12 become the address given to the address translation memory, ie, the index pointer of the address translation 'A table, and all 12 bits from bit 11 to bit 0 are given to the main memory as is as an intra-page offset. The address conversion table (memory) has 2 page information (page numbers) consisting of 11 bits.
Up to 56 items can be stored. The page information stored in the table specified by the index pointer is then given to the main memory as bits 22 to 12 of the main memory address. The most significant bit (bit 23) of the main memory address is given to the main memory as "0". In this way, the main memory address to be given to the main memory is formed from the given common bus address.

Now, let us consider a case where the processor 4a of the processor unit 1a attempts to access the main memory in the processor unit ld. The processor 4a is coupled to the common bus 2 by enabling the buffer gate 22a, and outputs on the common bus 2 an address pointing to the main memory access window area d" (FIG. 1) of the processor unit 1d. Processor unit 1
After receiving the common bus address, common bus address comparing circuits 24b to 24d compare the upper four pins (bits 23 to bit 20) of the common bus address with the contents (4 bits) of registers 25b to 25d. However, only the common bus address comparison circuit 24d of the processor 1d determines that the two match, and the others do not react.

At the same time, all 8 bits from bit 19 to bit 12 of the common bus address received by the processor unit 1d are given to the address translation memory 27d via the selector 26d, and the address translation memory 27d converts all the bits from the memory selected thereby. Outputs page information consisting of 11 bits. Then, in response to the match judgment notification from the common bus address comparison circuit 24d, the bus switching control circuit 20d enables the buffers 1 to 23d, and compares this page information with all bits 11 to 0 of the common bus address as the offset in the page. 12 focus is given to the main memory 6d. At this time, it is assumed that the address bit 23 is also given as a value "0" to the main memory 6d via the buffer 23d. (Not shown in Figure 2).

In this way, the processes of the processor unit 1a, step 4
a can access a predetermined address in the main memory within the processor unit 1d. from various device modules 3a and 3b other than the processor unit,
Access to main memory within the processor unit is handled in exactly the same way.

Here, in principle, the contents of the conversion between the common bus address and the internal main memory address are managed by the processor in the processor unit on the receiving side. Therefore, normally a processor and a device module within a processor unit will output a common bus address pointing to the corresponding window area when trying to access main memory within a processor unit, but no matter what internal main memory it is, It is converted into an address, so it is not directly known where in main memory the access is being made.

However, in this kind of multiprocessor system,
When the processor unit exchanges data with various device modules (input/output control device 1 communication control device), the processor unit sends commands to the device module, and also sends data to the device module by sending an address related to the main memory within its own unit to which data is to be transferred. As long as the processor unit that issues the command manages everything, the device module only has to access it based on the address information given by the processor unit, and the device module only has to access it based on the address information given by the processor unit. There is no need to know specifically what to access. Furthermore, access by one processor unit to the main memory of another processor unit is usually treated as so-called inter-processor communication.
In that case, the main memory area to be accessed can be limited depending on the role of inter-processor communication. Therefore, there is no problem if a fixed conversion value is stored in a fixed memory of the address conversion memory exclusively for communication between processors, and all processor units are aware of it.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of processors each having a processor and a main memory are connected to a common bus together with other device modules, and the address space of the common bus is within the address space of the processor of each processor unit. , and the processor accesses the main memory within its own processor unit using exactly the same procedure as the main memory access within its own processor unit.
In other words, in a multiprocessor system where the common bus side can be accessed by one machine language instruction of the processor,
An area with a limited address range for each processor unit is provided in the common bus address bits without overlapping, and an address for addressing the main memory within the own unit is provided between the main memory of each processor unit and the common bus interface section. It stores a value corresponding to the upper bits of a predetermined length in the common bus address information, and is addressed by the upper bits of a predetermined range of the common bus address information, and is also addressed by the address I output from the processor in its own unit. An address conversion memory is provided that can output the data to the processor in its own unit, and its contents can be set and changed by that processor, and when the own processor unit is accessed from the common bus side, The main memory address information is generated by the translated address value output from this address translation memory, which is derived from specific bit information of the given common bus address, and some other address bits of the common bus address. Since each processor unit can convert the given common bus address to any main memory address within the unit, the common bus address bits are provided for each processor unit's main memory access. SM
6 C. Regardless of the main memory capacity of each processor unit, it is only necessary to allocate a very small area, and it can be implemented in processor units due to the limited size of the common bus address space. Restrictions on the capacity of main memory and the number of processor units that can be connected to a common bus are extremely relaxed, and the effect is that it becomes possible to construct a multiprocessor system consisting of a large number of processor units each having a large capacity of main memory.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of memory address allocation according to the present invention, FIG. 2 is a block diagram of an embodiment of a multiprocessor system according to the present invention, and FIG. 3 is based on a memory address assignment and system embodiment according to the present invention. FIG. 4 is a diagram illustrating the concept of memory address allocation according to the conventional method. FIG. 5 is a diagram illustrating an example of the configuration of a multiprocessor system according to the conventional method. 1a-1d-11 Processor unit 2--Common bus 3a, 3b--Various device modules 4a-4d--Processor unit 6a-6d...-Main memory 7a-7d-1 Internal address comparison circuit 20a-20
d-bus switching control circuits 21a to 21d, 22a to 22d, 23a to 23c
l-・buffer gate

Claims (1)

[Claims] A plurality of processor units having a processor and a main memory are connected to a common bus together with other device modules,
In a multiprocessor system configured so that the processor in each processor unit can access the common bus side using the same procedure as accessing the main memory in its own processor unit, the address space of the common bus is allocated to each processor unit. In addition to providing an area that occupies a predetermined address range without overlapping, an area corresponding to the upper bits of a predetermined length in the address for addressing the main memory in each processor unit is provided between the main memory and the common bus interface section in each processor unit. A value that is addressed by the upper bits of a predetermined range in the common bus address information, and is also addressed by address information output by the processor in the own unit and output to the processor in the own unit, and the processor An address conversion memory whose contents can be set and changed is provided, and when the value of the address information output on the common bus is included in the range of addresses set on the common bus for the own processor unit, The output value from the address translation memory selected by a predetermined upper bit of the common bus address information is used as the upper part of the main memory address information, and the part of the common bus address information used for addressing the address translation memory is excluded. A memory address allocation management method characterized in that main memory address information is generated using address bits as a lower part of main memory address information and is provided to the main memory.