JPH03189754A - Shared memory access control circuit - Google Patents

Abstract

PURPOSE:To set data to an optional address of a memory space by subtracting the set value of an address setter with the address signal outputted from a microcomputer and granting an access to a shared memory when the preceding subtraction value is positive and coincident with the value set by a 1st address setter. CONSTITUTION:A head address setter 12 sets the lower rank address data of the head address of a shared memory 11 for the address spaces of microcomputers 1 and 4. A subtractor 13 performs the subtraction between the set value of the setter 12 and the output address data on both microcomputers 1 and 4. A coincidence detector 3 detects the coincidence be tween the result of the subtraction and the set value of an address setter 2a. Then an AND circuit 14 obtains the AND between the output of the detector 3 and the negative/positive codes outputted from the subtractor 13. Then an access request signal is produced to the memory 11. As a result, the data is set to an optional address of a memory space of a computer.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a shared memory access control circuit when a shared memory is shared by a plurality of microcomputers.

[Conventional technology]

A conventional circuit of this type is shown in Figure 50.
In the figure, ■ is a first microcomputer, 2 is a first address setter for setting the address of the shared memory 11, which will be described later, and 3 is an upper address signal of the first microcomputer 1 and a first address setting device. 4 is a second microcomputer; 4 is a second microcomputer;
5 is a second address setter for setting the address of the shared memory 11; 6 is for inputting the upper address signal of the second microcomputer 4 and the address setting signal of the second address setter 5; a second coincidence detector for detecting a coincidence; 7 is an arbitration logic that inputs the coincidence signals of the first defeat detector 3 and the second coincidence detector 6 to arbitrate access; 8 is an arbitration logic of the arbitration logic 7; After receiving the control signal, the first
A first switch 9 receives the control signal of the arbitration logic 7 and switches the control signals of the microcomputer 1 and the second microcomputer 4, and the lower address signal of the first microcomputer 1 and the second microcomputer 4. A second switch 10 receives a control signal from the arbitration logic 7 and switches the data bus between the first microcomputer 1 and the second microcomputer 4, and 11 is a shared memory. Next, the operation will be explained. First, to make the explanation easier to understand, it is assumed that the number of bits of the address buses of the first and second microcomputers 1.4 is 16 bits, that is, they have a memory space of 64 bytes. Here, the upper address signal refers to the upper 4 bits of the 16-bit address bus, and the lower address signal refers to the lower 12 bits of the 16-bit address. The memory size of the shared memory 11 is assumed to be 4 bytes. First, when the upper address signal of the first microcomputer 1 matches the address set by the first address setter 2, the output signal of the first coincidence detector 3 becomes valid and the shared memory 11 request access. If the second microcomputer 4 is not accessing the shared memory 11, the arbitration logic 7 includes a first switch 8 for switching the control signal, a second switch 9 for switching the lower address signal, and a third switch for switching the data. The switch 10 is all switched to the microcomputer 1 side to enable access by the first microcomputer 1. If the second microcomputer 4
is currently being accessed, until said access ends.
The first microcomputer 1 is on standby. As described above, the first and second microcomputers 1.4 can access the shared memory 11 from a plurality of microcomputers. FIG. 6 shows the first and second microcomputers 1.
This diagram schematically shows the arrangement of the shared memory 11 in the memory space of 4 bytes, and the memory space of the microcomputer that accesses the shared memory 11 of 4 bytes is always maintained in a fixed relationship. Then, the access conditions for the shared memory 11 are determined by checking the upper 4 bits of the address signal.

[Problem to be solved by the invention]

The conventional shared memory access control circuit is configured as described above, so it is 2fi bytes (n is an integer), and 2"
It is necessary to set the XM address (M is an integer) as the start address, and since it is not possible to set an arbitrary address as the start address, there are problems such as constraints on the system configuration. This invention was made in order to solve the above-mentioned problems, and it is possible to set an arbitrary address in a microcomputer memory space as the start address so that the memory area of the microcomputer can be used effectively and flexibly without wasting it. It is an object of the present invention to provide a shared memory access control circuit that can flexibly respond to changes in the start address when a program is stored in a ROM.

[Means to solve the problem]

The shared memory access control circuit according to the present invention sets the lower address data of the start address of the shared memory in the address space of the microcomputer using the start address setter, and combines the setting value of the start address setter and the output address data of the microcomputer. is subtracted by a subtracter, and a match detector detects whether the subtraction result matches the setting value of the address setter. Next, an AND circuit calculates the AND of the output of the coincidence detector and the positive and negative signs output from the subtracter to generate a shared memory access request signal.

[Effect]

The subtracter in this invention subtracts the setting value of the head address setter from the output address of the microcomputer,
Access to the shared memory is made possible when the result of the subtraction is positive and the coincidence detection circuit obtains a match with the set value of the address setter.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 5 are designated by the same reference numerals. In FIG.
a first address setter (address setter) in which the relationship between the address space of 1 and the real address of the shared memory 11 is set;
, 12 is a third address setter as a start address setter for setting lower address data of the start address of the shared memory 11 in the address space of the first microcomputer l, and 13 is an output address of the first microcomputer l. This subtracter subtracts the address data set by the third address setter 12 from the data, and outputs the subtraction result and a positive or negative sign output signal S of the subtraction result. 14 is an AND circuit which outputs the output signal D1 of the first coincidence detector 3.
and the sign output signal S of the subtracter 13. Note that the upper address Au, which is the output of the subtracter 13, is input to the first coincidence detector 3, and the lower address AL is input to the second switch 9. The sign output signal S is a logic “1” if the subtraction result of the subtracter 13 is positive (including “’0”);
A negative logic “0” is given to the AND circuit 14. Next, the operation will be explained. First, when the output address data of the first microcomputer 1 is smaller than the start address (for example, YoooH) of the shared memory 11 in the memory space of the first microcomputer 1, the sign output of the subtracter 13 is a logic "0". ”, the output of the AND circuit 14 is invalid, and the shared memory 11 is not accessed. Next, if the output address of the first microcomputer l is larger than the start address of the shared memory 11 in the memory space of the first microcomputer 1, and the result of the calculation by the subtracter 13 is If it matches the set upper address, AND circuit 1
4, that is, the output DI of the first coincidence detector 3 and the sign output signal S of the subtracter 13 both become logic "1", and a shared memory access request signal is given to the arbitration logic 7. At this time, if the second microcomputer 4 is not accessing the shared memory 11, the first microcomputer 1 accesses the shared memory 11. For example, as shown in FIG. 2, the number of bits of the address bus of the first microcomputer is 16 bits, the bit width of one address is 8 bits, and the number of address pins of the shared memory 11 is 12 bits (4 bits). bytes), then
The upper address has 4 bits and the lower address has 12 bits. In this invention, in the address space of the microcomputer, the starting address of the shared memory 11 is an arbitrary address YOOO.
When set to H, address Y000H is shared memory 1
It is converted to the lowest address of 1, and YOOOH+40
Address 95 is converted to the highest address of the shared memory 11. Next, the detailed operation of the address conversion of the present invention described above will be explained. First, the shared memory 1 shown in FIG. 3(b)
In the peripheral circuit diagram of No. 1, the first address is X0OO(H) (
(4 digits in hexadecimal) (X is any value from 0 to F (H)). The address of the first cell in the shared memory 11 is 000
(H) and does not depend on X. FIG. 3(a) shows the stored contents of the shared memory 11. That is, the start address of the shared memory 11 seen from the first microcomputer l is YOOO (H) (Y is any value from 0 to F (H)), and the start address of the shared memory 11 seen from the second microcomputer 2 is If the start address is X0OO(H), both CPUs! ! DATAO can be exchanged at the first address of each coexisting memory 11. As shown in FIG. 4(a), the starting address of the shared memory 11 is O≦X≦F(H
), and can be arbitrarily set within the range of O≦Y≦F(H). However, as shown in the address space setting diagram in Figure 4, etc., the first microcomputer 1
If you arbitrarily set a memory address (area) to 4 bytes in the address space of
If it is Z, access will be made from the second address of the actual shared memory 11 (because addresses A0 to A11 are connected to the shared memory 11 through a switch).
Addresses (Z-1) from address 0 cannot be accessed. Also, from address YOOOH+1000H to Y000H+1
Address 000H+ (Z-1) accesses an address in the shared memory 11 that does not actually exist. Therefore, in the case of this invention, since it is a problem that data that cannot be transferred between the second microcomputer 4 and the first microcomputer 1 is generated, 2 is deleted from the address of the first microcomputer 1. , conversion is performed so that when the starting address of the shared memory 11 in the address space of the first microcomputer 1 is accessed, the actual starting address of the shared memory 11 is accessed. In the above embodiment, the first microcomputer side has been described, but the present invention may also be applied to the second microcomputer and the same effects as in the above embodiment can be obtained.

【Effect of the invention】

As described above, according to the present invention, the set value of the address setter is subtracted from the address signal output from the microcomputer, and the subtracted value is positive and matches the value set by the first address setter. Since the shared memory can be accessed at the same time, data can be set at any address in the microcomputer's memory space, greatly increasing the degree of freedom in system configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a shared memory access control circuit showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of memory allocation of the present invention, FIG.
Figure (b) is a peripheral circuit diagram of the shared memory, Figure 4 (a), (
C) is an explanatory diagram of the address space of a microcomputer according to the present invention and a conventional case, FIG. 5 is a block diagram of a conventional shared memory access control circuit, and FIG. 6 is an explanatory diagram of conventional memory allocation. In the figure, 1 is the first microcomputer, 2a is the first address setter, 3 is the first coincidence detector, 4 is the second microcomputer, 11 is the shared memory, and 12 is the third (first) 13 is an address setter, 13 is a subtracter, and 14 is an AND circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a shared memory access control circuit that enables access to a shared memory of a microcomputer via a switch, a first address setter that sets lower address data of a first address of the shared memory in an address space of the microcomputer; a subtracter that subtracts the output address data of the microcomputer and the set address data of the head address setter and outputs the subtraction result and positive and negative sign signals; and an address space of the microcomputer and an actual address space of the shared memory. an address setter that sets a set value determined by the relationship with the address, a coincidence detector that detects a match between the subtraction result and the set value of the address setter, and a match between the output of the coincidence detector and the code signal. A shared memory access control circuit comprising: an AND circuit that calculates a logical product and generates an access request signal for the shared memory.