JPS6351674A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6351674A JPS6351674A JP19607486A JP19607486A JPS6351674A JP S6351674 A JPS6351674 A JP S6351674A JP 19607486 A JP19607486 A JP 19607486A JP 19607486 A JP19607486 A JP 19607486A JP S6351674 A JPS6351674 A JP S6351674A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- layer
- concentration
- type
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- -1 boron ions Chemical class 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 210000000744 eyelid Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、d1度の異な
る埋込層を一回の工程で形成する製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which buried layers having different degrees of d1 are formed in a single process.
従来、濃度の異なる埋込層を形成するには、最初に濃度
の低い埋込層を形成した後、濃度の高い埋込層するなど
の各々の別々の工程で形成していた。Conventionally, in order to form buried layers with different concentrations, a buried layer with a low concentration is first formed, and then a buried layer with a high concentration is formed in separate steps.
上述した従来の製造方法は、別々に形成するために、工
程が長くなる欠点がある。The above-described conventional manufacturing method has the disadvantage that the steps are long because they are formed separately.
上述した、従来の製造方法では、別々の工程で濃度の異
なる埋込J−を形成していたのに対し、本発明は、濃度
の低い埋込層を形成する箇所には薄い酸化gXを残し、
濃度の高い埋込層を形成する箇所は酸化膜を取り除き、
ポリシリコンを全面に形成することにより、イオン注入
と拡散を続けて行なうことで、濃度の異なる埋込層を形
成できる半導体装置の製造方法であることに独創的内容
を有する。In the conventional manufacturing method described above, the buried J- with different concentrations was formed in separate steps, whereas the present invention leaves a thin oxide g ,
The oxide film is removed from areas where a buried layer with high concentration will be formed.
The originality of this method is that it is a method for manufacturing a semiconductor device in which buried layers with different concentrations can be formed by forming polysilicon on the entire surface and successively performing ion implantation and diffusion.
本発明は、薄い酸化膜を残した箇所と酸化膜を取り除い
た箇所を形成した後、ポリシリコンを形成することによ
り、イオン注入と拡散により、1回の工程で異なる濃度
の埋込層を形成することができる半導体装置の製造方法
である。The present invention forms buried layers with different concentrations in a single process by forming polysilicon after forming areas where a thin oxide film is left and areas where the oxide film is removed. This is a method of manufacturing a semiconductor device that can be performed.
次に1本発明の製造方法について図面を参照して説明す
る。第1図は、本発明の実施例1の縦断面図である。Next, a manufacturing method of the present invention will be explained with reference to the drawings. FIG. 1 is a longitudinal sectional view of Example 1 of the present invention.
P型サブストレート1上に酸化膜2を形成したのち、フ
ォトリングラフィで、埋込層を形成する部分の酸化膜2
を除去し、レジストを取り除いた後、薄い酸化膜3をた
とえは100A形成し、−部分を、たとえばNPN ト
ランジスタのコレクタの埋込層を形成する部分の酸化膜
3をフォトリングラフィで取り除いた後、レジスト3を
除去する。After forming the oxide film 2 on the P-type substrate 1, photolithography is used to remove the oxide film 2 in the part where the buried layer will be formed.
After removing the resist, a thin oxide film 3 of, for example, 100A is formed, and after removing the oxide film 3 at the negative part, for example, the part where the buried layer of the collector of the NPN transistor is to be formed, by photolithography. , the resist 3 is removed.
〔第1図(a)〕
この後、ポリシリコンをたとえば700A成長した後、
N型不純物たとえばリンをP型すブストレート内にリン
が入いるようにE=70KeV、Φ=5X1015cm
イオン注入後、リン拡散を行なう。〔第1図(b)
〕
この後、高温で押し込むと、薄い酸化膜3上のポリシリ
コン中のリン拡散によるリンハ、薄い酸化膜3に防げら
れて、P型サブストレート1に拡散されない。この後、
ポリシリコンを酸化し、酸化膜を全面に取り除くと、P
型サブストレート1内に高濃度のN型不純物層5と低濃
度のN型不純物層6が形成されている。第1図(C)こ
の後、エピタキシャル成長をすると、高濃度のN型埋込
層5と低濃度のN型埋込層6が形成される。第1図(d
)
この後、酸化膜をマスクにして、コレクタリン9を行な
えば、低温でコレクタリン9は、高濃度のN型埋込層5
と接触できる。その後、ベース10とエミッタ12、コ
レクタコンタクト11を形成するが、ベース10直下は
、低濃度の埋込層6であるため、エピタキシャル厚が薄
くとも、埋込層6のせり上りが小さくなり、ベース直下
のエピタキシャル厚が大きく取れ、NPN )ランジス
タの耐圧を上げることができる。第1図(e)第2図は
、本発明の実施例2の縦断面図でおる。[FIG. 1(a)] After this, after growing polysilicon to, for example, 700A,
E=70KeV, Φ=5X1015cm so that phosphorus enters the plate of P-type N-type impurity.
After ion implantation, phosphorus diffusion is performed. [Figure 1 (b)
] Thereafter, when the phosphorus is pressed at a high temperature, phosphorus is diffused into the polysilicon on the thin oxide film 3 and is prevented from being diffused into the P-type substrate 1, which is prevented by the thin oxide film 3. After this,
When polysilicon is oxidized and the oxide film is completely removed, P
A heavily doped N-type impurity layer 5 and a lightly doped N-type impurity layer 6 are formed in a mold substrate 1 . FIG. 1(C) Thereafter, by epitaxial growth, a heavily doped N-type buried layer 5 and a lightly doped N-type buried layer 6 are formed. Figure 1 (d
) After that, if collector rinsing 9 is performed using the oxide film as a mask, the collector rinsing 9 will form a highly concentrated N-type buried layer 5 at a low temperature.
You can contact with. Thereafter, the base 10, emitter 12, and collector contact 11 are formed, but since the buried layer 6 with a low concentration is directly under the base 10, the rise of the buried layer 6 is small even if the epitaxial thickness is small, and the base The epitaxial thickness immediately below can be increased, and the withstand voltage of the NPN transistor can be increased. FIG. 1(e) and FIG. 2 are longitudinal cross-sectional views of a second embodiment of the present invention.
P型サブストレート14にN型拡散/1i15を形成す
る。第2図(al
この後、酸化膜16を形成した後、P型拡散層を形成す
る部分の酸化膜をフォトリングラフィで取り除いた後、
薄い酸化膜17を形成する。この後、絶縁層を形成する
部分とPNP トランジスタのコレクタの埋込層を形成
する部分の薄い酸化膜を取り除き、ポリシリコン18全
成長する。〔第2図(b)〕
この後、P型不純物たとえばポロンがシリコン中に入い
る様にイオン注入した後、ボロンを拡散する。高瞼で押
込みを行なった彼、ポリシリコン18を酸化した後、酸
化膜を全面取り除くと高濃度の埋込r−J l 9と低
濃度の埋込/1520が形成される。第2図(C1
この後、エピタキシャル成長すると、高@度のP型埋込
層19と低濃度のP型埋込層20が形成される。第2図
(d)
この後絶縁22と同時にコレクタ22を形成し、PNP
トランジスタのエミッタ23とベースコンタクト24
を形成する。〔第1図(e)〕コレクタ22直下の埋込
M+i19が高濃度であり、エミッタ23直下の埋込層
20が低濃度であるため、エピタキシャル厚が薄くても
PNP )ランジスタのペース巾が取れ、かつ低温の
熱処理で絶縁が取れる利点がある。An N-type diffusion/1i 15 is formed on the P-type substrate 14. FIG. 2 (al) After this, after forming the oxide film 16, the oxide film in the part where the P-type diffusion layer will be formed is removed by photolithography.
A thin oxide film 17 is formed. Thereafter, the thin oxide film on the part where the insulating layer is to be formed and the part where the buried layer of the collector of the PNP transistor is to be formed is removed, and the entire polysilicon 18 is grown. [FIG. 2(b)] After this, ions of a P-type impurity such as boron are implanted into the silicon, and then boron is diffused. After oxidizing the polysilicon 18 which has been indented with a high eyelid, the oxide film is completely removed to form a high concentration embedment r-Jl 9 and a low concentration embedment /1520. FIG. 2 (C1) After this, when epitaxial growth is performed, a high-concentration P-type buried layer 19 and a low-concentration P-type buried layer 20 are formed. to form PNP
Emitter 23 and base contact 24 of the transistor
form. [Fig. 1(e)] The buried M+i 19 directly under the collector 22 has a high concentration, and the buried layer 20 directly under the emitter 23 has a low concentration, so even if the epitaxial thickness is thin, the pace width of the PNP transistor can be secured. , and has the advantage of being able to provide insulation through low-temperature heat treatment.
以上説明したように本発明は、薄い酸化膜を形成した箇
所と酸化膜を取り除いた筒所を同一基板上に形成し、こ
の上にポリシリコンを形成することKより、イオン注入
と拡散を続けて行なえることにより、1回の工程で異な
る濃度の埋込層を形成できる効果がある。As explained above, in the present invention, a portion where a thin oxide film is formed and a tube portion from which the oxide film is removed are formed on the same substrate, and polysilicon is formed on this, so that ion implantation and diffusion are continued. By doing so, it is possible to form buried layers with different concentrations in a single process.
第1図(al〜(e)は、本発明の実施例1の縦断面図
、第2図(a)〜(e)は実施例2の縦断面図である。
1.14 ・・・・・・P型サブストレート、2,3,
13゜16.47.25・・・・・・酸化膜、4,18
・・・・・・ポリシリコン、5,6.15・川・・N型
埋込層、7,21・・・・・・N型エヒリキシャル層、
8.10,22,23・°°・・・P散拡散層、9,1
1,12.24・・・・・・N型拡散層、19.20
・・・・・・P型埋込層。
ゝ、
代理人 弁理士 内 原 ユ “町
第1図
第1図
第2図
グζFIGS. 1A to 1E are longitudinal sectional views of Example 1 of the present invention, and FIGS. 2A to 2E are longitudinal sectional views of Example 2. 1.14...・P type substrate, 2, 3,
13゜16.47.25...Oxide film, 4,18
...Polysilicon, 5, 6.15...N-type buried layer, 7,21...N-type epitaxial layer,
8.10,22,23・°°...P diffused layer, 9,1
1, 12.24...N-type diffusion layer, 19.20
...P-type buried layer.ゝ、Representative Patent Attorney Yu Uchihara "Town Figure 1 Figure 2 Figure ζ
Claims (1)
取り除く工程と、薄い酸化膜を形成する工程と、前記薄
い酸化膜の一部を取り除く工程と、ポリシリコンを成長
する工程と、不純物をイオン注入し、かつ拡散する工程
と、前記ポリシリコンを酸化する工程と、酸化膜を除い
た後、エピタキシャル成長する工程を含むことを特徴と
する半導体装置の製造方法。A step of forming an oxide film on a semiconductor substrate, a step of removing the oxide film, a step of forming a thin oxide film, a step of removing a part of the thin oxide film, a step of growing polysilicon, and an impurity A method for manufacturing a semiconductor device, comprising the steps of ion-implanting and diffusing polysilicon, oxidizing the polysilicon, and epitaxially growing the polysilicon after removing the oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19607486A JPS6351674A (en) | 1986-08-20 | 1986-08-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19607486A JPS6351674A (en) | 1986-08-20 | 1986-08-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6351674A true JPS6351674A (en) | 1988-03-04 |
Family
ID=16351767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19607486A Pending JPS6351674A (en) | 1986-08-20 | 1986-08-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6351674A (en) |
-
1986
- 1986-08-20 JP JP19607486A patent/JPS6351674A/en active Pending
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