JPS6350864Y2 - - Google Patents
Info
- Publication number
- JPS6350864Y2 JPS6350864Y2 JP1979155507U JP15550779U JPS6350864Y2 JP S6350864 Y2 JPS6350864 Y2 JP S6350864Y2 JP 1979155507 U JP1979155507 U JP 1979155507U JP 15550779 U JP15550779 U JP 15550779U JP S6350864 Y2 JPS6350864 Y2 JP S6350864Y2
- Authority
- JP
- Japan
- Prior art keywords
- coating
- printed pattern
- printed
- coatings
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000576 coating method Methods 0.000 claims description 29
- 238000007747 plating Methods 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- -1 etc. Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【考案の詳細な説明】
本案は特に半導体をプリントパターン上に直接
載置し金属細線で配線を施こす際にボンデイング
特性がよく、安価なプリント基板に関する。[Detailed Description of the Invention] The present invention particularly relates to an inexpensive printed circuit board that has good bonding characteristics when a semiconductor is placed directly on a printed pattern and wiring is performed using thin metal wires.
従来、半導体、特に発光ダイオードのような固
体表示素子をプリントパターン上に直接載置し、
金属細線(ワイヤ)で配線を施こして表示器を形
成するような場合、プリントパターンの表面は、
ワイヤボンド特性(よく密着しかつ引張荷重に対
しても強く固着されている)がよく、また発光ダ
イオードの光を反射する反射面ともなるように、
表面を金メツキしていた。しかし、金は高価であ
るため、全てのプリントパターン上を金メツキす
るとプリント基板はとても割高になつて表示器を
不当に高価なものとする。このため必要部分のみ
に金メツキする必要がある。この場合、メツキの
不要部分を被膜で覆つてからメツキするわけであ
るが、被膜の端部には気泡が残留しやすく、その
気泡のある部分のみメツキが不充分となつてしま
うことがよくある。 Conventionally, semiconductors, especially solid-state display elements such as light-emitting diodes, are placed directly on printed patterns.
When forming a display by wiring with thin metal wires, the surface of the printed pattern is
It has good wire bond properties (good adhesion and strong bonding against tensile loads), and also serves as a reflective surface to reflect the light from the light emitting diode.
The surface was plated with gold. However, gold is expensive, and if all printed patterns were gold plated, the printed circuit board would be very expensive, making the display unreasonably expensive. For this reason, it is necessary to gild only the necessary parts. In this case, the parts that do not need to be plated are covered with a film and then plated, but air bubbles tend to remain at the edges of the film, and it is often the case that only the areas with the air bubbles are insufficiently plated. .
さらに、被膜はプリントパターンの周縁部で膜
厚が薄くならざるを得ないが、極端に薄くなつた
り、プリントパターンの角部が露出すると、メツ
キに際して樹枝状のメツキ成長が得られる。これ
は、プリントパターンが相互に近接している場合
は特に生じやすい。このような樹枝状のメツキ成
長は隣接パターンと接触する事により短絡事故と
なるが、部品装着前であれば過電流法等により除
去可能である。しかしこの時は短絡事故に至らな
くて部品の装着作業中又は装着作業後に短絡事故
を生ずる場合も多く、この場合は処理出来ない。 Furthermore, the coating inevitably becomes thinner at the periphery of the printed pattern, but if it becomes extremely thin or the corners of the printed pattern are exposed, dendritic plating growth will occur during plating. This is particularly likely to occur if the printed patterns are close to each other. Such dendritic plating growth may cause a short circuit due to contact with adjacent patterns, but it can be removed by an overcurrent method or the like before parts are mounted. However, in this case, there are many cases in which a short-circuit accident does not occur, but rather occurs during or after the installation work of the parts, and in this case, it is impossible to solve the problem.
本案はこのような不都合をなくすために行なわ
れたもので、以下本案を詳細に説明する。 This proposal was made to eliminate these inconveniences, and will be explained in detail below.
第1図aはプリントパターン1(銅箔)が所望
の形状にエツチング等により形成された基板2′
の平面図であり、この例ではプリントパターン
1,1…は発光ダイオードの載置部3,3と、金
属細線(ワイヤ)のボンデイング部4,4と、こ
れら載置部3,3やボンデイング部4,4に連ら
なるリード部5,5…とから構成されている。 Figure 1a shows a substrate 2' on which a printed pattern 1 (copper foil) is formed into a desired shape by etching, etc.
In this example, printed patterns 1, 1, . It is composed of lead parts 5, 5, . . . connected to the lead parts 4, 4.
第1図bと第2図乃至第5図は本案実施例のプ
リント基板2を得る製造工程を示す基板断面図
で、第1図aのA−A断面図である第1図bを基
にしてある。プリント基板の基台6は、例えば紙
エポキシ樹脂、ガラスエポキシ樹脂等であり、こ
れに厚さ20乃至50μmの銅箔がプリントパターン
1として積層してある。第2図に示すように、こ
の基板のプリントパターン1を覆う第1の被膜7
をスクリーン印刷等の手段で設ける。この第1の
被膜7はエポキシ系の耐薬品特性の優れた樹脂と
かUVインクとかであつて厚さは8乃至23μmに
塗布硬化させる。この第1の被膜7から露出する
場所は載置部3,3とボンデイング部4,4およ
びこれらの周辺部(メツキ浴の状態により数10μ
m乃至数mm)であるが、必要に応じてプリントパ
ターンの全く存在しない基台表面やメツキしたい
端子部(図示せず)等は露出させる。このあとメ
ツキ浴に浸して、第3図のように、プリントパタ
ーン1の第1の被膜7,7…から露出した部分に
メツキ層8,8…を設ける。このメツキ層8,8
…は厚さ3乃至10μmのニツケル層と厚さ0.3乃至
1.0μmの金層から成る2層構造をしている。この
あと、前述した従来例の如く短絡事故を生じてい
る樹枝状のメツキ成長を除去し、第4図の如く第
2の被膜9,9…を設ける。第2の被膜9,9…
は第1の被膜7,7…を完全に覆いつくように第
1の被膜7,7より少し範囲を広くして印刷され
る。第2の被膜9,9…の材質はエポキシ系樹脂
等何でもよく、厚みも3乃至30μmとかなり粗雑
でよい。必要な事は、プリントパターン1の近接
している所や第1の被膜7,7…とメツキ層8,
8…の境界部分を確実に第2の被膜9,9で覆う
事であつて、その他の部分は第1の被膜7,7が
存在していても第2の被膜9,9はなくてもよ
い。 FIG. 1b and FIGS. 2 to 5 are board sectional views showing the manufacturing process for obtaining the printed circuit board 2 of the present embodiment, based on FIG. 1b, which is a sectional view taken along line A-A in FIG. There is. The base 6 of the printed circuit board is made of, for example, paper epoxy resin, glass epoxy resin, etc., and copper foil having a thickness of 20 to 50 μm is laminated thereon as the printed pattern 1. As shown in FIG. 2, a first coating 7 covering the printed pattern 1 of this substrate
is provided by means such as screen printing. The first coating 7 is made of epoxy resin with excellent chemical resistance or UV ink, and is coated and cured to a thickness of 8 to 23 μm. The areas exposed from this first coating 7 are the mounting parts 3, 3, bonding parts 4, 4, and their surrounding areas (several tens of μm depending on the state of the plating bath).
m to several mm), but if necessary, the base surface where no printed pattern exists or the terminal portion to be plated (not shown) are exposed. Thereafter, it is immersed in a plating bath to provide plating layers 8, 8, . . . on the portions of the printed pattern 1 exposed from the first coatings 7, 7, . This plating layer 8,8
...is a nickel layer with a thickness of 3 to 10 μm and a thickness of 0.3 to 10 μm.
It has a two-layer structure consisting of a 1.0 μm gold layer. Thereafter, the dendritic plating growth that causes the short-circuit accident as in the conventional example described above is removed, and second coatings 9, 9, . . . are provided as shown in FIG. Second coating 9, 9...
is printed in a slightly wider area than the first coatings 7, 7 so as to completely cover the first coatings 7, 7, . The material of the second coatings 9, 9, . . . may be any material such as epoxy resin, and the thickness may be as rough as 3 to 30 μm. What is necessary is the areas adjacent to the printed pattern 1, the first coating 7, 7... and the plating layer 8,
8... is to be reliably covered with the second coatings 9, 9, and the other areas can be covered even if the first coatings 7, 7 are present or the second coatings 9, 9 are not present. good.
第5図は、このようにして得られたプリント基
板2の載置部3,3に発光ダイオード10,10
を載置固着し、金線等の金属細線11,11でボ
ンデイング部4,4へ配線を施こした、表示器基
板を示すものである。 FIG. 5 shows light emitting diodes 10, 10 placed on the mounting parts 3, 3 of the printed circuit board 2 obtained in this way.
This figure shows a display board on which the wires are mounted and fixed, and wires are wired to the bonding parts 4, 4 using thin metal wires 11, 11 such as gold wires.
本案は上述の如く、基台6と、載置部3,3と
ボンデイング部4,4とを有し基台6上に設けら
れたプリントパターン1と少なくとも載置部3,
3とボンデイング部4,4とその周辺部分を除く
前記プリントパターン1上を覆う第1の被膜7,
7…と、プリントパターン1の前記第1の被膜
7,7…がない部分に施こされたメツキ層8,8
…と、第1の被膜7,7…とメツキ層8,8…と
の境界部分と第1の被膜7,7…とを覆う第2の
被膜9,9…とからなるものであるから、第2の
被膜によつて樹枝状のメツキ成長が固定されてい
るので後に続く工程での短絡事故は生ぜず、メツ
キ不安定な第1の被膜とメツキ層との境界部分も
第2の被膜で覆われているので種々の不都合も生
じずボンデイング特性は良好のまま保たれ、メツ
キの貴金属は必要部分のみなので安価となつたプ
リント基板が提供できる。 As described above, the present invention includes the base 6, the mounting parts 3, 3, and the bonding parts 4, 4, and the printed pattern 1 provided on the base 6 and at least the mounting parts 3, 4.
3 and a first coating 7 that covers the printed pattern 1 except for the bonding portions 4, 4 and the surrounding areas;
7... and plating layers 8, 8 applied to the portions of the printed pattern 1 where the first coatings 7, 7... are not present.
... and second coatings 9, 9, which cover the boundary portions between the first coatings 7, 7... and the plating layers 8, 8, and the first coatings 7, 7,... Since the dendritic plating growth is fixed by the second coating, short circuit accidents do not occur in subsequent processes, and the boundary between the first coating and the plating layer, where the plating is unstable, is also covered by the second coating. Since it is covered, various inconveniences do not occur and the bonding characteristics are kept good, and since the precious metal of the plating is only used in the necessary parts, it is possible to provide an inexpensive printed circuit board.
第1図aはプリント基板の平面図、第1図bと
第2図乃至第5図は本案実施例の基板の製造工程
を示す断面図である。
1……プリントパターン、2′,2……基板、
3,3……(半導体の)載置部、4,4……(金
属細線の)ボンデイング部、6……基台、7,7
……第1の被膜、8,8……メツキ層、9,9…
…第2の被膜。
FIG. 1a is a plan view of the printed circuit board, and FIG. 1b and FIGS. 2 to 5 are cross-sectional views showing the manufacturing process of the circuit board according to the present embodiment. 1...print pattern, 2' , 2 ...substrate,
3, 3... (semiconductor) mounting part, 4, 4... (metal thin wire) bonding part, 6... base, 7, 7
...First coating, 8,8... Plating layer, 9,9...
...Second coating.
Claims (1)
上に設けられたプリントパターンと、少なくとも
載置部とボンデイング部とその周辺部分とを除く
前記プリントパターン上を覆う第1の被膜と、プ
リントパターンの前記第1の被膜がない部分に施
こされたメツキ層と、第1の被膜とメツキ層との
境界部分と第1の被膜とを覆う第2の被膜とを具
備してなる事を特徴とするプリント基板。 a base, a printed pattern provided on the base having a mounting part and a bonding part, and a first coating covering the printed pattern excluding at least the mounting part, the bonding part and the peripheral parts thereof; , comprising a plating layer applied to a portion of the printed pattern where the first coating is not present, and a second coating covering the boundary portion between the first coating and the plating layer and the first coating. A printed circuit board characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1979155507U JPS6350864Y2 (en) | 1979-11-08 | 1979-11-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1979155507U JPS6350864Y2 (en) | 1979-11-08 | 1979-11-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5678288U JPS5678288U (en) | 1981-06-25 |
JPS6350864Y2 true JPS6350864Y2 (en) | 1988-12-27 |
Family
ID=29667373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1979155507U Expired JPS6350864Y2 (en) | 1979-11-08 | 1979-11-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6350864Y2 (en) |
-
1979
- 1979-11-08 JP JP1979155507U patent/JPS6350864Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5678288U (en) | 1981-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2002016181A (en) | Semiconductor device, manufacturing method thereof, and electrodeposition frame | |
JPS62216259A (en) | Manufacture and structure of hybrid integrated circuit | |
US5776801A (en) | Leadframe having contact pads defined by a polymer insulating film | |
JPH07106729A (en) | Manufacture of thick film circuit component | |
JP4362163B2 (en) | Manufacturing method of semiconductor device | |
JP3550875B2 (en) | Lead frame and semiconductor device using the same | |
US6933448B2 (en) | Printed circuit board having permanent solder mask | |
JP2006196922A (en) | Semiconductor device, manufacturing method thereof, and electrodeposition frame | |
US5731547A (en) | Circuitized substrate with material containment means and method of making same | |
US5406119A (en) | Lead frame | |
JPS6350864Y2 (en) | ||
JP3118509B2 (en) | Chip resistor | |
EP1367874A2 (en) | Printed circuit board having permanent solder mask | |
JP2717200B2 (en) | Method of forming overlay plating on electronic component mounting substrate | |
JP2714691B2 (en) | Manufacturing method of electronic component mounting board | |
KR101297662B1 (en) | Manufacture method of lead frame | |
JPS58182854A (en) | Resin-sealed semiconductor device and manufacture thereof | |
JPS6234466Y2 (en) | ||
JP2663789B2 (en) | Manufacturing method of carrier tape with bumps | |
JPS5938070Y2 (en) | hybrid integrated circuit | |
JPH033292A (en) | Circuit board and image sensor using the same | |
JP2526592Y2 (en) | IC module | |
JPH05190302A (en) | Chip resistor and its production | |
KR100201389B1 (en) | Semiconductor package | |
JPS6325727Y2 (en) |