JPS6350046A - Vessel for cryogenic cooling - Google Patents
Vessel for cryogenic coolingInfo
- Publication number
- JPS6350046A JPS6350046A JP61192660A JP19266086A JPS6350046A JP S6350046 A JPS6350046 A JP S6350046A JP 61192660 A JP61192660 A JP 61192660A JP 19266086 A JP19266086 A JP 19266086A JP S6350046 A JPS6350046 A JP S6350046A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- thermal expansion
- semiconductor element
- container
- bonding section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001816 cooling Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 17
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims abstract description 3
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 3
- 239000000956 alloy Substances 0.000 claims abstract description 3
- 229910017709 Ni Co Inorganic materials 0.000 claims abstract 2
- 229910003267 Ni-Co Inorganic materials 0.000 claims abstract 2
- 229910003262 Ni‐Co Inorganic materials 0.000 claims abstract 2
- 229910000833 kovar Inorganic materials 0.000 claims description 20
- 239000000758 substrate Substances 0.000 abstract description 16
- 239000011521 glass Substances 0.000 abstract description 10
- 229910001374 Invar Inorganic materials 0.000 abstract description 8
- 230000002265 prevention Effects 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 19
- 229910052594 sapphire Inorganic materials 0.000 description 15
- 239000010980 sapphire Substances 0.000 description 15
- 239000007788 liquid Substances 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- 238000005452 bending Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910004613 CdTe Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 1
- 102000016941 Rho Guanine Nucleotide Exchange Factors Human genes 0.000 description 1
- 108010053823 Rho Guanine Nucleotide Exchange Factors Proteins 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 101150114988 invA gene Proteins 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Containers, Films, And Cooling For Superconductive Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は高速素子など液体窒素温度に冷却して使用す
る半導体素子を接着する超低温用冷却用容器に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) This invention relates to an ultra-low temperature cooling container for bonding semiconductor elements such as high-speed elements that are cooled to liquid nitrogen temperature and used.
（従来の技術）
近年、科学技術計算用コンピュータ等では処理速度を速
くするために高速素子の要求が多くなっている。素子の
高速化にはいくつか方法があるが、その中に冷却による
高速化がある。例えばＳｉのＦＥＴでは液体窒素で冷却
すると数倍の光速化がはかれる。(Prior Art) In recent years, there has been an increasing demand for high-speed elements in computers for scientific and technical calculations in order to increase processing speed. There are several ways to increase the speed of devices, one of which is to increase speed by cooling. For example, when a Si FET is cooled with liquid nitrogen, the speed of light can be increased several times.
通常、ＩＣやトランジスタ等の半導体素子は金属やセラ
ミックで作られたパッケージに入っているか、あるいは
プラスチックでモールドされている。しかし、これらの
パッケージ等は冷却効率が悪く素子が充分に冷却されな
かったり、またはパッケージ等が熱膨張係数の差で破壊
されたりして超低温冷却用には適していない。そこで従
来は第３図に断面図を示すような構造の超低温冷却用容
器を使用していた。第３図を使って従来容器の構造を説
明する。超低温に冷却して使われる半導体素子２１が厚
さ ０．６關サフアイア板２２に銀ベースト等で接着さ
れている。サファイア板２２はＣｕ板２３にやはり銀ペ
ースト等で接着されている。Ｃｕ板２３はその周辺部で
他の端子板等の部品（図では省略している）の固定する
部品固定材で、半導体素子２１の冷却効率を落さないよ
うに熱伝導のよいＣｕが使われている。サファイア板２
２は緩衝材で、Ｃｕの熱膨張係数α。ｕ＝ １６．８×
１０−６と例えばＳｉの半導体素子の熱膨張係数α ＝
３．４Ｘ １０ ＝との差か大きいのでα とＳｉ
Ｃｕα の中間の熱膨張係数α −［
ｉ、７Ｘ１０’の］
ｓａｐミルサファイアわれている。Ｃｕ板２３はコ
バール（２９％Ｎｉ、１７％Ｃｏ、５４％Ｆｅ）基板２
４に例えば銀ロー付けで接着されている。サファイア板
２２．Ｃｕ板２３．コバール基板２４を合わせて素子接
着部と呼ぶ。コバール基板２４はガラス容器２５に溶着
されている。ガラス容器は２重管の様な構造で、内側は
コバール基板４が溶着され、外側はやはリコバールの口
金２６が溶着されている。口金２６にはドーナッツ状の
導入端子２７がロー付けされている。導入端子２７上に
は口金２８がロー付けされている。半導体素子２１をサ
ファイア板２２に接着し、ボンディングワイヤー２９で
、半導体素子２１と導入端子２７間を配線した後に、ふ
た３０を周辺部３１で溶接する。その後排気口３２から
真空排気して排気口１２を閉じて容器内部３３を真空に
封じて完成する。ガラス容器２５とコバール基板２４で
形成された凹部３４に液体窒素を注入して半導体素子２
１を冷却する。容器内部３３を真空にしたのは、容器内
部３３の気体による熱電導のために四部３４に注入した
液体窒素の蒸発速度を小さくするためである。またガラ
ス容器２５は四部３４の液体窒素の蒸発速度が、壁の熱
伝導で大きくなるのを防ぐために熱伝導率の小さいガラ
スを材料としている。そのために、コバール基板２４と
口金２６はガラスと溶着できるコバールを材料としてい
る。Semiconductor elements such as ICs and transistors are usually housed in packages made of metal or ceramic, or molded with plastic. However, these packages are not suitable for ultra-low-temperature cooling because they have poor cooling efficiency and the elements may not be cooled sufficiently, or the packages may be destroyed due to differences in thermal expansion coefficients. Therefore, conventionally, a cryogenic cooling container having a structure as shown in the cross-sectional view in FIG. 3 has been used. The structure of a conventional container will be explained using FIG. A semiconductor element 21, which is used after being cooled to an ultra-low temperature, is bonded to a sapphire plate 22 with a thickness of 0.6 mm using a silver base or the like. The sapphire plate 22 is also bonded to the Cu plate 23 using silver paste or the like. The Cu plate 23 is a component fixing material for fixing other components such as terminal boards (not shown in the figure) around the Cu plate 23, and Cu, which has good thermal conductivity, is used so as not to reduce the cooling efficiency of the semiconductor element 21. It is being said. Sapphire plate 2
2 is a buffer material, and the thermal expansion coefficient α of Cu. u= 16.8×
10-6 and, for example, the thermal expansion coefficient α of a Si semiconductor element =
The difference between 3.4X 10 = is large, so α and Si
The intermediate thermal expansion coefficient α − [ of Cuα
i, 7X10']
Sap mill sapphire is made. The Cu plate 23 is a Kovar (29% Ni, 17% Co, 54% Fe) substrate 2
4, for example, by silver soldering. Sapphire plate 22. Cu plate 23. The Kovar substrate 24 is collectively referred to as an element bonding section. The Kovar substrate 24 is welded to a glass container 25. The glass container has a double tube-like structure, and a Kovar substrate 4 is welded to the inside, and a Kovar cap 26 is welded to the outside. A donut-shaped introduction terminal 27 is soldered to the base 26. A cap 28 is soldered onto the introduction terminal 27. After bonding the semiconductor element 21 to the sapphire plate 22 and wiring between the semiconductor element 21 and the introduction terminal 27 using a bonding wire 29, a lid 30 is welded at the peripheral portion 31. Thereafter, the vacuum is evacuated from the exhaust port 32, the exhaust port 12 is closed, and the interior of the container 33 is sealed in a vacuum to complete the process. Liquid nitrogen is injected into the recess 34 formed by the glass container 25 and the Kovar substrate 24 to remove the semiconductor element 2.
Cool 1. The reason why the inside of the container 33 is made vacuum is to reduce the evaporation rate of the liquid nitrogen injected into the fourth part 34 due to heat conduction by the gas inside the container 33. Further, the glass container 25 is made of glass having low thermal conductivity in order to prevent the evaporation rate of the liquid nitrogen in the four parts 34 from increasing due to heat conduction from the walls. For this purpose, the Kovar substrate 24 and the base 26 are made of Kovar, which can be welded to glass.
上記超低温冷却用容器では、第４図に示すように凹部３
４に液体窒素３５を注入すると、サファイア板２２．Ｃ
ｕ板２３．コバール基板２４の熱膨張係数の違いで素子
接着部が湾曲し、半導体素子２１がサファイア板２２か
ら剥離する事故が発生した。サファイア板２２の厚さを
数倍に厚くすると、湾曲がかなり小さくなり、半導体素
子２１の剥離は防止できる。ところかサファイアは熱伝
導率が良くないので、半導体素子か充分に冷却できなく
なるという問題が新たに発生してしまう。In the ultra-low temperature cooling container, as shown in FIG.
When liquid nitrogen 35 is injected into the sapphire plate 22. C
u board 23. Due to the difference in the thermal expansion coefficients of the Kovar substrate 24, the element bonding portion was bent, causing an accident in which the semiconductor element 21 was peeled off from the sapphire plate 22. If the thickness of the sapphire plate 22 is made several times thicker, the curvature becomes considerably smaller, and peeling of the semiconductor element 21 can be prevented. However, since sapphire does not have good thermal conductivity, a new problem arises in that semiconductor elements cannot be cooled sufficiently.
（発明が解決しようとする問題点）
以上述べた様に従来の超低温冷却用容器では、液体窒素
で冷却すると、素子接着部が湾曲し、半導体素子がサフ
ァイア板から剥離するという問題点があり、これを防ぐ
ためにサファイア板を厚くすると半導体素子が充分に冷
却されなくて、目的の高速化が達成できないという問題
が新らたに発生していた。(Problems to be Solved by the Invention) As mentioned above, in the conventional ultra-low temperature cooling container, when cooled with liquid nitrogen, the bonded part of the element curves and the semiconductor element peels off from the sapphire plate. In order to prevent this, if the sapphire plate was made thicker, the semiconductor element would not be cooled sufficiently, causing a new problem in that the desired speed increase could not be achieved.
本発明は、液体窒素で冷却しても半導体素子が剥離する
ことなく、信頼性良く、充分に半導体素子を冷却するこ
とができる超低温冷却用容器を提供することを目的とす
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a container for ultra-low temperature cooling that can reliably and sufficiently cool a semiconductor element without causing the semiconductor element to peel off even when cooled with liquid nitrogen.
［発明の構成］
（問題点を解決するための手段）
」−記目的を達成するために本発明による超低温冷却用
容器を以下に示す。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above objects, a container for ultra-low temperature cooling according to the present invention is shown below.
ガラス容器に溶着されたコバール基板に、例えば低膨張
のＦｅ−Ｎｉ合金系のＩＮＶＡＲ（３６％Ｎｉ）からな
る部品固定材°をロー付けする。部品固定材のＩＮＶＡ
Ｒ板に緩衝材としてＡ４２Ｎ板を銀ペースト等で接着し
ＡＩＮ板に半導体素子を接着する。A component fixing material made of, for example, INVAR (36% Ni), a low-expansion Fe-Ni alloy, is brazed to the Kovar substrate welded to the glass container. INVA of parts fixing material
An A42N plate is bonded to the R plate as a cushioning material using silver paste, etc., and a semiconductor element is bonded to the AIN plate.
（作用）
このような構造の超低温冷却用容器においては、素子接
着部に使われる材料の熱膨張係数の差を小さくし、熱膨
張係数の小さいＩＮＶＡＲ板を中心にしてその両側をＩ
ＮＶＡＲより熱膨張係数の大きいＡＡＮとコバールで
はさむことで、素子接着部の湾曲を防止している。また
、ＡＩＮはサファイアよりも熱伝導が良いので、半導体
素子は充分に冷却される。(Function) In an ultra-low temperature cooling container with such a structure, the difference in thermal expansion coefficients of the materials used for the element bonding parts is reduced, and both sides of the INVAR plate, which has a small thermal expansion coefficient, are
By sandwiching it between AAN, which has a larger coefficient of thermal expansion than NVAR, and Kovar, bending of the element bonding area is prevented. Furthermore, since AIN has better thermal conductivity than sapphire, the semiconductor element is sufficiently cooled.
（実施例）
本発明による超低温冷却用容器の一実施例を第１図を使
って説明する。第３図、第４図と同一部分は同一番号で
示されている。(Example) An example of a container for ultra-low temperature cooling according to the present invention will be described with reference to FIG. The same parts as in FIGS. 3 and 4 are designated by the same numbers.
第１図で半導体素子２１は、銀ペースト等で厚さ ０
、６ ｍｍのＡＰＮ板２に接着されている。Ａ４２Ｎ板
２はＩＮＶＡＲ板３に銀ペースト等で接着されている。In FIG. 1, the semiconductor element 21 is made of silver paste or the like to a thickness of 0.
, 6 mm APN board 2. The A42N board 2 is bonded to the INVAR board 3 with silver paste or the like.
ＩＮＶＡＲ板３は、コバール基板２４に例えは銀熱膨張
計数α −３，４Ｘ １０−６と良く一致していＳす
る。そしてＡｆｌＮ板２とコバール基板２４の間に熱膨
張係数カａ −１，２Ｘ １０ ’ノ１ＮＶＡＲ
板３ＩＮＶ。The INVAR plate 3 has a silver thermal expansion coefficient α −3,4×10 −6 that closely matches that of the Kovar substrate 24 . And between the AflN plate 2 and the Kovar substrate 24, the coefficient of thermal expansion is a -1,2X 10'
Board 3 INV.
がはさまれていて、ＡｆｌＮ板２と ＩＮＶＡＩ？板３
による応力と ＩＮＶＡＩ？板３とコバール基板２４に
よる応力とがうまく打ち消し合ってＡｐＮ板２． Ｉ
ＮＶＡＲ板３．コバール基板２４を合わせた素子接着部
の湾曲を防いでいる。上記の様にＡＰＮ板２゜ＩＮＶＡ
Ｒ板３．コバール基板２４の熱膨張係数の差が小さいの
で、ＡＱＮ板２の板厚も０ 、６ ｍと薄くても充分に
素子接着部の湾曲か防げる。更にＡ氾Ｎの熱伝導率はサ
ファイアの約２倍良いので冷却効率も向上する。is sandwiched between AflN board 2 and INVAI? Board 3
Stress due to INVAI? The stresses caused by the plate 3 and the Kovar substrate 24 cancel each other out, and the ApN plate 2. I
NVAR board 3. This prevents bending of the element bonding portion where the Kovar substrate 24 is joined. APN board 2゜INVA as above
R plate 3. Since the difference in the coefficient of thermal expansion of the Kovar substrate 24 is small, even if the thickness of the AQN plate 2 is as thin as 0.6 m, the bending of the element bonding portion can be sufficiently prevented. Furthermore, the thermal conductivity of A-flooded N is about twice as good as that of sapphire, so cooling efficiency is also improved.
第２図は本発明の他の実施例を示す。第２図では素子接
着部のみを示してあり、第１図と同一部分は同一番号で
示しである。 ＩＮＶＡＲ板１３はコバール基板２４と
銀ロー付けをするときの位置決めを容易にするために周
辺部が厚くなっている。このように ＩＮＶＡＲ板の形
状を変化させても本発明の効果はそこなわれない。FIG. 2 shows another embodiment of the invention. In FIG. 2, only the element bonding portion is shown, and the same parts as in FIG. 1 are designated by the same numbers. The INVAR plate 13 is thick at the periphery in order to facilitate positioning when performing silver brazing with the Kovar substrate 24. Even if the shape of the INVAR plate is changed in this way, the effects of the present invention are not impaired.
半導体素子はＳｉの高速素子に限らない。Ｇｅ。The semiconductor element is not limited to a high-speed Si element. Ge.
ＧａＡｓ、Ｇａｐ、Ｉｎｐ、ＩｎＳｂ、ＣｄＴｅ。GaAs, Gap, Inp, InSb, CdTe.
ＨｇＣｄＴｅ等の半導体材料の高速素子１発光素子、受
光素子、温度センサー等でもよい。また、容器の利質は
ガラスに限らず、金属等でもよい。The high-speed device 1 may be a light emitting device, a light receiving device, a temperature sensor, etc. made of a semiconductor material such as HgCdTe. Further, the material of the container is not limited to glass, but may also be made of metal or the like.
冷却容器内は真空に限らず、Ｈｅ、Ｎ２等のガスでもよ
い。更に冷却方法は液体窒素に限らず、液体ヘリウム、
液体酸素でもよ（、また、ミニクーラーと呼ばれる高圧
窒素ガスを使う方法でもよい。The inside of the cooling container is not limited to a vacuum, but may be a gas such as He or N2. Furthermore, the cooling method is not limited to liquid nitrogen, but also liquid helium,
You can use liquid oxygen (or you can use high-pressure nitrogen gas called a mini-cooler).
ＡｐＮ板上をメタライズして半導体素子と導入端子間の
配線のターミナルとすることもできる。部品固定材は
ＩＮＶＡＲに限らない。It is also possible to metalize the ApN board and use it as a wiring terminal between the semiconductor element and the lead-in terminal. Parts fixing material
Not limited to INVAR.
［発明の効果］
本発明による超低温冷却用容器は、素子接着部に使われ
る材料の組み合わせを変更して超低温冷却時の素子接着
部の湾曲を防いだので、素子の剥離がなくなった。[Effects of the Invention] In the ultra-low temperature cooling container according to the present invention, the combination of materials used for the device bonding portion is changed to prevent the device bonding portion from curving during ultra-low temperature cooling, so that peeling of the device is eliminated.
また、素子接着部の材料間の熱膨張係数の差を小さくし
たのでＡＩＮの板厚が薄くても充分に湾曲防止の効果か
あり、更にＡＩＮは熱伝導が良いので、半導体素子の冷
却効率の向上が可能になった。In addition, since the difference in thermal expansion coefficient between the materials of the element bonding part has been reduced, even if the AIN plate is thin, it is sufficiently effective in preventing curvature.Furthermore, since AIN has good thermal conductivity, cooling efficiency of semiconductor elements can be improved. improvement is possible.
第１図は本発明の一実施例の超低温冷却用容器を示す断
面図、第２図は本発明の他の実施例の一部分を示す断面
図、第３図は従来の超低温冷却用容器を示す断面図、第
４図は従来の超低温冷却用容器の問題点を示す断面図で
ある。
１．２１ 半導体素子、
２ Ａｆｌ Ｎ板、
３ 、 １３ １ＮＶＡＲ仮、
２４ コバール基板、
２５ ガラス容器、
２２ サファイア板、
２３ Ｃｕ板。FIG. 1 is a sectional view showing a container for ultra-low temperature cooling according to an embodiment of the present invention, FIG. 2 is a sectional view showing a part of another embodiment of the invention, and FIG. 3 is a sectional view showing a conventional container for ultra-low temperature cooling. FIG. 4 is a cross-sectional view showing problems with the conventional ultra-low temperature cooling container. 1.21 semiconductor element, 2 Afl N plate, 3, 13 1 NVAR temporary, 24 Kovar substrate, 25 glass container, 22 sapphire plate, 23 Cu plate.
Claims (1)
体素子を超低温に冷却するための容器において、該容器
の壁の該半導体素子を接着する部分がコバールであり、
該コバールの上に熱膨張係数が３．０×１０＾−＾６以
下のＦｅ−Ｎｉ系又はＦｅ−Ｎｉ−Ｃｏ系の低膨張合金
からなる部品固定材とＡｌＮからなる緩衝材を順次接着
したコバール−部品固定材−ＡｌＮの積層構造であり、
前記ＡｌＮ緩衝材の上に上記半導体素子を接着すること
を特徴とする超低温冷却用容器。In a container for adhering a semiconductor element to be used after being cooled to an ultra-low temperature, and for cooling the semiconductor element to an ultra-low temperature, a portion of the wall of the container to which the semiconductor element is adhered is made of Kovar,
A component fixing material made of a Fe-Ni or Fe-Ni-Co low expansion alloy with a coefficient of thermal expansion of 3.0 x 10^-^6 or less and a cushioning material made of AlN were successively adhered onto the Kovar. It has a laminated structure of Kovar - parts fixing material - AlN,
A container for ultra-low temperature cooling, characterized in that the semiconductor element is adhered onto the AlN buffer material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61192660A JPH0797615B2 (en) | 1986-08-20 | 1986-08-20 | Ultra low temperature cooling container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61192660A JPH0797615B2 (en) | 1986-08-20 | 1986-08-20 | Ultra low temperature cooling container |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6350046A true JPS6350046A (en) | 1988-03-02 |
| JPH0797615B2 JPH0797615B2 (en) | 1995-10-18 |
Family
ID=16294925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61192660A Expired - Lifetime JPH0797615B2 (en) | 1986-08-20 | 1986-08-20 | Ultra low temperature cooling container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0797615B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126830A (en) * | 1989-10-31 | 1992-06-30 | General Electric Company | Cryogenic semiconductor power devices |
| EP0757234A1 (en) * | 1995-08-02 | 1997-02-05 | Societe Francaise De Detecteurs, Infrarouges- Sofradir | Assembly of an infrared detector with thermal compensation |
-
1986
- 1986-08-20 JP JP61192660A patent/JPH0797615B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126830A (en) * | 1989-10-31 | 1992-06-30 | General Electric Company | Cryogenic semiconductor power devices |
| EP0757234A1 (en) * | 1995-08-02 | 1997-02-05 | Societe Francaise De Detecteurs, Infrarouges- Sofradir | Assembly of an infrared detector with thermal compensation |
| FR2737566A1 (en) * | 1995-08-02 | 1997-02-07 | Sofradir | METHOD FOR REALIZING THE ASSEMBLY OF AN ELECTROMAGNETIC WAVE DETECTION BLOCK, ESPECIALLY INFRARED, WITH A THERMAL CONDUCTIVE SUPPORT, AND ELECTROMAGNETIC WAVE DETECTOR USING THE SAME |
| US5834778A (en) * | 1995-08-02 | 1998-11-10 | Societe Francaise De Detecteurs Infrarouges-Sofradir | Method for assembling a detection unit for electromagnetic and in particular infrared waves with a thermally conducting substrate and an electromagnetic and in particular an infrared detector with which to implement this method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0797615B2 (en) | 1995-10-18 |
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