JPS6349416B2 - - Google Patents
Info
- Publication number
- JPS6349416B2 JPS6349416B2 JP3331883A JP3331883A JPS6349416B2 JP S6349416 B2 JPS6349416 B2 JP S6349416B2 JP 3331883 A JP3331883 A JP 3331883A JP 3331883 A JP3331883 A JP 3331883A JP S6349416 B2 JPS6349416 B2 JP S6349416B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- stereo
- pilot
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002131 composite material Substances 0.000 claims description 22
- 230000001360 synchronised effect Effects 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 18
- 238000001514 detection method Methods 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 description 17
- 230000035945 sensitivity Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/1646—Circuits adapted for the reception of stereophonic signals
- H04B1/1653—Detection of the presence of stereo signals and pilot signal regeneration
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
- H04H40/72—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Stereo-Broadcasting Methods (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、コンポジツト信号中に含まれるパイ
ロツト信号を除去する回路を備えたステレオ復調
回路に関する。特に、ステレオ信号を受信中であ
ることを表示するステレオ受信表示回路を有する
ステレオ復調回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stereo demodulation circuit including a circuit for removing a pilot signal contained in a composite signal. In particular, the present invention relates to a stereo demodulation circuit having a stereo reception display circuit that indicates that a stereo signal is being received.
ここに、「コンポジツト信号」とは、FMステ
レオ信号から復調され左右の和分信号と左右の差
分信号とパイロツト信号とを含む混成信号をい
う。 Here, the "composite signal" refers to a composite signal demodulated from an FM stereo signal and including a left and right sum signal, a left and right difference signal, and a pilot signal.
本発明は、コンポジツト信号とパイロツト除去
信号とを入力してコンポジツト信号からパイロツ
ト信号を除去する第一回路を含むステレオ復調回
路において、
この第一回路を差動演算回路で構成し、パイロ
ツト除去信号を発生する回路をこの差動演算回路
の負帰還回路として接続し、この負帰還回路の中
でステレオ受信表示信号を分岐することにより、
ステレオ受信表示の感度を変更するために回路
の利得を変更しても、負帰還回路が自動的に追従
して、パイロツト信号の抑圧に影響を与えないよ
うにしたものである。
The present invention provides a stereo demodulation circuit including a first circuit that inputs a composite signal and a pilot removed signal and removes the pilot signal from the composite signal. By connecting the generating circuit as a negative feedback circuit of this differential calculation circuit and branching the stereo reception display signal in this negative feedback circuit, the gain of the circuit can be changed in order to change the sensitivity of the stereo reception display. However, the negative feedback circuit automatically follows the signal, so that it does not affect the suppression of the pilot signal.
第１図は、従来例のステレオ受信表示回路を有
するパイロツト信号除去回路を示すブロツク構成
図である。
FIG. 1 is a block diagram showing a pilot signal removal circuit having a conventional stereo reception display circuit.
第１図において、符号１はコンポジツト信号の
入力端子、２はバツフア増幅器、３は前置増幅
器、４は同期検波回路、５はローパスフイルタ、
６は直流増幅器、７は復調回路、８は波形変換回
路である。この波形変換回路８にはパイロツト信
号を除去するための大容量のコンデンサC3が接
続される端子１４を備えている。符号９はステレ
オ受信表示ランプ駆動回路、１０はPLL（Phase
Locked Loop）回路、１１は加算回路、１２，
１３はステレオ信号の出力端子を示す。 In FIG. 1, reference numeral 1 is a composite signal input terminal, 2 is a buffer amplifier, 3 is a preamplifier, 4 is a synchronous detection circuit, 5 is a low-pass filter,
6 is a DC amplifier, 7 is a demodulation circuit, and 8 is a waveform conversion circuit. This waveform conversion circuit 8 is provided with a terminal 14 to which a large capacity capacitor C3 for removing the pilot signal is connected. Reference numeral 9 is a stereo reception display lamp drive circuit, and 10 is a PLL (Phase
Locked Loop) circuit, 11 is an addition circuit, 12,
13 indicates an output terminal for stereo signals.
入力端子１から入力されたコンポジツト信号
は、バツフア増幅器２を介して加算回路１１に印
加されるとともに、コンデンサC1によつて直流
的に遮断された後に前置増幅器３に印加される。
前置増幅器３に入力されたコンポジツト信号は、
PLL回路１０に入力されるとともに、同期検波
回路４、ローパスフイルタ５、直流増幅器６を順
に通る。PLL回路１０は、コンポジツト信号中
に含まれるパイロツト信号に同期した矩形波を発
生してこの矩形波を同期検波回路４に与え、これ
により、同期検波回路４はコンポジツト信号から
パイロツト信号を同期検波する。検波されたパイ
ロツト信号は、ローパスフイルタ５により直流成
分が抽出され、さらに直流増幅器６により直流電
流に変換される。この直流電流の大きさは、パイ
ロツト信号レベルに比例したものとなり、この直
流電流によつてステレオ表示ランプ駆動回路９が
作動され、ステレオ信号を受信したことを表示す
るランプが点灯される。 A composite signal inputted from an input terminal 1 is applied to an adder circuit 11 via a buffer amplifier 2, and is also applied to a preamplifier 3 after being DC-blocked by a capacitor C1 .
The composite signal input to the preamplifier 3 is
The signal is input to the PLL circuit 10 and passes through the synchronous detection circuit 4, the low-pass filter 5, and the DC amplifier 6 in this order. The PLL circuit 10 generates a rectangular wave synchronized with the pilot signal included in the composite signal and supplies this rectangular wave to the synchronous detection circuit 4, whereby the synchronous detection circuit 4 synchronously detects the pilot signal from the composite signal. . A DC component of the detected pilot signal is extracted by a low-pass filter 5, and further converted into a DC current by a DC amplifier 6. The magnitude of this DC current is proportional to the pilot signal level, and the stereo display lamp drive circuit 9 is operated by this DC current to light up a lamp indicating that a stereo signal has been received.
また、PLL回路１０は、パイロツト信号と位
相が約90゜異なる矩形波を発生し、これを波形変
換回路８に送出する。この矩形波は、波形変換回
路８により波形変換され、さらにコンデンサC2
により直流を遮断されて加算回路１１に印加され
る。これにより加算回路１１では、バツフア増幅
器２の出力ではコンポジツト信号からパイロツト
信号成分が除去される。パイロツト信号が除去さ
れた信号は、復調回路７を通り、Ｌ信号とＲ信号
とにそれぞれ分離されて出力端子１２，１３にそ
れぞれ出力される。 Further, the PLL circuit 10 generates a rectangular wave whose phase differs by about 90 degrees from the pilot signal, and sends this to the waveform conversion circuit 8. This rectangular wave is converted into a waveform by a waveform conversion circuit 8, and further connected to a capacitor C 2
The direct current is cut off and applied to the adding circuit 11. As a result, in the adder circuit 11, the pilot signal component is removed from the composite signal at the output of the buffer amplifier 2. The signal from which the pilot signal has been removed passes through the demodulation circuit 7 and is separated into an L signal and an R signal, which are output to output terminals 12 and 13, respectively.
第１図の従来例回路においては、コンポジツト
信号中に含まれるパイロツト信号レベルに対する
ステレオ受信表示ランプ駆動回路９の感度設定
は、直流増幅器６の出力直流電流の大きさにより
決まり、この直流電流値を変えるには、前置増幅
器３の利得、あるいは同期検波回路４から直流増
幅器６に至るパスの電圧−電流変換利得を変えな
ければならない。 In the conventional example circuit shown in FIG. 1, the sensitivity setting of the stereo reception display lamp drive circuit 9 to the pilot signal level included in the composite signal is determined by the magnitude of the output DC current of the DC amplifier 6, and this DC current value is determined by the magnitude of the output DC current of the DC amplifier 6. To change this, the gain of the preamplifier 3 or the voltage-current conversion gain of the path from the synchronous detection circuit 4 to the DC amplifier 6 must be changed.
ところがこれらの利得を変えると、加算回路１
１に入力されるパイロツト信号除去のための信号
のレベルが変化してしまい、加算回路１１の出力
からの適正なパイロツト信号の除去を行えなくな
る。また、前置増幅器３の出力はPLL回路１０
に入力され、この出力に基づいてキヤプチヤーレ
ンジおよびロツクレンジ等がこのPLL回路１０
において設定される。このため、ステレオ受信表
示の感度を変更するために前置増幅器３の利得等
を安易に変えることができず、ステレオ表示のた
めのステレオ表示ランプ駆動回路９の感度設定も
容易に行えない。さらに、本回路を半導体集積回
路により実現した場合は、ステレオ受信表示の感
度はある固有の感度に設定され、ステレオ受信表
示の感度設定には自由度がなくなる欠点がある。
さらに感度設定を可変できるようにするために
は、そのための特別な回路や端子を新たに設ける
必要が生じ、半導体集積回路装置の端子数が増え
ることになる。
However, when these gains are changed, adder circuit 1
The level of the signal for removing the pilot signal inputted to the adder circuit 11 changes, making it impossible to remove the pilot signal properly from the output of the adder circuit 11. In addition, the output of the preamplifier 3 is output from the PLL circuit 10.
The capture range, lock range, etc. are input to this PLL circuit 10 based on this output.
It is set in . For this reason, it is not possible to easily change the gain of the preamplifier 3 in order to change the sensitivity of stereo reception display, and it is also difficult to easily set the sensitivity of the stereo display lamp drive circuit 9 for stereo display. Furthermore, when this circuit is realized by a semiconductor integrated circuit, the sensitivity of the stereo reception display is set to a certain inherent sensitivity, and there is a drawback that there is no degree of freedom in setting the sensitivity of the stereo reception display.
Furthermore, in order to make the sensitivity setting variable, it becomes necessary to newly provide a special circuit and terminals for this purpose, which increases the number of terminals of the semiconductor integrated circuit device.
本発明はこれを改良するもので、ステレオ受信
表示の感度を変更するために、同期検波回路の出
力回路で利得を変更しても、パイロツト信号の抑
圧には影響を与えることがないステレオ信号の復
調回路を提供することを目的とする。 The present invention improves on this, and allows the stereo signal to be changed without affecting the suppression of the pilot signal even if the gain is changed in the output circuit of the synchronous detection circuit in order to change the sensitivity of the stereo reception display. The purpose is to provide a demodulation circuit.
本発明は、一方の入力端子にステレオコンポジ
ツト信号が与えられ、他方の入力端子にパイロツ
ト除去信号が与えられ、前記ステレオコンポジツ
ト信号中のパイロツト信号を前記パイロツト除去
信号により抑圧した出力信号を送出する第一回路
を差動演算回路により構成し、
前記パイロツト信号に等しい周波数の信号を基
準信号とする同期検波回路を含み前記第一回路に
与えるパイロツト除去信号を発生する第二回路を
前記差動演算回路の負帰還回路として接続し、
ステレオ受信表示回路への信号分岐回路はこの
負帰還回路内に設けたことを特徴とする。
In the present invention, a stereo composite signal is applied to one input terminal, a pilot removal signal is applied to the other input terminal, and an output signal is sent out in which the pilot signal in the stereo composite signal is suppressed by the pilot removal signal. A first circuit for generating a pilot signal to be applied to the first circuit is configured by a differential arithmetic circuit, and a second circuit for generating a pilot removal signal to be applied to the first circuit includes a synchronous detection circuit that uses a signal of a frequency equal to the pilot signal as a reference signal. It is characterized in that it is connected as a negative feedback circuit for the arithmetic circuit, and that a signal branch circuit to the stereo reception display circuit is provided within this negative feedback circuit.
パイロツト除去信号を発生する第二回路は第一
回路である差動演算回路の負帰還回路となるか
ら、出力信号に残留するパイロツト信号レベルが
最小になるように自動的に差動演算回路の二つの
入力レベルが追従する。ステレオ受信表示回路へ
の信号分岐をこの負帰還回路内に設けるので、ス
テレオ受信表示信号の感度を変更するために、同
期検波回路の出力回路で利得を変更しても、負帰
還増幅器として動作する差動演算回路が自動的に
これに追従して、パイロツト信号の抑圧に対する
影響はほとんど問題にならなくなる。
Since the second circuit that generates the pilot removal signal serves as a negative feedback circuit for the first circuit, the differential arithmetic circuit, it automatically controls the second circuit of the differential arithmetic circuit so that the pilot signal level remaining in the output signal is minimized. two input levels follow. Since the signal branch to the stereo reception display circuit is provided within this negative feedback circuit, it operates as a negative feedback amplifier even if the gain is changed in the output circuit of the synchronous detection circuit to change the sensitivity of the stereo reception display signal. The differential arithmetic circuit automatically follows this, and the influence on the suppression of the pilot signal becomes almost irrelevant.
以下、本発明に係る実施例を図面に基づいて説
明する。
Embodiments according to the present invention will be described below based on the drawings.
第２図は本発明実施例回路を示すブロツク構成
図である。 FIG. 2 is a block diagram showing a circuit according to an embodiment of the present invention.
第２図において、入力端子１５には19kHzのパ
イロツト信号を含むコンポジツト信号が入力さ
れ、このコンポジツト信号は、バツフア増幅器１
６を通つて差動演算回路２４の非反転入力端子
（＋）に印加される。この差動演算回路２４は第
一回路を構成し、この差動演算回路２４の反転入
力端子（−）には第二回路３０からのパイロツト
除去信号が印加されて、差動演算回路２４の出力
では、コンポジツト信号からパイロツト信号が除
去される。パイロツト信号が除去された差動演算
回路２４の出力は復調回路２１に入力され、ここ
で右チヤンネルと左チヤンネルのステレオ信号が
分離復調され、それぞれ出力端子２５，２６に出
力される。 In FIG. 2, a composite signal including a 19kHz pilot signal is input to the input terminal 15, and this composite signal is input to the buffer amplifier 1.
6 to the non-inverting input terminal (+) of the differential arithmetic circuit 24. The differential arithmetic circuit 24 constitutes a first circuit, and the pilot removal signal from the second circuit 30 is applied to the inverting input terminal (-) of the differential arithmetic circuit 24, and the output of the differential arithmetic circuit 24 is Then, the pilot signal is removed from the composite signal. The output of the differential arithmetic circuit 24 from which the pilot signal has been removed is input to the demodulation circuit 21, where the right channel and left channel stereo signals are separated and demodulated and output to output terminals 25 and 26, respectively.
第２図に破線で囲む回路３０は第二回路であ
る。この回路は、差動演算回路２４の出力信号に
残留するパイロツト信号を同期検波回路１７によ
り同期検波し、その出力をローパスフイルタ１
８、直流増幅器１９を介して波形変換回路２０に
導き、この波形変換回路２０により、端子２７に
接続されたコンデンサC4を充放電させ、そのコ
ンデンサC4の端子電圧をパイロツト除去信号と
して、差動演算回路２４の反転入力端子（−）に
導く。ここで、この第二回路３０が差動演算回路
２４にその負帰還回路となる極性で接続されたと
ころに特徴がある。 A circuit 30 surrounded by a broken line in FIG. 2 is a second circuit. This circuit uses a synchronous detection circuit 17 to synchronously detect the pilot signal remaining in the output signal of the differential arithmetic circuit 24, and the output is passed through a low-pass filter 1.
8. The waveform converter circuit 20 charges and discharges the capacitor C4 connected to the terminal 27, and uses the terminal voltage of the capacitor C4 as a pilot removal signal to output the difference. It leads to the inverting input terminal (-) of the dynamic arithmetic circuit 24. The feature here is that the second circuit 30 is connected to the differential arithmetic circuit 24 with a polarity that makes it a negative feedback circuit.
端子２７およびコンデンサC4は、パイロツト
信号除去用に従来から設けられている端子１４お
よびコンデンサC3（第１図参照）に相当する大容
量のコンデンサである。 Terminal 27 and capacitor C 4 are large capacitors corresponding to terminal 14 and capacitor C 3 (see FIG. 1) conventionally provided for pilot signal removal.
同期検波回路１７および波形変換回路２０は
PLL回路２３からの矩形波出力により作動され
る。PLL回路２３は、同期検波回路１７に対し
てはコンポジツト信号中に含まれるパイロツト信
号と同期した矩形波を発生し、また波形変換回路
２０に対してはパイロツト信号と位相が90゜異な
る矩形波を発生する。波形変換回路２０は、
PLL回路２３からの矩形波により直流増幅器１
９からの出力電流を断続させてコンデンサC4に
供給し、コンデンサC4を断続的に充放電させる。 The synchronous detection circuit 17 and the waveform conversion circuit 20 are
It is operated by the rectangular wave output from the PLL circuit 23. The PLL circuit 23 generates a rectangular wave synchronized with the pilot signal included in the composite signal to the synchronous detection circuit 17, and generates a rectangular wave whose phase is 90 degrees different from the pilot signal to the waveform conversion circuit 20. Occur. The waveform conversion circuit 20 is
The DC amplifier 1 is powered by the square wave from the PLL circuit 23.
The output current from 9 is intermittently supplied to capacitor C 4 to intermittently charge and discharge capacitor C 4 .
ステレオ受信表示ランプ駆動回路２２は、直流
増幅器１９の出力から分岐された信号で作動し、
ステレオ信号を受信したことを表示するランプを
点灯する回路である。ランプは特に図面に示して
ない。 The stereo reception display lamp drive circuit 22 operates with a signal branched from the output of the DC amplifier 19,
This circuit lights up a lamp to indicate that a stereo signal has been received. The lamp is not specifically shown in the drawing.
次に本実施例装置の動作を説明する。 Next, the operation of the device of this embodiment will be explained.
入力端子１５に入力されたコンポジツト信号
は、バツフア増幅器１６で増幅されて差動演算回
路２４の入力に与えられ、この回路２４の他方の
入力に与えられるパイロツト除去信号により、パ
イロツト信号を抑圧した信号が出力信号として送
出される。この出力信号は復調回路２１に入力し
て左右のチヤンネルのステレオ信号が復調され
る。 The composite signal input to the input terminal 15 is amplified by the buffer amplifier 16 and applied to the input of the differential arithmetic circuit 24, and a signal obtained by suppressing the pilot signal is generated by the pilot removal signal applied to the other input of this circuit 24. is sent out as an output signal. This output signal is input to a demodulation circuit 21, and stereo signals of left and right channels are demodulated.
第二回路３０では差動演算回路２４の出力のパ
イロツト信号残留成分は、同期検波回路１７で同
期検波されてローパスフイルタ１８を通つて直流
電圧に変換され、さらに直流増幅器１９を通つて
上記パイロツト信号の残留成分に比例した直流電
流に変換される。この直流電流は波形変換回路２
０に入力し、PLL回路２３からの19kHzの矩形波
により断続されてコンデンサC4に供給される。
この波形変換回路２０は上記直流電流を断とする
ときにはコンデンサC4を短絡するように構成さ
れている。したがつてコンデンサC4は19kHzの周
期で充放電を繰り返し、その端子電圧はコンポジ
ツト信号中のパイロツト信号に位相が同期した
19kHzの三角波となり、この三角波がパイロツト
除去信号として差動演算回路２４に与えられる。 In the second circuit 30, the residual component of the pilot signal output from the differential arithmetic circuit 24 is synchronously detected by the synchronous detection circuit 17, passed through the low-pass filter 18, converted into a DC voltage, and further passed through the DC amplifier 19 to convert the pilot signal to the pilot signal. is converted into a direct current proportional to the residual component of This DC current is transferred to the waveform conversion circuit 2.
0, is interrupted by a 19kHz rectangular wave from the PLL circuit 23, and is supplied to the capacitor C4 .
This waveform conversion circuit 20 is configured to short-circuit the capacitor C4 when the DC current is cut off. Therefore, capacitor C4 is repeatedly charged and discharged at a cycle of 19kHz, and its terminal voltage is synchronized in phase with the pilot signal in the composite signal.
This becomes a 19kHz triangular wave, and this triangular wave is applied to the differential arithmetic circuit 24 as a pilot removal signal.
ここで第二回路３０は差動演算回路２４の負帰
還回路となつているから、差動演算回路２４の増
幅利得にしたがつて、その正負入力のパイロツト
信号レベルがちようど等しくなるように自動的に
追従し、その出力信号のパイロツト信号は自動的
に最良に抑圧された状態となる。 Here, since the second circuit 30 serves as a negative feedback circuit for the differential arithmetic circuit 24, it automatically adjusts the pilot signal levels of its positive and negative inputs to become equal according to the amplification gain of the differential arithmetic circuit 24. The pilot signal of the output signal automatically becomes the best suppressed state.
ステレオ表示ランプ駆動回路２２の感度を変え
るには、直流増幅器１９の出力直流電流を変えれ
ばよい。これには例えば波形変換回路２０の変換
利得を変化させればよい。利得を変化させても、
同期検波回路１７から波形変換回路２０に至る回
路は差動演算回路２４の負帰還回路に組み込まれ
ており、上述のように差動演算回路２４の反転入
力端子に入力される端子２７の信号は差動演算回
路２４の出力のパイロツト信号残留成分が最小と
なるような値に常に自動調整される。 The sensitivity of the stereo display lamp drive circuit 22 can be changed by changing the output DC current of the DC amplifier 19. This can be done by changing the conversion gain of the waveform conversion circuit 20, for example. Even if you change the gain,
The circuit from the synchronous detection circuit 17 to the waveform conversion circuit 20 is incorporated into the negative feedback circuit of the differential arithmetic circuit 24, and as mentioned above, the signal at the terminal 27 input to the inverting input terminal of the differential arithmetic circuit 24 is It is always automatically adjusted to a value that minimizes the pilot signal residual component of the output of the differential arithmetic circuit 24.
一方この端子２７上の信号の大きさは、直流増
幅器１９の直流電流値とコンデンサC4の容量値
との関係で決まる。したがつてコンデンサC4の
容量値を変えることにより、等価的に波形変換回
路２０の利得を変え、直流増幅器１９の出力直流
電流を変えることができる。コンデンサC4の容
量値を変更すると差動演算回路２４は相応に見か
け上の利得が変化し、その出力パイロツト信号残
留成分が最小になるように追従する。すなわち差
動演算回路２４によるパイロツト信号除去動作に
支障を与えることなく、ステレオ受信表示感度を
任意に変えることができる。 On the other hand, the magnitude of the signal on this terminal 27 is determined by the relationship between the DC current value of the DC amplifier 19 and the capacitance value of the capacitor C4 . Therefore, by changing the capacitance value of the capacitor C 4 , the gain of the waveform conversion circuit 20 can be equivalently changed, and the output DC current of the DC amplifier 19 can be changed. When the capacitance value of the capacitor C4 is changed, the apparent gain of the differential calculation circuit 24 changes accordingly, and the residual component of the output pilot signal is followed so as to be minimized. That is, the stereo reception display sensitivity can be arbitrarily changed without interfering with the pilot signal removal operation by the differential arithmetic circuit 24.
なお、PLL回路２３に対しては、バツフア増
幅器１６の出力からパイロツト信号を入力させる
ので、波形変換回路２０の変換利得を変えてもそ
の動作に何らの支障も生じない。 Incidentally, since the pilot signal is inputted to the PLL circuit 23 from the output of the buffer amplifier 16, even if the conversion gain of the waveform conversion circuit 20 is changed, no problem occurs in its operation.
以上説明したように、本発明によれば、パイロ
ツト除去信号を発生する第二回路は、差動演算回
路の負帰還回路となつていて、しかもステレオ受
信表示信号はこの第二回路の負帰還回路内で分岐
されるから、この負帰還回路の利得を変更すると
ステレオ受信表示信号の感度が変更され、この感
度を変更しても、パイロツト信号の抑圧にはほと
んど影響を与えることがない回路が得られる。実
用的には、ステレオ受信表示信号の感度を変更す
るには、外付けのコンデンサの容量を変更するこ
とにより行うことができるから、このステレオ信
号復調回路を集積回路により実現する場合にも、
ステレオ受信表示信号の感度を変更するための回
路や端子を別に設ける必要はない。
As explained above, according to the present invention, the second circuit that generates the pilot removal signal is a negative feedback circuit of the differential arithmetic circuit, and the stereo reception display signal is transmitted through the negative feedback circuit of the second circuit. Therefore, changing the gain of this negative feedback circuit changes the sensitivity of the stereo reception display signal, and even if you change this sensitivity, you can create a circuit that has almost no effect on suppressing the pilot signal. It will be done. Practically speaking, the sensitivity of the stereo reception display signal can be changed by changing the capacitance of an external capacitor, so even if this stereo signal demodulation circuit is implemented using an integrated circuit,
There is no need to provide a separate circuit or terminal for changing the sensitivity of the stereo reception display signal.
第１図は従来例のステレオ復調回路を示すブロ
ツク構成図。第２図は本発明実施例のステレオ復
調回路を示すブロツク構成図。
２，１６……バツフア増幅器、４，１７……同
期検波回路、５，１８……ローパスフイルタ、
６，１９……直流増幅器、７，２１……復調回
路、８，２０……波形変換回路、９，２２……ス
テレオ表示ランプ駆動回路、１０，２３……
PLL回路、１１……加算回路、２４……差動演
算回路（第一回路）、３０……第二回路。
FIG. 1 is a block diagram showing a conventional stereo demodulation circuit. FIG. 2 is a block diagram showing a stereo demodulation circuit according to an embodiment of the present invention. 2, 16... Buffer amplifier, 4, 17... Synchronous detection circuit, 5, 18... Low pass filter,
6, 19... DC amplifier, 7, 21... Demodulation circuit, 8, 20... Waveform conversion circuit, 9, 22... Stereo display lamp drive circuit, 10, 23...
PLL circuit, 11... Addition circuit, 24... Differential calculation circuit (first circuit), 30... Second circuit.
Claims (1)
が与えられ、他方の入力端子にパイロツト除去信
号が与えられ、前記ステレオコンポジツト信号中
のパイロツト信号を前記パイロツト除去信号によ
り抑圧した出力信号を送出する第一回路２４と、 前記パイロツト信号に等しい周波数の信号を基
準信号とする同期検波回路１７を含み前記第一回
路の入力に与えるパイロツト除去信号を発生する
第二回路３０と、 ステレオ信号を受信していることを表示するス
テレオ受信表示回路２２と を備えたステレオ信号復調回路において、 前記第一回路は差動演算回路２４であり、 前記第二回路３０の入力には前記差動演算回路
の出力信号が接続され、 前記第二回路３０には、前記同期検波回路１７
の出力信号を増幅する直流増幅器１９と、この直
流増幅器の出力レベルにしたがつて前記パイロツ
ト信号に等しい周波数の信号を基準信号として前
記パイロツト除去信号を発生する波形変換回路２
０とを含み、かつこのパイロツト除去信号が接続
される前記第一回路の入力は前記差動演算回路の
差動入力の一方であり、この第二回路の前記差動
演算回路の差動入力に対する接続位相はこの第二
回路が前記差動演算回路に対して負帰還回路とな
る極性であり、 前記ステレオ受信表示回路への信号分岐回路は
前記第二回路に含まれる直流増幅器の出力信号路
に設けられた ことを特徴とするステレオ受信表示回路を有する
ステレオ復調回路。[Claims] 1. An output in which a stereo composite signal is applied to one input terminal, a pilot removal signal is applied to the other input terminal, and the pilot signal in the stereo composite signal is suppressed by the pilot removal signal. a first circuit 24 that sends out a signal; a second circuit 30 that includes a synchronous detection circuit 17 that uses a signal with a frequency equal to the pilot signal as a reference signal and generates a pilot removal signal to be applied to the input of the first circuit; In the stereo signal demodulation circuit including a stereo reception display circuit 22 that indicates that a signal is being received, the first circuit is a differential arithmetic circuit 24, and the input of the second circuit 30 is the differential arithmetic circuit 24. The output signal of the arithmetic circuit is connected to the second circuit 30, and the synchronous detection circuit 17
a DC amplifier 19 for amplifying the output signal of the DC amplifier; and a waveform conversion circuit 2 for generating the pilot removal signal using a signal of a frequency equal to the pilot signal as a reference signal according to the output level of the DC amplifier.
0, and the input of the first circuit to which this pilot removal signal is connected is one of the differential inputs of the differential arithmetic circuit, and the input of the second circuit to the differential input of the differential arithmetic circuit is The connection phase is such that this second circuit serves as a negative feedback circuit for the differential arithmetic circuit, and the signal branch circuit to the stereo reception display circuit is connected to the output signal path of the DC amplifier included in the second circuit. A stereo demodulation circuit having a stereo reception display circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331883A JPS59158635A (en) | 1983-02-28 | 1983-02-28 | Stereo demodulation circuit having stereo reception display circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331883A JPS59158635A (en) | 1983-02-28 | 1983-02-28 | Stereo demodulation circuit having stereo reception display circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59158635A JPS59158635A (en) | 1984-09-08 |
| JPS6349416B2 true JPS6349416B2 (en) | 1988-10-04 |
Family
ID=12383206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3331883A Granted JPS59158635A (en) | 1983-02-28 | 1983-02-28 | Stereo demodulation circuit having stereo reception display circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59158635A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0389346U (en) * | 1989-12-27 | 1991-09-11 |
-
1983
- 1983-02-28 JP JP3331883A patent/JPS59158635A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0389346U (en) * | 1989-12-27 | 1991-09-11 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59158635A (en) | 1984-09-08 |
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