JPS6348893A - Lead terminal soldering - Google Patents
Lead terminal solderingInfo
- Publication number
- JPS6348893A JPS6348893A JP19342986A JP19342986A JPS6348893A JP S6348893 A JPS6348893 A JP S6348893A JP 19342986 A JP19342986 A JP 19342986A JP 19342986 A JP19342986 A JP 19342986A JP S6348893 A JPS6348893 A JP S6348893A
- Authority
- JP
- Japan
- Prior art keywords
- soldering
- printed wiring
- wiring board
- solder
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 title claims description 39
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 18
- 239000006071 cream Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
本発明は、プリント配線板に対する電子部品のリード端
子のはんだ付けにおいて、はんだクリーム・予備はんだ
等のはんだ付け+オ料層を、各はんだ付け面の一部領域
にのみ形成してはんだ付けすることにより、余分なはん
だの流出によるリード端子間の短絡を防止したものであ
る。[Detailed Description of the Invention] [Summary] In the soldering of lead terminals of electronic components to a printed wiring board, the present invention applies soldering such as solder cream or pre-solder + solder layer to a part of each soldering surface. By forming and soldering only in the area, short circuits between lead terminals due to excess solder flowing out can be prevented.
本発明は、プリント配線板に対する電子部品のリード端
子のはんだ付け方法、とくに予備はんだあるいははんだ
クリームを(吏用しておこなうリード端子のはんだ付け
方法に関するものである。The present invention relates to a method for soldering lead terminals of electronic components to a printed wiring board, and particularly to a method for soldering lead terminals using preliminary solder or solder cream.
プリント配線板に対する電子部品の取りつけには、古く
から、浸l責はんだ付け(熔融したはんだ槽に接合面を
浸してはんだ付けする方法)、リフローはんだ付け(再
溶融法:予備はんだまたはめっき等によって接合面に予
め作っておいたはんだ層を熱風等によって熔融させては
んだ付けする方法)、はんだクリーム印刷法(粉末状の
はんだとフラックスとを練り合わせてクリーム状にした
ものを接合面に予め印刷しておき熱風等によって熔融さ
せてはんだ付けする方法)等によるはんだ付けが広く用
いられている。For attaching electronic components to printed wiring boards, immersion soldering (a method in which the joint surface is immersed in a bath of molten solder for soldering), reflow soldering (remelting method: pre-soldering or plating, etc.) have been used for a long time. Solder cream printing method (a method in which a solder layer prepared in advance on the joint surface is melted using hot air, etc.), a solder cream printing method (a method in which a cream made by mixing powdered solder and flux is printed on the joint surface in advance) Soldering methods such as a method of melting and soldering using hot air or the like are widely used.
一方、賃1債回路・コネクタ等の電子部品におけるリー
ド端子の増加やプリント配線板の高密度実装化に伴って
、電子部品のリード端子の間隔は非字に狭くなってきて
いる。On the other hand, with the increase in the number of lead terminals in electronic components such as circuits and connectors and the high-density mounting of printed wiring boards, the spacing between the lead terminals of electronic components has become extremely narrow.
このため、プリント配線板に対する電子部品のリード端
子のはんだ付けに際しては、余分なはんだによるリード
端子間の短絡が生しないように。For this reason, when soldering the lead terminals of electronic components to a printed wiring board, be careful not to cause a short circuit between the lead terminals due to excess solder.
十分な性急を配る必要がある。It is necessary to distribute enough haste.
〔従来の技1・Fr)
第4図((a)正面図、(b)断面図)は従来例の説明
図で、3は電子部品、 31は電子部品3のリート端子
、4はプリント配線板、41はリード線端子31 (l
ul+のはんだ付け面に対応して設けられるプリント配
線板4側のはんだ付り而(パッドまたうよランドともい
う)、また5′ははんだクリームを表している。[Conventional technique 1/Fr] Figure 4 ((a) front view, (b) sectional view) is an explanatory diagram of a conventional example, where 3 is an electronic component, 31 is a lead terminal of the electronic component 3, and 4 is a printed wiring. board, 41 is the lead wire terminal 31 (l
The solder area (also referred to as a pad land) on the printed wiring board 4 side provided corresponding to the soldering surface of ul+, and 5' represent solder cream.
すなわち、従来例では、プリント配線板4上の各はんだ
付け面41の全面にはんだクリーム5′を印刷によって
塗布し、その上に電子部品3のリード端子31を押し当
てた状態で熱風によって加メ;(シすることにより、は
んだクリーム5′中のはんだを熔融させて接合していた
。That is, in the conventional example, solder cream 5' is applied by printing to the entire surface of each soldering surface 41 on printed wiring board 4, and solder cream 5' is applied with hot air while the lead terminals 31 of electronic component 3 are pressed onto the solder cream 5'. (By doing so, the solder in the solder cream 5' was melted and the joint was made.
上述の従来例では、電子:)3品3のリード・端子31
の間隔が狭いものにおいては、余分なはんだが形成する
はんだブリッジによって、隣接するはんだ付け面41あ
るいはリード端子31の間が短絡され。In the conventional example described above, electronic:) 3 products 3 leads/terminals 31
In the case where the distance between the soldering surfaces 41 and the lead terminals 31 is narrow, a solder bridge formed by the excess solder causes a short circuit between adjacent soldering surfaces 41 or lead terminals 31.
製品不良を発生ずるという問題点があった。There was a problem that product defects occurred.
すなわち本発明の目的は、はんだブリッジの発生を防止
することにある。That is, an object of the present invention is to prevent the occurrence of solder bridges.
本発明によるリード端子のはんだ付け方法は。 A method for soldering lead terminals according to the present invention.
第1図の原理図に示すように。As shown in the principle diagram in Figure 1.
電子部品のリード端子の各はんだ付け面または対応する
プリント配線板上の各はんだ付け面の。Each soldering surface of the lead terminal of electronic components or each soldering surface on the corresponding printed wiring board.
少、り【くとも一方の各はんだ付け面の各々の一部領域
にのみはんだ付け材料層を形成する材料層形成工程1と
。A material layer forming step 1 in which a soldering material layer is formed only on a partial area of each soldering surface on at least one side.
前記少なくとも一方にはんだ付け材料層を形成されたプ
リント配線板とリード端子とを押し当てた状態で加熱す
る加熱工程2とによって、プリント配線板とリード端子
とを接合するものである。The printed wiring board and the lead terminal are bonded by a heating step 2 of heating the printed wiring board, on which at least one of the soldering material layers is formed, and the lead terminal while being pressed against each other.
第2図((a)正面図・(bl断面図)に示すように。 As shown in FIG. 2 ((a) front view/(bl sectional view)).
リード線端子31のはんだ付け而とプリント配線板4上
のはんだ付け面41とによって挾まれる領域の全域では
なく、一部領域にのみはんだ+オ料屓5を形成すること
により、余分なはんだの流出によるはんだブリッジの発
生を防止するごとができる。By forming the solder + solder material 5 only in a part of the area sandwiched between the soldering area of the lead wire terminal 31 and the soldering surface 41 on the printed wiring board 4 instead of the entire area, excess solder can be removed. It is possible to prevent the occurrence of solder bridges due to the outflow of solder.
本発明の要旨を第3図に示す断面図によって具体的に説
明する。The gist of the present invention will be specifically explained with reference to the sectional view shown in FIG.
プリント配線板4に接続される電子部品はコネクタ3′
であり、リード端子31′ ハ2列に設けられており、
これらをプリント配線板4の両面からはんだ付けするよ
うに構成したものである。The electronic component connected to the printed wiring board 4 is the connector 3'.
The lead terminals 31' are provided in two rows,
These are configured to be soldered to both sides of the printed wiring board 4.
プリント配線板4側の各はんだイ(jけ而41に対する
リード端子31′ の当て付けは、プリント配線板4の
面に沿って、これを2列に並んでいるリード端子31′
の間に挿仕込む形でおこなう。To attach the lead terminals 31' to each solder pin 41 on the printed wiring board 4 side, connect the lead terminals 31' arranged in two rows along the surface of the printed wiring board 4.
Do this by inserting it in between.
このため、各リード端子31′ の先端部は、プリント
配線板4の面に対し外側に曲げている。For this reason, the tip of each lead terminal 31' is bent outward with respect to the surface of the printed wiring board 4.
また、はんだクリーム5′は、各はんだ付け面41上の
前記挿入の際にリード端子31′ の先端部によって押
しのけられない様な場所にのみ、印刷によって形成して
いる。Further, the solder cream 5' is formed by printing only at a location on each soldering surface 41 where it will not be pushed away by the tip of the lead terminal 31' during the insertion.
0.1mmの間隔で配列される長Jさ約5mm−幅約1
mmのり一ト端子31′ を、同じ幅と間隔でプリント
配線板4上に配列されるはんだ付け面、11に対し。Length J approximately 5 mm - Width approximately 1, arranged at intervals of 0.1 mm
mm glued terminals 31' to the soldering surface 11 arranged on the printed wiring board 4 with the same width and spacing.
上記の方法によってはんだ付けした結果、従来例に比べ
てはんだブリッジの発生を大幅に減少することができた
。As a result of soldering using the above method, it was possible to significantly reduce the occurrence of solder bridges compared to the conventional example.
以上説明したように1本発明によるリード端子のはんだ
付け方法によって、はんだ付け不良による製品不良の発
生を防止でき、コストダウンの効果かイブられた。As explained above, the lead terminal soldering method according to the present invention can prevent product defects due to poor soldering, and has the effect of reducing costs.
第1図は本発明の原理図。
第2図(al・(b)は作用の説明図。
第3図は実施例の説明図。
第4図fa)・(b)は従来例の説明図である。
図中。
lは材料層形成工程、 2は加熱工程。
3は電子部品、31と31′ はり一ト端子。
4はプリント配線板5 5ははんだ材料層25′はばん
だクリームを表す。FIG. 1 is a diagram showing the principle of the present invention. Fig. 2(al) and (b) are explanatory diagrams of the action. Fig. 3 are explanatory diagrams of the embodiment. Fig. 4 fa) and (b) are explanatory diagrams of the conventional example. In the figure. 1 is a material layer forming process, and 2 is a heating process. 3 is an electronic component, 31 and 31' are beam terminals. 4 represents a printed wiring board 5; 5 represents a solder material layer 25'; a solder cream;
Claims (2)
はんだ付け方法であって、 前記リード端子の各はんだ付け面または対応するプリン
ト配線板上の各はんだ付け面の少なくとも一方の各はん
だ付け面の各々の一部領域にのみはんだ付け材料層を形
成する材料層形成工程(1)と、 前記少なくとも一方にはんだ付け材料層を形成されたプ
リント配線板とリード端子とを押し当てた状態で加熱す
る加熱工程(2)とによってプリント配線板とリード端
子とを接合することを特徴とするリード端子のはんだ付
け方法。(1) A method for soldering lead terminals of electronic components to a printed wiring board, the method comprising: each soldering surface of the lead terminal or at least one of each soldering surface on the corresponding printed wiring board; a material layer forming step (1) of forming a soldering material layer only in a partial region of the printed wiring board and the lead terminal, the printed wiring board having the soldering material layer formed on at least one side thereof pressed against each other; A method for soldering lead terminals, which comprises joining a printed wiring board and lead terminals by step (2).
よって形成するものであることを特徴とする特許請求の
範囲第(1)項記載のリード端子のはんだ付け方法。(2) The method for soldering lead terminals according to claim (1), wherein the soldering material layer is formed by printing solder cream.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19342986A JPS6348893A (en) | 1986-08-19 | 1986-08-19 | Lead terminal soldering |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19342986A JPS6348893A (en) | 1986-08-19 | 1986-08-19 | Lead terminal soldering |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6348893A true JPS6348893A (en) | 1988-03-01 |
Family
ID=16307827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19342986A Pending JPS6348893A (en) | 1986-08-19 | 1986-08-19 | Lead terminal soldering |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6348893A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980737A (en) * | 1988-09-30 | 1990-12-25 | Kabushiki Kaisha Toshiba | Luminance signal and chrominance signal separating circuit |
-
1986
- 1986-08-19 JP JP19342986A patent/JPS6348893A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980737A (en) * | 1988-09-30 | 1990-12-25 | Kabushiki Kaisha Toshiba | Luminance signal and chrominance signal separating circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS63202989A (en) | Soldering | |
JPH01319993A (en) | Connecting method for printed circuit board | |
JPS6348893A (en) | Lead terminal soldering | |
JPH0536871U (en) | Flexible board for circuit connection | |
JP2912308B2 (en) | Soldering structure for surface mount components | |
JPH0846343A (en) | Method of soldering lead terminal and screen used for the method | |
JPH05129753A (en) | Discrete component and printed board mounting method thereof | |
JPS625690A (en) | Soldering of electronic component | |
JPS61263191A (en) | Mounting of electronic component | |
JPS61115343A (en) | Semiconductor integrated circuit | |
JPS63155689A (en) | Method of solder-coating of printed board | |
JP3223592B2 (en) | Method of forming bump electrode on substrate | |
JPS63127593A (en) | Printed wiring board | |
JPS6352795B2 (en) | ||
JPH02301725A (en) | Soldered terminal | |
JPH01143164A (en) | Printed wiring board for surface mount | |
JPS6023998Y2 (en) | Heating crimp | |
JPS63299855A (en) | Soldering method | |
JPH04167496A (en) | Soldering method of printed-wiring board | |
JPS63169096A (en) | Mounting structure of surface mount component | |
JPS63263796A (en) | Method of attaching chip component | |
JPS59222994A (en) | Method of mounting electronic part | |
JPS6147697A (en) | Method of soldering electronic part | |
JPH0718475U (en) | Printed wiring board | |
JPH09283900A (en) | Mounting method of substrate and electronic parts |