JPS59222994A - Method of mounting electronic part - Google Patents

Method of mounting electronic part

Info

Publication number
JPS59222994A
JPS59222994A JP9893283A JP9893283A JPS59222994A JP S59222994 A JPS59222994 A JP S59222994A JP 9893283 A JP9893283 A JP 9893283A JP 9893283 A JP9893283 A JP 9893283A JP S59222994 A JPS59222994 A JP S59222994A
Authority
JP
Japan
Prior art keywords
solder
soldering
adhesive
melting point
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9893283A
Other languages
Japanese (ja)
Inventor
後藤 基之
徳田 龍馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9893283A priority Critical patent/JPS59222994A/en
Publication of JPS59222994A publication Critical patent/JPS59222994A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、両面印刷配線板にフラントパソケージIC
,チップ部品などの電子部品をリフ口半田付けする実装
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] This invention provides a flat path cage IC on a double-sided printed wiring board.
, relates to a mounting method for re-opening soldering of electronic components such as chip components.

〔従来技術〕[Prior art]

従来のこの種の電子部品の実装方法として、第1図ない
し第3図に示すものがあった。第1,2図において、l
は両面印刷配線板、2はこの両面印刷配線板1の表面に
接着剤3により仮固定されたあと、リフ口半田付けされ
たフラットパッケージIC14はチップ部品、5はディ
スクリート部品であり、6は両面印刷配線板1の裏面に
接着剤3により仮固定されてフロー半田付げされたチッ
プ部品、8は半田である。
2. Description of the Related Art Conventional methods for mounting electronic components of this type include those shown in FIGS. 1 to 3. In Figures 1 and 2, l
2 is a double-sided printed wiring board, 2 is a flat package IC 14 temporarily fixed to the surface of this double-sided printed wiring board 1 with an adhesive 3 and then soldered at the refill opening, is a chip component, 5 is a discrete component, and 6 is a double-sided printed wiring board. A chip component 8 is solder which is temporarily fixed to the back surface of the printed wiring board 1 with an adhesive 3 and flow soldered.

また第3図において、7は接着剤なしでリフ口半田付け
されたチップ部品である。
Further, in FIG. 3, numeral 7 indicates a chip component soldered to the rift opening without adhesive.

従来、両面印刷配線板1にフラットパッケージIC2を
リフ口半田付けする場合、搭載部品の種類により第1,
2図に示すようなリフ口・フロー併用方式と、第3図の
ような両面リフ口方式とがある。第1,2図に示す方式
では、裏面のフロー半田熱により先にリフ口半田付けし
た表面側のフラットパッケージIC2の半田8が再熔解
し、該IC2が位置ズレを起こさないように接着剤3に
て固定するようにしていた。
Conventionally, when soldering a flat package IC 2 to a double-sided printed wiring board 1, the first
There are two types: a combined ref-port and flow method as shown in FIG. 2, and a double-sided ref-port method as shown in FIG. In the method shown in FIGS. 1 and 2, the solder 8 of the flat package IC 2 on the front side that has been previously soldered at the rift opening is remelted by the flow soldering heat on the back side, and the adhesive 3 is applied to prevent the IC 2 from shifting its position. I tried to fix it with.

また第3図に示す方式は裏面にフラットパッケージIC
2を実装する場合の方式で、この場合も表面のフランI
−I C7やチップ部品4のリフ口半田熱により、先に
リフ口半田付けした裏面側のフラットパッケージIC2
の半田8の再熔解による位置ズレや脱落の防止のために
、接着剤3にて固定するようにしていた。
In addition, the method shown in Figure 3 has a flat package IC on the back side.
2, and in this case also the surface flange I
- The flat package IC 2 on the back side to which the rift opening was previously soldered due to the rift opening soldering heat of I C7 and chip component 4.
In order to prevent the solder 8 from shifting or falling off due to re-melting, the adhesive 3 is used to fix the solder 8.

従来のフラットパッケージICの実装方法では以上のよ
うに仮固定のための接着剤を使用しているので、接着剤
の塗布量や塗布位置のバラツキにより接着剤がパターン
に付着して半田付不良が発生したり、あるいは塗布量過
多によってフラットパッケージIGのリード端子が浮き
上がって導通不良が発生するなど、接続信頼性の面で問
題があった。
Conventional flat package IC mounting methods use adhesive for temporary fixing as described above, so variations in the amount and position of the adhesive applied can cause the adhesive to adhere to the pattern, resulting in poor soldering. There were problems in terms of connection reliability, such as the lead terminals of the flat package IG being lifted up due to excessive amount of coating, resulting in poor continuity.

〔発明の概要〕[Summary of the invention]

この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、表面及び裏面の半田付けにおの
おの融解点(融点)の異なる半田材料を使用することに
より、接着剤を不要とすることができる電子部品実装方
法を提供することを目的としている。
This invention was made to eliminate the drawbacks of the conventional products as described above, and eliminates the need for adhesives by using solder materials with different melting points for soldering on the front and back surfaces. The purpose of the present invention is to provide a method for mounting electronic components that can be used to mount electronic components.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第4図は本発明の一実施例による電子部品実装方法を示
す。本実施例の実装方法はりフロ・フロー併用方式に適
用した場合で、表面のディップ又はフロー半田付けの融
点(通常183℃前後)より更に高い融点の高温半田9
によって、両面印刷回路板1の表面にフラットパッケー
ジIC2のリフロ半田付けを行なうものである。
FIG. 4 shows an electronic component mounting method according to an embodiment of the present invention. When the mounting method of this embodiment is applied to a combination of beam and flow soldering, high-temperature solder 9 with a melting point higher than that of surface dip or flow soldering (usually around 183°C)
Accordingly, the flat package IC 2 is reflow soldered onto the surface of the double-sided printed circuit board 1.

即ち、表面のフラットパッケージIC2、チップ部品4
をあらかじめ高温半田である高い融点221”Cの半田
クリーム9を用いてリフロ半田付けする。次に、裏面の
ディスクリート部品5及びチップ部品6のディップ又は
フロー半田付けを、表面より融点の低い半田8 (例え
ば、通常の融点183℃)を用いて行なう。このように
すれば、表面の高温半田9は融点が高いために裏面側に
おける半田付は時に融解せず、従ってフラットパッケー
ジIC2やチップ部品4ば位置ズレを起こさないので、
表面側における仮固定用の接着剤は不要である。
That is, the flat package IC 2 on the surface, the chip component 4
are reflow soldered in advance using solder cream 9 with a high melting point of 221"C, which is a high-temperature solder. Next, dip or flow soldering of the discrete components 5 and chip components 6 on the back side is performed using solder cream 9 with a melting point lower than that on the front surface. (for example, a normal melting point of 183° C.). In this way, since the high-temperature solder 9 on the front surface has a high melting point, the solder on the back surface sometimes does not melt, and therefore the flat package IC 2 or the chip component 4 Since it does not cause misalignment,
Adhesive for temporary fixation on the surface side is not required.

以上のような本実施例の実装方法では、仮固定のための
接着剤を不要とすることができるので、接着剤の塗布量
や塗布位置のバラツキに起因する半田付不良や導通不良
の問題は発生せず、接続信頼性を向上できる。また資材
コストや組立加工コストも低減できる。
The mounting method of this embodiment as described above eliminates the need for adhesive for temporary fixing, thereby eliminating the problems of poor soldering and poor conductivity caused by variations in the amount and position of adhesive applied. This does not occur and connection reliability can be improved. Additionally, material costs and assembly processing costs can be reduced.

また第5図は本発明の他の実施例方法を示す。Further, FIG. 5 shows another embodiment of the method of the present invention.

この方法は表、裏面共にリフロ半田付は実装する場合で
、裏面のフラットパッケージIC2のリフロ用半田クリ
ーム8の融点より低い低温半田10を用いて、表面にフ
ラットIC7やチップ部品4のリフロ半田付けを行なう
ものである。
This method is for reflow soldering on both the front and back sides, and uses low temperature solder 10 lower than the melting point of the reflow solder cream 8 of the flat package IC 2 on the back side to reflow solder the flat IC 7 and chip components 4 on the front side. This is what we do.

即ち、耐熱性のないフラットIC7を両面リフロ半田付
けにて実装する場合、先に裏面にフラ・ノドパッケージ
IC2のリフロ半田付けを行ない、次に表面に融点の更
に低い低温半田10(例えば融点162℃)を用いてフ
ラットIC7,チップ部品4のリフロ半田付けを行なう
。このようにすれば、裏面の半田8は表面の半田10よ
り融点が高いために融解せず、従ってフラットパッケー
ジIC2は位置ズレや剥離、脱落を起こさないので、裏
面側における仮固定用の接着剤は不要である。
That is, when mounting a non-heat resistant flat IC 7 by double-sided reflow soldering, first perform reflow soldering of the flat-nod package IC 2 on the back side, and then apply low-temperature solder 10 with a lower melting point (for example, melting point 162) on the front surface. ℃) to reflow solder the flat IC 7 and chip components 4. In this way, the solder 8 on the back side has a higher melting point than the solder 10 on the front side, so it will not melt, and the flat package IC 2 will not be misaligned, peeled off, or fall off. is not necessary.

なお、上記実施例では半田クリーム(ソルダペースト)
にょろりフロ半田付けの場合について説明したが、半田
クリームの代わりに導電接着剤などの他の導電性接合物
を用いてもよく、上記実施例と同様の効果を奏する。
In addition, in the above example, solder cream (solder paste)
Although the case of Nyororiflow soldering has been described, other conductive bonding materials such as conductive adhesive may be used instead of solder cream, and the same effects as in the above embodiments can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、表、裏面に融点の異
なる半田を用いるようにしたので、仮固定用の接着剤を
不要とでき、その結果電子部品の半田付接続信頼性が向
上し、又資材コストや組立加工コストも低減できる効果
がある。
As described above, according to the present invention, since solder with different melting points is used on the front and back surfaces, it is possible to eliminate the need for adhesive for temporary fixing, and as a result, the solder connection reliability of electronic components is improved. Also, it has the effect of reducing material costs and assembly processing costs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のりフロ・フロー半田付は実装方法を示す
平面図、第2図は第1図の断面側面図、第3図は従来の
両面リフロ半田付は実装方法を示す断面側面図、第4図
は本発明の一実施例による電子部品実装方法を示す断面
側面図、第5図は本発明の他の実施例による電子部品実
装方法を示す断面側面図である。 代理人  大 岩 増 雄 第1図 第3図 第4図 f1コ5図 手続補正書(1発) 1□8オ。5龜121氾8 特許庁長官殿 1、事件の表示   特願昭 58−98932号2、
発明の名称 電子部品実装方法 3、補正をする者 代表者片山仁へ部 4、代理人 5、補正の対象 明細書の発明の詳細な説明の欄 6、補正の内容 fl)  明細書第4頁第3行の1表面の」を「裏面の
」に訂正する。 以   上
Fig. 1 is a plan view showing the mounting method for conventional reflow/flow soldering, Fig. 2 is a cross-sectional side view of Fig. 1, and Fig. 3 is a cross-sectional side view showing the mounting method for conventional double-sided reflow soldering. FIG. 4 is a cross-sectional side view showing an electronic component mounting method according to one embodiment of the present invention, and FIG. 5 is a cross-sectional side view showing an electronic component mounting method according to another embodiment of the present invention. Agent Masuo Oiwa Figure 1 Figure 3 Figure 4 Figure f1 Co. 5 Procedural amendment (1 shot) 1□8 O. 5.121 Flood 8 Mr. Commissioner of the Japan Patent Office 1. Indication of the case Patent application No. 58-98932 2.
Name of the invention Electronic component mounting method 3, Representative Hitoshi Katayama of the person making the amendment, Department 4, Agent 5, Detailed explanation of the invention column 6 of the specification to be amended, Contents of the amendment fl) Description page 4 In the third line, ``on the front side'' is corrected to ``on the back side''. that's all

Claims (1)

【特許請求の範囲】[Claims] (11両面印刷W配線板の表面及び裏面のいずれか一方
に高融解点の導電性接合物を用いて電子部品を接続し、
他方に低融解点の導電性接合物を用いて電子部品を接続
することを特徴とする電子部品実装方法。
(11 Connect electronic components to either the front or back side of the double-sided printed W wiring board using a conductive bonding material with a high melting point,
An electronic component mounting method characterized by connecting an electronic component to the other side using a conductive bonding material having a low melting point.
JP9893283A 1983-06-01 1983-06-01 Method of mounting electronic part Pending JPS59222994A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9893283A JPS59222994A (en) 1983-06-01 1983-06-01 Method of mounting electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9893283A JPS59222994A (en) 1983-06-01 1983-06-01 Method of mounting electronic part

Publications (1)

Publication Number Publication Date
JPS59222994A true JPS59222994A (en) 1984-12-14

Family

ID=14232892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9893283A Pending JPS59222994A (en) 1983-06-01 1983-06-01 Method of mounting electronic part

Country Status (1)

Country Link
JP (1) JPS59222994A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645370U (en) * 1992-09-03 1994-06-14 新電元工業株式会社 Mounting structure of printed wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645370U (en) * 1992-09-03 1994-06-14 新電元工業株式会社 Mounting structure of printed wiring board

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