JPS6348852A - Large scale integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a packaging space, by housing two LSIs in one package as a double-layer structure, leading one terminal group, which is connected to lead wires of each LSI, out of the side surface of the package, and leading the other terminal groups out of the lower surface of the package. CONSTITUTION:A first LSI 2 and a second LSI 3 are housed in a package 1 in two layers. Lead wires 4 are connected to the first LSI 2 at the first layer (upper stage). First terminal groups 5 are connected to the wires 4. Lead wires 6 are newly provided for the second LSI 3 at the second layer (lower stage). Second terminal groups 7 are connected to the wires 6. The second terminal groups 7, which are vertically led out of the lower surface of the package, are arranged in two lines. The odd-numbered pins are arranged on the inner side, and the even-numbered pins are arranged on the outer side. Therefore, the integration density and the number of the terminals can be more than doubled with an area kept equal to the conventional area, and the packaging space on the substrate can be reduced.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field)
High-density integrated circuits (hereinafter referred to as LS
A one-package system (SYSTEMON PAC
The present invention relates to a large-scale integrated circuit (hereinafter abbreviated as VLSI) device applied to obtain a large-scale integrated circuit (hereinafter abbreviated as VLSI).

(Conventional technology) Recently, LSI and VLSI have been developed using SI technology, and SYSTEM ON CHIP
became possible. However, as high-density integration progresses, flat no! Tukeno (F'LAT)
PACKAGE) (hereinafter abbreviated as rp) has increased in number, and various problems have arisen when mounting the rounded FP on a circuit board or the like. Currently, the number of FP bins is 14.
Although up to 4 bottles have been put into practical use, increasing the number beyond that increases problems, making it difficult to put them into practical use. In addition, high-density integration on a single chip is said to be reaching its limits due to changes in characteristics due to tip size and shrinkage.

(Problems to be Solved by the Invention) As mentioned above, in the past, the number of bins for FPs, etc. tended to be limited due to packaging issues9, and high-density integration on a single chip was limited by characteristics due to chip size and shrinkage. There is a problem that even if a one-chip system becomes possible, it is difficult to obtain a one/4' caisson stem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a VLSI device that solves the above conventional problems, increases the number of bins such as F'P, and can provide a one-package system.

[Structure of the Invention] (Means for Solving the Problems) The present invention improves the current F'P, for example, to support a large number of pins, and further improves the LSI that is densely integrated using one FPKSr technology. This was done based on the idea that a one-cell cage system could be obtained by incorporating the two-layer structure.

The VLSI device according to the present invention has first and second LSIs built into a two-layer structure within one socket, and each lead wire of the first LSI is connected to the lead wires of the first LSI.
A first group of terminals each led out from the side surface of the housing, and a second terminal connected to each lead wire of the second LSI, and a second terminal led out from the bottom surface of the housing. The t-characteristic is that it comprises a group.

(Function) According to the present invention, one /! Two LSIs in Tsukeno
is built into a two-layer structure, one group of terminals connected to each lead wire of each wire is led out from the side of the package, and the other group is led out from the bottom of the package. By leading to the outside, the FP can be improved to a multi-pin compatible F'P, thereby making it possible to obtain a simple package system, reducing the number of mounting processes, and further reducing the mounting space.

(Embodiment) FIG. 1 is a side view showing the configuration of an embodiment of the present invention.
An example is shown in which the number of FP bins is 200 pins.

FIG. 2 shows a bottom view of the embodiment shown in FIG.

FIG. 3 shows a perspective view, partially in section, of the embodiment shown in FIG.

In Figures 1 to 3, 1 is a synthetic resin casing with insulation properties, 2.3 is a first and second LSI built into the casing 1 in a two-layer structure, and 4 is a casing made of a synthetic resin with insulation properties. 1st L
The SI lead wires 5 are connected to each lead wire 4,
・The first terminal group (bin group) led out from the side surface of the Zenkaiso 1, 6 is the lead wire of the second LSI, 7 is connected to each lead wire 6, and led out from the bottom surface of the package 1. The second terminal group (bin group) shown in FIG.

One embodiment of the invention shown in FIGS.
This is an example of an F'P of a pin, and its bin arrangement is similar to the bin arrangement of a conventional FP, for example, as shown in FIG. 1 and FIG. The first terminal group 5 consisting of a bottle and, apart from this, a new FP
It consists of a total of 200 pins including a second terminal group 7 consisting of 100 pins led out from the bottom surface of the terminal.

Additionally, as shown in Figure 3, there are first and second
LSIs 2 and 3 are built in two layers, and the first LSI in the first layer (upper layer) is ? A lead wire 4 is connected to the lead wire 4 in the same manner as the lead wire of a conventional F'P, and a first terminal group 5 is connected to each of these lead wires. Also, the second L of the second layer (lower row)
S1. ? , new IJ-do wires 6 are provided, and a second terminal group 7 is connected to each of these. In this case, F
A second terminal group 7 led out perpendicularly from the lower surface of P
As shown in the figure and FIG. 3, they are arranged in two rows, with odd numbered bottles on the inside and even numbered bottles on the outside. Note that each of the second terminal groups 7 is composed of hard terminals.

As described above, according to the present invention, an FP can be easily improved to a multi-pin compatible FP.

In one embodiment of the invention described above, the invention is implemented in a 200-pin F
'When applying PK, it was explained in (・), but it can be similarly applied to FP with a number of bins other than 200 bins, and
For example, it can also be applied to a DIP type IC (integrated circuit).

[Effect of the invention] According to the present invention, the following excellent effects can be achieved.

(1) The integration rate and number of terminals can be more than doubled with the same area as the conventional F'P.

(2) One/mother system becomes possible.

(3) It can be automatically mounted on a printed circuit board, etc.

(4) The mounting space on the board can be significantly reduced.

(5) The mounting process for the board can be shortened.

[Brief explanation of drawings]

1 to 3 are views showing the construction of an embodiment of the present invention, respectively, with FIG. 1 being a side view, FIG. 2 being a bottom view, and FIG. 3 being a partially sectional perspective view. 1...Package, 2,3...IAI, 4.6...
・Lead wires, 5, 7...Terminal group.

Claims (1)

[Claims] A first and a second high-density integrated circuit built in a two-layer structure in one package are connected to respective lead wires of the first high-density integrated circuit, and each lead out from a side surface of the package. the first terminal group, and the second terminal group
A large-scale integrated circuit device comprising: a second group of terminals connected to respective lead wires of the high-density integrated circuit and led out from the bottom surface of the package.