JPS61105860A - Mounting process of ic or lsi package - Google Patents

Abstract

PURPOSE:To mount a wiring substrate mixing IC or LSI package with DIL-16 pin IC package without deteriorating the mounting concentration by a method wherein the lead conducting direction, package shape and lead pin arrangement are taken into consideration. CONSTITUTION:A print circuited substrate is provided with four layered wiring layer with through holes of 100mil grids. The second and third layers respectively for GND wiring and VEE wiring as well as the through holes for GND or VEE are connected and fixed to these layers being left as free state for other wiring layers S1, S2 for signals. The LSI package (L1, L2...) DIL-16 pin IC package mixed with DIL-16 pin IC package D1, D2 is mounted on double space. At this time, GND pins on the upper two columns of LSI package are connected to the through holes common to GND pin of DIL-16 pin IC package while GND pin on the lower two columns and for VEE are connected to the through holes not to be used in the DIL-16 pin IC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting form of an integrated circuit (LSI) package on a wiring board, and is mainly directed to the mounting of a high-speed logic LSI of an electronic computer.

In electronic computers, in response to the reform of logic elements, almost everything has now been converted to IC, and is progressing to LSI. By the way, regarding IC packages, DIL (
or DIP, dual in-line) - 16 bins (
The printed wiring board on which it is mounted is also standardized according to its pin arrangement, but on the other hand, L
Such standardization has not yet been achieved for SI packages, and their dimensions and shapes vary depending on the circuit content.
There are many problems when mounting it on a printed wiring board,
The fruits of integration are not bearing fruit. Therefore, as an attempt to standardize LSI packages, (1) increasing the number of bins in the DILIC" package, and (2) 4-side flat package (Japanese Patent Application Laid-Open No. 49-38575), etc. have been proposed in the past. Regarding (1) above, (a) the package dimensions increase as the number of pins increases, making it difficult to increase the packaging density; and (b)
When mixing with the standard 16-bin type, for example, when mounting ICs and LSIs on a multilayer wiring board, it is necessary to supply power and GND (ground) on the inner layer, but the inner layer pattern must be adjusted accordingly. Standardization is difficult due to reasons such as non-standardization. Regarding (2) above, (a)
Since the solder/reflow method is generally used for mounting on printed wiring boards, it cannot be installed at the same time as standard DTL. However, if the pitch is reduced, it will be difficult to mix with the DIL package, and a special dense substrate will be required, leading to higher product costs (as well as problems such as lower reliability). occurs.

The inventors of the present application solved the above problem by considering the lead-out direction of the leads in the package, the package shape, and the arrangement of the lead bins. Therefore, an object of the present invention is to provide a mounting method for mounting an IC or LSI package together with a DIL-16 pin IC package on a wiring board without reducing the packaging density.

A detailed explanation will be given below based on examples.

FIG. 1 shows a D I L-16 used for carrying out the present invention.
An LSI package is shown that has a planar space corresponding to two Bin TC packages.

Reference numeral 1 denotes a ceramic package substrate having a rectangular planar shape, and lead pins 2 are coaxially implanted on the bottom surface of the substrate 1 in a direction perpendicular to the surface.

In the same figure, the vertically long shapes A and B surrounded by broken lines are DIL
- This shows the pin arrangement of a 16-pin IC package.
The lead pins of the package used to carry out the present invention are arranged in two or two rows along the peripheral edge of the substrate at the same pin spacing as in the above arrangement.

Among the above lead pins, the top row and bottom row pins (represented by ■ in the figure) are used as GND (grounding) pins, and the middle row pins (represented by ■ in the figure) are used as VEIc (power supply) pins. However, the pins marked with ■ in the row two rows up from the bottom row are used as LSI inspection bins, and the other pins are used as input and output signal pins.
These do not conflict with the pin usage pattern of the DIL-16 pin located at the corresponding position.

In the same figure (d), there is a T on the top surface of the ceramic package substrate 1.
This is an example in which a cavity 3 is provided for mounting the SI chip.

FIG. 2 shows a DI L-16 pin IC on a printed wiring board with a standardized inner layer pattern according to the present invention.
A mounting form is shown in which the package and the LSI package shown in FIG. 1 are mixed and arranged. A printed wiring board with standardized wiring has, for example, four wiring layers as shown in Fig. 3, and the through hole hole 4 has a diameter of 100 ml.
It is opened with a lattice. Of these, the second layer is for GND wiring, and the third layer is for V0 wiring, which are connected and fixed to the GND or VEE through-hole holes, and are connected to other signal wiring layers S, , S. The through hole is in a free state.

Conventionally, for such printed wiring boards, DIT,
- 16-pin IC package shown in Figure 2.

The LSI package according to the present invention is mounted at predetermined intervals as shown by D,... in the same figure.
It is mounted with space for two 16-bin IC packages. In this case, the two GNs in the upper row of the LSI package
The D-bin is connected to the common through hole with the GND pin of the DIL-16 pin IC package, and the two lower rows are connected to the DIL
-It will be connected to a through hole that is not used in a 16-bin IC.

The two pins for VEIc are also connected to through holes not used in the DIL package.

According to the invention described in the embodiments above, the following effects can be brought about. (1) Any number of LSI packages can be mounted at any position on a printed wiring board having a standardized inner layer pattern by mixing them with DIL-16 pin IC packages. (2) According to the present invention, the number of pins per unit space is increased by axially arranging lead pins in multiple rows on one substrate according to the conventional pin spacing, and the number of pins per unit space is increased. Since packages and LSI packages can be mixed and arranged without gaps, it is expected that the packaging density will be improved.

This invention is not limited to the above embodiments, but has various other embodiments as described below.

(1) Figure 4 shows the standardized DIL-16 pin I board space of the LSI package used for mounting the present invention.
The C package is surrounded by the waves MA, B, and C in the same figure, with spaces arranged horizontally for three pieces.By doing this, an LSI package with more lead pins can be placed on the second board. Can be implemented.

(2) FIG. 5 is an example of an LSI package having a space in which four DIL-16-pin IC packages are arranged vertically and horizontally (indicated by broken lines A, B, C, and D in the figure).

(3) In (1) and (2) above, the lead pins are arranged in two rows along the periphery of the substrate, but this is changed to three rows,
Alternatively, the pins may be placed at other appropriate locations.

(4) The positions of the GND bin and VEI pin can be changed depending on the pattern of the printed wiring board used.

(5) The printed wiring board on which the , T, and SI packages are mounted may have a three-dimensional structure instead of a planar one.

The field to which this invention is applicable is when an integrated circuit package is mounted on a wiring board.

[Brief explanation of the drawing]

FIG. 1 shows an example of an IC package used in the present invention, in which (a) is a bottom view (or top view), (b) is a front view, and (
Figure c) is a side view, and figure (d) is a partially modified front view. FIG. 2 is a plan view showing the mode of use of this invention;
FIG. 3 is a schematic diagram showing an enlarged cross-sectional structure of the printed wiring board used in FIG. 2. FIG. 4 shows another example of the LSI package used in the present invention, (a) is a bottom view (or top view), (b) is a front view, and FIG. 5 is another example of the LSI package. It is a bottom view (or top view). 1...Package board, 2...Lead pin, 3...
・Base part, 4...Clearance hole, 5...Through hole, A, B, C, D...DTL-16 pin IC
Dashed lines showing the pin arrangement of the package, D, , D, , D, ・
・・DIL-16 pin IC package, L,,L,・・
・LSI package.

Claims (1)

[Claims] 1. IC or L on a wiring board with multiple through holes
A method for mounting an SI package, wherein an IC package having external leads arranged in two rows with lead pins at predetermined intervals is mounted on a part of the wiring board, and the IC package is mounted on the other part of the board. A method for mounting an IC or LSI package, comprising mounting an IC or LSI package that has external leads having the same pin spacing as the lead pin spacing and a planar space that is an integral multiple of the planar space of the IC package.