JPS6348179A - Rotational frequency monitor - Google Patents

Abstract

PURPOSE:To automatically detect the abnormal state of rotational frequency, by comparing the counted value of the number of pulse from a rotary encoder during a specified sampling period, with the upper limit value and the lower limit value. CONSTITUTION:By a counting means 2, the number of pulse from a rotary encoder 1 is counted during a specified sampling time. Respectively from a first detecting meane 3 and a second detecting means 4, the output of the information of an abnormal state on too high rotational frequency is generated when the counting value of the counting means 2 is larger than first rotational frequency data, and the output of the information of an abnormal state on too low rotational frequency is generated when the counting value is smaller than second rotational frequency data. Input signal is discriminated by a discriminating means 5. By a controlling means 6, the rotational frequency is contrived to be lowered when the abnormal state of too high output on the discriminating means 5 is shown, and the rotational frequency is contrived to be heightened when the abnormal state of too low output is shown.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a rotation speed monitoring device that monitors the rotation speed of a rotating machine, and particularly to a rotation speed monitoring device that monitors the rotation speed of a motor of a magnetic card inspection machine to detect abnormal rotation speed. The present invention relates to a rotation speed monitoring device that prevents malfunctions or overheating of an inspection machine.

[Conventional technology]

2. Description of the Related Art In equipment that uses a rotating machine such as a motor, such as a magnetic card inspection machine, the rotating machine must operate normally in order to ensure a predetermined accuracy or safety factor. However, due to the lifespan of the motor or some other factor, the operation of the motor becomes abnormal, and the number of revolutions increases or decreases, which often causes equipment to malfunction or become abnormally heated.

[Problem that the invention seeks to solve]

By the way, conventional magnetic card inspection machines are not equipped with a device to monitor the motor rotation speed, and whether the motor rotation speed is normal or abnormal is left entirely to the operator's judgment. . Therefore, the operator must constantly monitor whether the motor rotation speed is increasing and is dangerous, or whether the motor rotation speed is decreasing and causing inspection defects. At the same time, there was a problem in that appropriate measures could not be taken until after an abnormal situation had occurred.This invention detects an abnormality in the rotation speed and automatically takes prompt and appropriate measures. The purpose of the present invention is to provide a rotation speed monitoring device that can be used for various purposes.

[Means for solving problems]

FIG. 1 is a functional block diagram showing the configuration of the rotation speed monitoring device of the present invention.

The present invention includes a rotary encoder 1 that converts the number of rotations into a number of pulses, a counting means 2 that counts the number of pulses from the rotary encoder 1 for a predetermined period, and a first pulse number counted by the counting means 2. a first detection means 3 for detecting an abnormality in which the rotation speed is too high when the number of rotations is higher than the rotation speed data; and a first detection means 3 for detecting an abnormality in which the rotation speed is too high when the number of pulses counted by the counting means 2 is smaller than the second rotation speed data. The second detection means 4 detects that the rotation speed is too low, and the rotation speed is too high based on the detection data of the first detection means 3 and the second detection means 4. The present invention is characterized by comprising a determining means 5 for determining whether the rotation speed is too low or an abnormality, and a control means 6 for controlling the abnormal rotation of the rotating machine based on the result of the determining means 5.

[Effect]

After the rotational speed of the rotary machine is converted into a pulse number by the rotary encoder 1, the counting means 2 counts the number of pulses from the rotary encoder 1 during a predetermined sampling time. The first detection means 3 detects whether or not the number of revolutions counted by the counting means 2 is greater than preset first number of revolutions data. When the rotation speed is larger than the first rotation speed data, information indicating that the rotation speed is too high is outputted, and when the rotation speed is smaller than the first rotation speed data, information indicating that the rotation speed is not too high is outputted. Further, the second detecting means 4 detects whether or not the number of revolutions counted by the counting means 2 is smaller than preset second number of revolutions data. When the rotation speed is smaller than the second rotation speed data, information indicating that the rotation speed is too low is outputted, and when the rotation speed is larger than the second rotation speed data, information indicating that the rotation speed is not too low is outputted. If there is an abnormality in the rotation speed that is too high or too low,
The information detected by the detection means 3 and the second detection means 4 is sent to the processor, and the processor uses the determination means 5 to determine whether the information indicates an abnormality that is too high or an abnormality that is too low. 6, if the result of the determination by the determination means 5 is that the temperature is too high, control such as displaying an alarm, reducing the rotation speed, or stopping the rotation is carried out; If so, control such as displaying an alarm, increasing the number of rotations, or stopping the rotation is performed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a system configuration diagram of the rotation speed monitoring device, and FIG. 3 is a circuit diagram of the rotation speed monitoring means 11 of the rotation speed monitoring device 9.

In FIG. 2, the rotational speed monitoring device 9 operates under the control of a microprocessor 10. In FIG. microprocessor 1
0 operates according to a program stored in a read-only memory (ROM), although not shown. Control signals C and TL from the microprocessor 10 are applied to the rotation speed monitoring means 11, and the operation of the rotation speed monitoring means 11 is controlled by this control signal CTL. The rotation speed monitoring means 11 is composed of the rotary encoder 1 and the counting means 2 shown in FIG. It is detected whether the rotation speed data is smaller than the second rotation speed data.

The output of the rotation speed monitoring means 11 is applied to an interrupt driver 12 and a data buffer 13.

The data buffer 13 includes a rotation speed monitoring means 1 as described below.
1 detection data FFI and FF2 are transferred and stored.

Further, the interrupt driver 12 detects when the rotation speed of the rotating machine is either larger than the first rotation speed data or smaller than the second rotation speed data according to the output signal FFi of the rotation speed monitoring means 11. This is a pass buffer for performing interrupt processing on the microprocessor 10 only when there is an abnormality in the rotation speed, and its output signal is applied to the microprocessor 10 as an interrupt signal i RQ T.

The address decoder 14 decodes the address signal ADDR on the address bus 15 of the microprocessor 10 and selects the input/output device associated with this address signal ADDR. When an interrupt signal i RQ T is applied from the rotation speed monitoring means 11 to the processor 10 via the interrupt driver 12, the processor 10
For example, detection data FF1. It is necessary to use FF2 as data for discrimination. For this purpose, the processor 10 uses an interrupt signal 1RQT.
When the address signal ADDR is received, an address signal ADDR is sent on the address bus 15 to select the data buffer 13 as an input/output device.
At the same time, a read strobe signal R8TB is output. Address decoder 14 accesses data buffer 13 based on these output signals ADDR and R8TB from processor 10 and outputs detection data FFI and FF2 stored in data buffer 13 onto data bus 16. Based on the detected data FFI and FF2 output on the data bus 16, the processor 10 determines whether the abnormality is due to the rotation speed being too high or the rotation speed is stored in the ROM (not shown) as described later. It is determined whether the abnormality is due to a too low value, and the abnormal rotation of the rotating machine is controlled based on the result of this determination.

Next, the rotation speed monitoring means 11 shown in FIG. 2 will be explained in detail using FIG. 3.

18= In FIG. 3, a rotary encoder 1 is attached to a rotating shaft (not shown) of a rotating machine, such as a motor, and converts the number of rotations of the motor into a number of pulses by photoelectric conversion. Therefore, when the motor is rotating at high speed, the number of pulses output from rotary encoder 1 per sampling time is large, and when the motor is rotating at low speed, the number of pulses output from rotary encoder 1 per sampling time is large. becomes less. The receiver circuit 20 is for receiving the photoelectrically converted pulse signal P from the rotary encoder 1 and applying it to the counter 21 as a clock signal CLKI. counter 2
1, this clock signal CLKI is counted to count the number of pulses.

Further, the reference clock signal OK is applied to the counter 22, and a signal OUT for determining the pulse number counting period, that is, the sampling time is outputted, and a reset signal R8TF is sent to the flip-flops 23 and 24 at a predetermined timing.
Output. The output signal OUT of the counter 22 is applied to a D latch 25 and an invert 26.

The D latch 25 delays the output signal OUT of the counter 22 by one reference clock, and the output signal EBL of the D latch 25 is added to the counter 21 and the period during which the output signal EBL is high becomes the sampling time, and the output signal E
During the period when BL is high, the counter 21 can count the number of clock signals CLKI from the receiver circuit 20, that is, the number of pulses.

The output signal EBL of the D latch 25 is also applied to the AND circuit 27. The AND circuit 27 is further supplied with a signal ○UT which is an inversion of the output signal OUT of the counter 22 by an inverter 26.
I is added, and the output signal EBL and the signal 0UTI are ANDed to generate a pulse signal at the trailing edge of the output signal EBL, which is output as the clock signal CLK for the flip-flops 23 and 24. The output signal CLK of the AND circuit 27 is also applied to the delay circuit 28, and the output signal CLK is delayed by a predetermined time by the delay circuit 28 and outputted as a reset signal R8T for resetting the counter 21.

The output signal of the counter 21, that is, the count value CNT is
It is applied to one input terminal of comparators 29 and 30. The other input terminals of the comparators 29 and 30 have first and second rotation speed data HDT and LDT set by the high side setting switch 31 and the low side setting switch 32, respectively.
is added.

The comparator 29 outputs the output signal of the counter 21, that is, the counted number of revolutions indicated by the count value CNT, and the first number of revolutions data HD set by the high-side setting switch 31.
When the counted number of revolutions is larger than the number of revolutions data HDT, the output signal HR from the output terminal H of the comparator 29 becomes high, and when it is smaller, the output signal HR becomes low. Further, the comparator 30 compares the counted number of revolutions indicated by the output signal of the counter 21, that is, the count value CNT, and the second number of revolutions data LDT set by the low side setting switch 32, and The rotation speed is the rotation speed data LD.
When it is smaller than T, the output signal LR from the output terminal of the comparator 30 becomes high, and when it is larger, the output signal LR becomes low.

If the motor is operating normally when the number of revolutions of the motor is, for example, 2 to 6 revolutions per sampling time, and if it is abnormal when it is 7 revolutions or more or 1 revolution or less, then the high side setting switch 31 The first rotation speed data H
DT is set to 7", and the low side setting switch 32 is set to 2 as the second rotation speed data LDT. As a result, the output signal HR of the comparator 29 is set to the output signal of the counter 21, that is, the count value. When CNT is 7" or more, it becomes high, indicating an abnormality, and the output signal LR of the comparator 30 indicates that the count value CNT of the counter 21 is "1".
"The signal goes high in the following cases to indicate an abnormality. The rotational speed that is judged to be abnormal can be arbitrarily and easily changed by setting these switches 31 and 32 in several bit widths depending on the relationship with the sampling time. It is possible.

In addition, in this embodiment, predetermined rotation speed data HDT, L
The DT is set using switches 31 and 32, but a register (not shown) for setting rotation speed data is provided in place of the switches 31 and 32, and the processor 10
Predetermined rotation speed data may be stored from the side.

The output signal HR of the comparator 29 is the flip-flop 2
3 and the clock signal C to the flip-flop 23
The output signal FF of the flip-flop 23 is latched in synchronization with LK and when the signal HR is high when the signal CLK is input.
I becomes high. Also, the output signal L of the comparator 30
R is applied to the flip-flop 24 and latched in synchronization with the clock signal CLK to the flip-flop 24. When the signal LR is high when the signal CLK is input, the output signal FF2 of the flip-flop 24 becomes high.

If the output signal FFI of the flip-flop 23 is high, there is an abnormality in the rotational speed that is too high, and if the output signal FF2 of the flip-flop 24 is high, there is an abnormality in the rotational speed that is too low. When both the output signals FFI and FF2 are low, there is no abnormality in the rotation speed. Flip-flops 23 and 24 receive a reset signal R8 from counter 22.
Reset by TF.

Output signal FFI of flip-flops 23,24.

The FF2 becomes detection data and is stored in a predetermined position of the data buffer 13, respectively. The output signals FF1 and FF2 are also logically summed by the logical sum circuit 33, and when either the output signal FFI or FF2 is high, the output signal OR of the logical sum circuit 33 is high, and the number of rotations per sampling time is high. Indicates that the value is not within the normal range. That is, it indicates that the rotation speed is larger than the first rotation speed data HDT or smaller than the second rotation speed data LDT.

This output signal OR is latched by the interrupt flip-flop 34 and output as a signal FFI. The signal FFI becomes high when the output signal OR of the OR circuit is high, that is, when there is an abnormality in the rotation speed, and this signal FFI is sent to the processor 10 via the interrupt driver 12 as an interrupt signal i RQ T. . In response to this interrupt signal 1RQT, the processor 10 provides the address signal ADDR and read strobe signal R8TB to the address decoder 14 as described above, and the address decoder 14 controls the data buffer 13 so that the data is stored in the data buffer 13. Data FFI and FF2 are output onto the data bus 16. Data FFI, FF output on data bus 16
One of the two is high.

An example of the operation of the rotation speed monitoring device 9 having the above configuration will be explained using the time chart of FIG. 4 and the flow chart of FIG. 5.

FIG. 4(a) shows the waveform of the output signal CLKI when the rotational speed is converted into a pulse signal P by the rotary encoder 1, and the pulse signal P is received by the receiver circuit 20 and output. When the reference clock is added to the counter 22,
The counter 22 outputs a signal OU as shown in FIG. 4(b).
T is output. The output signal OUT of the counter 22 is D
It is delayed by one reference clock by the latch 25 as shown in Fig. 4(c).
It is output as an enable signal EBL as shown in FIG.

This enable signal EBL determines the sampling time when counting the number of pulses, and when the enable signal EBL is high, the counter 21 can count the number of pulses of the output signal CLKI from the receiver circuit 20.

Now, if an abnormality occurs when the motor rotation speed is 7 rotations or more or 1 rotation or less, "7" is set as the first rotation speed data HDT in the high side setting switch 31 as described above. and the low side setting switch 32 has a second
Since “2” is set as the rotation speed data LDT,
The comparator 29 compares whether the output signal of the counter 21, that is, the count value CNT of the number of pulses, has become "7" or more, and the comparator 30 compares whether the count value CNT of the counter 21 has become "2" or more. do.

During the sampling time indicated by the symbol A in FIG. 4, the output signal CLKI of the receiver circuit 20 is applied to the counter 21 by three pulses, and the count value CNT of the counter 21 is maximum "8".
Therefore, the output signal HR of the comparator 29 is maintained in a low state and does not become high as shown in FIG. 4(g). On the other hand, the output signal LR of the comparator 30 is shown in FIG. 4(h) when the second pulse is applied to the counter 21.
The state changes from high to low as shown in . The state in which the output signal HR of the comparator 29 is low and the state in which the output signal LR of the comparator 30 is low is determined by the flip-flop clock signal CLK output at the trailing edge of the enable signal EBL, as shown in FIG. 4(d). The flip-flops 23 and 24 are latched and held. As a result, the output signals FFI, F of the flip-flops 23 and 24
Since F2 is latched low as shown in FIGS. 4(i) and (j), this means that the rotational speed is normal at this time.

Immediately after latching with flip-flop 23.24, the fourth
In response to the data buffer write signal WE as shown in FIG.
FF2 (both low) are stored in predetermined positions of the data buffer 13, respectively. On the other hand, flip-flop 23.24
The detected data FFI and FF2 are logically summed by a logical sum circuit 33, and an output signal OR of the logical sum as shown in FIG. 4(1) is applied to an interrupt flip-flop 34. In this case, data FFI and FF2 are both low, and the rotation speed is normal, so the output signal OR of the OR circuit 33 becomes low, and the output signal FFI of the interrupt flip-flop
becomes low as shown in FIG. 4(m), and processor 1
No interrupts to 0 occur.

After storing the detection data FFI and FF2 in the data buffer 13 and causing the interrupt flip-flop 34 to latch the output signal OR, the counter 21 and the flip-flop 23
．． Perform initial settings with 24. This initial setting is performed by resetting the counter 21 with the reset signal R8T shown in FIG. 4(e) which is the output signal of the delay circuit 28, and by resetting the counter 21 with the reset signal R8' shown in FIG.
This is done by resetting the flip-flops 23,24 at TF.

During the next sampling period, that is, during the sampling time indicated by B in FIG.
LKI is added to the counter 21 for 8 pulses, and the output signal HR of the comparator 29 changes from a low state to a high state as shown in FIG. 4(g) when the seventh pulse is added. On the other hand, the output signal LR of the comparator 30 is shown in FIG. 4(h) when the second pulse is applied to the counter 21.
The state changes from high to low as shown in . These states of the comparators 29 and 30 are latched and held in flip-flops 23 and 24, respectively, by the flip-flop clock signal CLK shown in FIG. 4(d). In this case, the output signal FFI of the flip-flop 23 is high and the output signal FF2 of the flip-flop 24 is low, which means that the rotation speed is too high.

These output signals, that is, the detected data FFI and FF2 are respectively stored in predetermined positions of the data buffer 13 by the data buffer write signal WE of FIG. 4(k), while
These detection data FFI and FF2 are logically summed by a logical sum circuit 33. In this case, since the detection data FFI is high, the output signal ○R of the OR circuit 33 becomes high as shown in FIG. 4(1), and the output signal FFI of the interrupt flip-flop 34 becomes high as shown in FIG. 4(1). m) goes high, causing an interrupt to the processor 10.

Further, at the sampling time indicated by symbol C in FIG. 4, the output signal CLKI of the receiver circuit 20 is added to the counter 21 for one pulse, and the output signal of the comparator 29 is maintained in a low state as shown in FIG. 4(g). The output signal of the comparator 30 is maintained in a high state as shown in FIG. 4(h). These states of the comparators 29 and 30 are determined by the flip-flop clock signal C shown in FIG. 4(d).
It is latched and held by flip-flops 23 and 24 by LK. In this case, the output signal FFI of the flip-flop 23 is low and the output signal FF2 of the flip-flop 24 is high, which means that the rotation speed is too low. This output signal, that is, the detection data FFI, FF2
are respectively stored in predetermined positions of the data buffer 13 by the data buffer write signal WE in FIG. 4(k), while these detected data FFI and FF2 are stored in the OR circuit 3
A logical sum is taken at 3. In this case, detection data FF2
is high, the output signal OR of the OR circuit 33 becomes high, and the output signal FF of the interrupt flip-flop 34 becomes high.
I goes high as shown in FIG. 4(m), causing an interrupt to the processor 10.

Next, the operation when an interrupt occurs to the processor 10 will be explained using the flowchart shown in FIG.

First, the rotation speed is larger than the predetermined rotation speed data HDT (FFI is high) or the rotation speed is higher than the predetermined rotation speed data LDT.
When it is smaller than (F F 2 is high), the rotation speed is abnormal, and the interrupt signal i RQ T is sent from the interrupt driver 12 to the processor 10 so that the processor 10 can take countermeasures against this.

That is, the interrupt signal iRQT is the detection data FFI.

Sent to processor 10 when any of FF2 is high. The processor 10 sends an interrupt signal 1RQT
is sent (step 5TI). When the interrupt signal i RQ T is not sent, the rotation speed is normal, and the process returns to step STI, and the interrupt signal i
Wait until RQ T occurs. Interrupt signal i RQ
When T occurs and the processor 10 is interrupted, the processor 10 retrieves the detection data FFI and FF2 stored in the data buffer 13 and sends them to the address decoder 14 to analyze them.
An address signal ADDR and a read strobe signal R8TB for accessing are generated (step 5T2).
. The processor 10 monitors whether the detection data FFI and FF2 are output from the data buffer 13 onto the data bus 16 (step 5T3). Detection data FF1.
If FF2 has not been output yet, the process returns to step ST3 again to wait until it is output. Detection data F
When FI and FF2 are output onto the data bus 16, the processor 10 determines whether the detection data FFI is high in order to check whether there is an abnormality due to the rotation speed being too high. When the detected data FFI is high, there is an abnormality in which the rotational speed is too high, so a process for this is performed (step 5T5). This process includes measures such as displaying an alarm, controlling the motor to reduce the number of revolutions, or immediately stopping the rotation. Also, when the detection data FFI is not high,
Since the detection data FF2 is high, which means that the rotation speed is too low, a process is performed to deal with this abnormality (step 5T6). This process includes measures such as displaying an alarm, controlling the motor to increase the rotation speed,
Alternatively, measures are taken to promptly stop the rotation.

In this way, the rotation speed of a single-rotation machine is monitored during the sampling time, and an abnormality in which the rotation speed is too high or too low is automatically detected, and the processing when an abnormality is detected is automatically carried out by the processor. can be done.

〔Effect of the invention〕

As mentioned above, according to the rotation speed monitoring device according to the present invention,
To constantly monitor abnormalities when the rotational speed of a rotating machine is too high and abnormalities when the rotational speed is too low, to be able to automatically detect these abnormalities, and to have a processor take measures after detection. This prevents equipment malfunctions, overheating, etc., significantly reduces the burden on operators, and at the same time allows equipment using rotating machines to operate safely and reliably, that is, with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing the configuration of the rotation speed monitoring device of the present invention, FIG. 2 is a system configuration diagram of the rotation speed monitoring device of the present invention, and FIG. 3 is the rotation speed of the rotation speed monitoring device of FIG. FIG. 4 is a detailed circuit diagram of the monitoring means, FIG. 4 is a time chart showing the operation of the rotation speed monitoring means of FIG. 3, and FIG. 5 is a flowchart showing a program executed by the microprocessor of the rotation speed monitoring device. 1... Rotary encoder, 2... Counting means, 3...
...First comparison holding means, 4...Second holding means, 5
...Discrimination means, 6...Control means. Applicant Hitachi Electronics Engineering Co., Ltd. Agent
Patent Attorney Yoshihito Iizuka Figure 5

Claims (1)

[Claims] 1. A rotation speed monitoring device that monitors the rotation speed of a rotating machine, comprising: a rotary encoder that converts the rotation speed into a pulse number; and a counting means that counts the number of pulses from the rotary encoder for a predetermined period. , a first detection means for detecting an abnormality in which the rotational speed is too high when the number of pulses counted by the counting means is larger than the first rotational speed data; and the number of pulses counted by the counting means. a second detection means for detecting that the rotation speed is too low when the rotation speed is smaller than the second rotation speed data; and a second detection means based on the detection data of the first detection means and the second detection means. , a determining means for determining whether the rotational speed is too high or too low, and a control means for controlling the rotational abnormality of the rotating machine based on the result of the determining means. A rotation speed monitoring device characterized by: 2. The first detection means includes a high side setting switch,
The first rotation speed data can be set to be changeable by the high side setting switch, and the second detection means includes a low side setting switch, and the low side setting switch allows the second rotation speed to be changed. 2. The rotation speed monitoring device according to claim 1, wherein the rotation speed monitoring device is characterized in that the number data can be set to be changeable.