JPS634730A - Data synchronizing device in bus type line switching system - Google Patents

Abstract

PURPOSE:To attain the miniaturization and to eliminate the need for the addition of a start bit and the use of a control clock being 16 times of the transmission rate by calculating a head bit of a reception channel based on a control channel to be synchronized, and synchronizing the head data of a receptioin channel with the head bit. CONSTITUTION:The reception data is processed by using a synchronizing pulse synchronously with the head bit in the reception channel synchronously with a control channel. A control channel recognition circuit 13 applies pattern recognition processing to the inputted control channel and supplies an output to a control signal head bit time slot generating circuit 15 in the timing after cooncidence processing. the circuit 15 outputs a gate signal G2 having a timing width corresponding to a reception channel (n) to a reception signal gate circuit 17 while calculating to which order bit the object reception channel (n) corresponds from the control channel, supplies one gate signal G3 (pulse) corresponding to the head B of the reception channel (n) to a head bit detection storage circuit 21 and feeds it also to a reception data register circuit 19 unconditionally via an OR circuit 23.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a data synchronization device in a bus type circuit switching system, and more particularly, to a data synchronization device for mutual transmission and reception of digital data including voice data in a private telephone switching system or other local network. This invention relates to improvements in data synchronization devices for bus-type circuit switching systems suitable for

(Summary of the Invention) The present invention provides a receiver that is connected to a transmission line for both transmission and reception, and that receives a data signal transmitted by dividing the frame into a peer channel, a control channel, and a reception channel, with each predetermined cycle being one frame. 11 control channel detection means for detecting the control channel from the output signal of the reception means and outputting a detection signal; reception channel detection means for detecting the reception channel from the output signal of the reception means; The means includes a leading bit generating means for calculating the leading bit of the base-to-base receiving channel and outputting the leading bit, and a synchronizing means for synchronizing the received data of the receiving channel with the leading bit, so that the data is received asynchronously in a burst manner. It is possible to receive channel signals in a synchronous manner.

(Prior art and its problems) Conventionally, all PCM frame data in a digital switch is continuous data, so a balanced synchronization method can be adopted, but in a bus-type circuit switching system, channel data is continuous. Because of this, conventional synchronous methods cannot be used as is, and asynchronous methods such as start-stop synchronization are generally used.

However, if the start-stop synchronization method is adopted in this bus-type circuit switching system, a synchronization control clock pulse of about 16 times the transmission rate is required, for example, 2
A high-speed circuit element that can run a clock pulse of 32MH2 is required for the Mbl)S rate, but such high-speed elements are rare and expensive, and there are restrictions on patterns, so there is a problem that miniaturization is not possible. There is a point.

Roughly speaking, in the asynchronous method, if a Manchester encoded signal is used, in an asynchronous state, the first bit of the received data changes from a no-signal state to a "1" signal when a signal is input. There is also the problem that it is difficult to distinguish whether it is an rOJ signal or not.

That is, as shown in FIG. 4A, when the received data at the first bit changes from a no-signal state to an ``11 signal state, it becomes rLJ and then rHJ, so a synchronization pulse is output at the first change point. .

On the other hand, even if the first bit is the rOJ signal, the fourth
As shown in Figure B, a pulse synchronized with the first change point is output.

Therefore, when unnecessary pulses are masked by masking timers in both cases, the same clock is generated, and an accurate synchronization clock cannot be detected depending on the state of the leading bit of the received data.

(Object of the Invention) The present invention has been made in order to solve these conventional drawbacks, and it is possible to accurately receive receive channel signals in a synchronous manner in a bus-type circuit switching system, which are received in an asynchronous manner in a burst manner. This provides an inexpensive and compact data synchronization device.

(Structure and Effects of the Invention) In order to achieve such an object, the present invention provides a transmission line that is connected to a transmission line for both transmission and reception, and that divides the frame into a synchronization channel, a control channel, and a reception channel, with a predetermined period as one frame. a control channel detecting means for detecting the control channel from the output signal of the receiving means and outputting a detection signal, and detecting the receiving channel from the output signal of the receiving means. a receiving channel detecting means for detecting and outputting; a leading bit generating means for calculating a leading bit of the receiving channel based on the detecting means and outputting the leading bit; and synchronizing received data of the receiving channel with the leading bit. and synchronization means.

In a similar device in a bus-type circuit switching system with such a configuration, a pulse based on the first bit of the receiving channel synchronized with the control channel is output, and the received data is processed using this pulse as a synchronization pulse. can be received.

(Explanation of Examples) The present invention will be explained in detail below.

FIG. 1 is a block diagram showing an embodiment of a channel control device in a data transmission system according to the present invention.

In the same figure, a receiver 3 connected to a transmission line 1 for both transmitting and receiving functions has an amplifier circuit, a filter circuit, etc., and receives and outputs a data signal from the transmission line 1 for both transmitting and receiving purposes. It is connected to a Manchester demodulation circuit 5 for demodulating.

The demodulated signal from the Manchester demodulation circuit 5 is in a so-called bit stream format, and one frame is divided into a plurality of time slots with a predetermined period as one frame, which are allocated to a synchronization channel, a control channel, and a reception channel.

The data in the synchronization channel has a specific bit pattern, and the width of each channel is selected so that the channel data in adjacent time slots do not overlap during transmission on the transmitting/receiving transmission line 1.

Since the signals of the control channel and reception channel n have the same transmission source, the delay time of both channels is the same. The control channel and the reception channel are in a synchronous relationship.

The Manchester demodulation circuit 5 outputs the demodulated signal to the synchronous channel recognition circuit 7, and also outputs the synchronous clock pulse to the synchronous channel recognition circuit 7 and the control channel recognition circuit 13.
A data synchronization clock pulse is output to an AND gate 25 (all of which will be described later).

The synchronous channel recognition circuit 7 stores the specific bit pattern of the synchronous channel V channel, and recognizes the synchronous channel pattern in the bit stream.If the synchronous channel pattern matches the specific bit pattern, a detection signal time slot is generated. It has a function of outputting to the circuit 9.

Note that since the first bit of this synchronization channel is fixed to 0, it can be received by the synchronization circuit.

The time slot generation circuit 9 fixes the transmission time slot based on the detection signal, outputs a gate signal G1 with a width synchronized with the control channel, and outputs it to one input of the control channel reception gate circuit 11. .

The control channel reception gate circuit 17 to which the gate signal NG+ of the time slot generation circuit 9 and the demodulation signal from the Manchester demodulation circuit 5 are added selects channel data corresponding to the 1i17 control channel from the demodulation signal and sends it to the control channel recognition circuit 13. This is an AND circuit that outputs to.

The control channel recognition circuit 13 detects a control channel, and when detecting a control channel, outputs a 1111 control signal to the leading bit/time slot generation circuit 15.

For example, if the control channel is in HDLC frame format,
It consists of a flag field, an address field, a control field, an information field, an FCS field, and a flag field, and since the first bit of the flag field always starts with rOJ, it can be received by a synchronous circuit.

The leading bit/time slot generation circuit 15 determines the receiving channel n, and generates a gate signal G2 with a timing width corresponding to the receiving channel n, and outputs it to the receiving signal gate circuit 17 and the leading bit detection and holding circuit 21. The first bit of the reception channel is calculated from the control channel, and a pulse corresponding to the first bit is output as gate signal = a3 to the first bit detection and holding circuit 21 and the OR circuit 23.

The reception signal gate circuit 17 receives the demodulation signal from the Manchester demodulation circuit 5 based on the gate signal G2 from the leading bit/time slot generation circuit 15, and selects reception channel n from among the demodulation signals based on the gate signal G2.
is selected and the received data is output to the received data register circuit 19.

The gate signal G2 of the first bit/time slot generation circuit 15 is also connected to the OR circuit 23, and the gate signal G2 is connected to the OR circuit 23.
2 is output, the reception data register circuit 19 is unconditionally
is now entered.

The first bit detection holding circuit 21 is a holding circuit for gate signal @G2 which is made up of a flip-flop, and is a holding circuit for gate signal @G2.
2 is held while ON, and the output is set to O through the AND circuit 25.
It is connected to the R circuit 23 and directly to the Manchester demodulation circuit 5.

The reception data register circuit 19 generates a masking timer based on the input gate signal G3, masks the synchronization clock from the reception data, creates the synchronization clock as a synchronization clock pulse for data shifting, and shifts the reception data. I'll go.

In addition, in the embodiment described above, each circuit is controlled by MPtJ, which is not shown.

Next, the operation of the data synchronizer in the bus type circuit switching system of the present invention will be explained.

When a received signal as shown in FIG. At this time, the synchronization clock pulse is output from the Manchester demodulation circuit 5 to the synchronization channel recognition circuit 7 and the control channel recognition circuit 13, and the data synchronization clock pulse is output to the AND circuit 25, respectively.

The synchronization channel pattern of the received data is recognized by the synchronization channel recognition circuit 7, and at the timing after the matching process, a control signal as shown in FIG. The time slot generation circuit 9 creates and fixes a time slot for transmission based on the control signal, and also
A synchronizing signal G1 (FIG. 2) is output to the control channel reception gate circuit 11.

When control channel data is transmitted from the other device in the control time slot in this state rffl, the control channel reception gate circuit 11 compares the demodulated signal from the Manchester demodulation circuit 5 with the gate signal G1 and sends the gate signal G1.
A control channel is selected with a timing width of 1 and output to the control channel recognition circuit 13.

The control channel recognition circuit 13 recognizes the pattern of the input control channel ff11! ! ! is performed, and at the timing after the -match processing, the first bit of the control signal as shown in Figure 2 ■ is activated.
It is output to the time slot generation circuit 15.

The leading bit/time slot generation circuit 15 determines the time slot for reception based on the control signal, determines the number of bits from the control channel that the target reception channel n is, and calculates the timing width corresponding to the reception channel n. The gate signal G2 is outputted to the reception signal gate circuit 17, and the one-pulse gate signal G3 corresponding to the head B in the reception channel n is added to the head pip 1-detection holding circuit 21, and is unconditionally transmitted via the OR circuit 23. It is added to the reception data register circuit 19.

The received signal gate circuit 17 compares the gate signal G2 with the demodulated signal from the Manchester demodulation circuit 5 and outputs the received data (■ in FIG. 2) to the received data register circuit 19.

The first hit detection hold 14 circuit 21 holds the signal G2 based on the reception channel only while it is ON, and the output shown in FIG. Figure ■) is compared and the logical sum is O.
It is output to the reception data register circuit 19 via the R circuit 23.

As shown in FIG. 3, the reception data register circuit 19 receives a gate signal G3 corresponding to the first bit of the reception channel.
A Manchester clock is generated from a base masking timer, and any excess locks are masked from among the synchronization clocks generated based on the received data, and data shift 1~
The received data is processed to shift 1 by generating a clock pulse for shift 1.

As described above, in the present invention, synchronous reception is possible by processing received data using a synchronization pulse synchronized with the first bit of a reception channel synchronized with a control channel.

As explained above, the present invention calculates the first bit of a reception channel based on a synchronized control channel, and synchronizes the first data of the reception channel with the first bit, so that data is received asynchronously in bursts. It becomes possible to receive channel signals in a synchronous manner, and there is no need to add a starting point or a control clock that is 16 times the transmission rate as in the asynchronous method, making it inexpensive and compact.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data synchronizer in a bus-type circuit switching system according to the present invention, FIG. 2 is a timing chart of signals in the main part of FIG. 1, and FIG.
FIG. 4 is a timing chart showing the processing operation in the received data register circuit in FIG. 1, and FIG. 4 is a timing chart in a conventional bus-type circuit switching system. 1... Transmission/reception transmission line 3... Receiver 5... Manchester demodulation circuit 7... Synchronous channel recognition circuit 9... Time thrower 1 to generation circuit 11... Control channel reception gate circuit 13... - Leading bit/time slot generation circuit 15... Leading bit/time slot i/Generating circuit 17... Received signal 1
-Circuit 19... Reception data register circuit 21... Leading bit detection holding circuit Figure 1 Figure 2 = : Figure 3 (Q) 7' γr rOr
rOr r/

Claims (1)

[Claims] (1) Connected to a transmission line for both transmission and reception, and with a predetermined cycle as one frame, this frame is a synchronous channel,
a receiving means for receiving a data signal divided into a control channel and a receiving channel; a control channel detecting means for detecting the control channel from an output signal of the receiving means and outputting a detection signal; a receiving channel detecting means for detecting and outputting the receiving channel from an output signal; a starting bit generating means for calculating the leading bit of the receiving channel based on the detecting means and outputting the leading bit; and receiving data of the receiving channel. A data synchronization device in a bus-type circuit switching system, comprising: synchronization means for synchronizing the data with the first bit.