JPS6347127A - Manufacture of mulilayer printed interconnection board - Google Patents
Manufacture of mulilayer printed interconnection boardInfo
- Publication number
- JPS6347127A JPS6347127A JP19187586A JP19187586A JPS6347127A JP S6347127 A JPS6347127 A JP S6347127A JP 19187586 A JP19187586 A JP 19187586A JP 19187586 A JP19187586 A JP 19187586A JP S6347127 A JPS6347127 A JP S6347127A
- Authority
- JP
- Japan
- Prior art keywords
- fluororesin
- fluoroplastic
- inner layer
- melting point
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000002844 melting Methods 0.000 claims abstract description 26
- 230000008018 melting Effects 0.000 claims abstract description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 11
- 239000011889 copper foil Substances 0.000 abstract description 11
- 238000000465 moulding Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 9
- 229920002313 fluoropolymer Polymers 0.000 abstract 10
- 229920005989 resin Polymers 0.000 description 21
- 239000011347 resin Substances 0.000 description 21
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 229920006026 co-polymeric resin Polymers 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000004744 fabric Substances 0.000 description 5
- 239000011888 foil Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000004810 polytetrafluoroethylene Substances 0.000 description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 4
- 125000000816 ethylene group Chemical group [H]C([H])([*:1])C([H])([H])[*:2] 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 2
- 239000012779 reinforcing material Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Laminated Bodies (AREA)
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
- Lining Or Joining Of Plastics Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は、多層プリント配線板の製法に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a method for manufacturing a multilayer printed wiring board.
従来、多層プリント配線板は、たとえば、第４図にみる
ように、ガラス布等の基材にフッ素樹脂が含浸されたプ
リプレグ１′と、フッ素樹脂を樹脂分とするとともに両
面に内層回路が形成された内層材２と、外層回路となる
銅箔（外層材）３と、フッ素樹脂からなる樹脂フィルム
４とをそれぞれ所定枚ずつ重ね合わせ、フッ素樹脂が溶
融する温度で成形するようにしてつくられていた。Conventionally, multilayer printed wiring boards have been made of prepreg 1', which is a base material such as glass cloth impregnated with fluororesin, and inner layer circuits formed on both sides with fluororesin as the resin component, for example, as shown in Figure 4. The inner layer material 2, the copper foil (outer layer material) 3 that will become the outer layer circuit, and the resin film 4 made of fluororesin are stacked in predetermined amounts, respectively, and molded at a temperature where the fluororesin melts. was.
このようにしてつくられた多層プリント配線板は、フッ
素樹脂を樹脂分としているため、誘電率が低いものであ
った。しかし、前記製法によれば、成形時にフッ素樹脂
が溶融してしまうので、寸法変化率が大きくなり、得ら
れる多層プリント配線板の寸法安定性が悪かった。The multilayer printed wiring board thus produced had a low dielectric constant because it contained fluororesin as the resin component. However, according to the above manufacturing method, the fluororesin melts during molding, resulting in a large dimensional change rate and poor dimensional stability of the resulting multilayer printed wiring board.
以上の事情に鑑みて、この発明は、得られる多層プリン
ト配線板の寸法安定性を向上させることができる多層プ
リント配線板の製法を提供することを目的とする。In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a multilayer printed wiring board that can improve the dimensional stability of the obtained multilayer printed wiring board.
前記目的を達成するため、この発明は、基材に第１のフ
ッ素樹脂を保持させたのち、その第１のフッ素樹脂より
融点の低い第２のフッ素樹脂を保持させてプリプレグを
つくり、このプリプレグと、少なくとも片面に内層回路
が形成されている内層材と、外層回路となる外層材とを
所定枚ずつ、第１のフッ素樹脂の融点より低く、第２の
フッ素樹脂の融点より高い温度で積層成形して多層プリ
ント配線板を得るようにする多層プリント配線板の製法
をその要旨としている。In order to achieve the above object, the present invention makes a prepreg by holding a first fluororesin on a base material and then holding a second fluororesin having a lower melting point than that of the first fluororesin. , an inner layer material having an inner layer circuit formed on at least one side, and an outer layer material serving as an outer layer circuit are laminated at a temperature lower than the melting point of the first fluororesin and higher than the melting point of the second fluororesin. The gist of this paper is a method for manufacturing a multilayer printed wiring board by molding it to obtain a multilayer printed wiring board.
以下に、この発明を、その一実施例をあられす図面を参
照しながら詳しく説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第１図はこの発明にかかる多層プリント配線板の製法の
一実施例に用いられるプリプレグの断面を模式的にあら
れしている。FIG. 1 schematically shows a cross section of a prepreg used in an embodiment of the method for manufacturing a multilayer printed wiring board according to the present invention.
図にみるように、プリプレグ１は、基材１０に第１のフ
ッ素樹脂１１および第２のフッ素樹脂１２が保持されて
いる。第２のフッ素樹脂１２は、主として第１のフッ素
樹脂１１の外側に保持されている。このように基材１０
に第１のフッ素樹脂１１および第２のフッ素樹脂１２を
保持させるには、基材１０に第１のフッ素樹脂１１を含
浸させ、乾燥したのち、さらに、第２のフッ素樹脂１２
を含浸させ、乾燥するようにすればよい。ただし
“、これに限られるものではなく、塗布等の方法によ
って基材にフッ素樹脂を保持させるようにしてもよい。As shown in the figure, in the prepreg 1, a first fluororesin 11 and a second fluororesin 12 are held on a base material 10. The second fluororesin 12 is mainly held outside the first fluororesin 11. In this way, the base material 10
In order to hold the first fluororesin 11 and the second fluororesin 12, the base material 10 is impregnated with the first fluororesin 11, dried, and then further impregnated with the second fluororesin 12.
All you have to do is impregnate it and dry it. however
However, the present invention is not limited to this, and the fluororesin may be retained on the base material by a method such as coating.
第２のフッ素樹脂１２は、その融点が第１のフッ素樹脂
１１の融点より低いものが用いられている。たとえば、
第１のフッ素樹脂１１に４フッ化エチレン樹脂（ＰＴＦ
Ｅ、融点３２７℃）が用いられ、第２のフッ素樹脂１２
に４フッ化エチレン−パーフルオロアルキルビニルエー
テル共重合樹脂（ＰＦＡ、融点３１０℃）または４フッ
化エチレン−６７ソ化プロピレン共重合樹脂（ＦＥＰ、
融点２７０℃）が用いられている。第１のフッ素樹脂１
１に４フッ化エチレン−パーフルオロアルキルビニルエ
ーテル共重合樹脂（Ｐ Ｆ Ａ ＋融点３１０℃）を用
いる場合は、第２のフッ素樹脂１２に４７ソ化エチレン
−６フソ化プロピレン共重合樹脂（ＦＥＰ、融点２７０
℃）を用いるようにする。基材は、ガラス布、ガラス不
織布等を用いればよい。The second fluororesin 12 used has a melting point lower than that of the first fluororesin 11. for example,
The first fluororesin 11 is made of tetrafluoroethylene resin (PTF).
E, melting point 327°C) was used, and the second fluororesin 12
Tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer resin (PFA, melting point 310°C) or tetrafluoroethylene-67isopropylene copolymer resin (FEP,
(melting point 270°C) is used. First fluororesin 1
When a tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer resin (P F A + melting point 310°C) is used as the second fluororesin 12, a 47-fluorinated ethylene-6-fluorinated propylene copolymer resin (FEP, Melting point 270
℃). As the base material, glass cloth, glass nonwoven fabric, etc. may be used.
この多層プリント配線板の製法は、以上のようなプリプ
レグ１を用い、第２図にみるように、このプリプレグ１
と両面に内層回路が形成された内層材２と外層回路とな
る銅箔（外層材）３とをそれぞれ所定枚ずつ重ね合わせ
、プリプレグｌの第１のフッ素樹脂１１の融点より低く
、第２のフッ素樹脂１２の融点より高い温度で成形して
、多層プリント配線板を得るようにするのである。内層
材Ｉには、たとえば、フッ素樹脂積層板の両面に内層回
路となる回路が形成されたものを用いる。The manufacturing method of this multilayer printed wiring board uses the prepreg 1 as described above, and as shown in FIG.
The inner layer material 2 with the inner layer circuit formed on both sides and the copper foil (outer layer material) 3 which will become the outer layer circuit are stacked in predetermined amounts, and the melting point of the second fluororesin is lower than the melting point of the first fluororesin 11 of the prepreg l. The multilayer printed wiring board is obtained by molding at a temperature higher than the melting point of the fluororesin 12. As the inner layer material I, for example, a fluororesin laminate with circuits forming inner layer circuits formed on both sides is used.
このような内層材ｌは、たとえば、フッ素樹脂を基材に
含浸させたのち乾燥してプリプレグをつくり、このプリ
プレグと銅箔等の金属箔とを所定枚ずつ、必要に応じて
、フッ素樹脂からなる樹脂フィルムを介在させるように
して、積層成形してフッ素樹脂金属箔張り積層板を得た
後、このフッ素樹脂金属箔張り積層板の金属箔をエツチ
ングすることにより、フッ素樹脂金属箔張り積層板の両
面に回路形成を行うようにしてつくればよい。Such an inner layer material l can be made by, for example, impregnating a base material with a fluororesin and then drying it to make a prepreg, and then combining this prepreg and metal foil such as copper foil into predetermined sheets of the fluororesin as necessary. After laminating and molding a fluororesin metal foil-clad laminate with a resin film interposed therebetween, a fluororesin metal foil-clad laminate is obtained by etching the metal foil of the fluororesin metal foil-clad laminate. The circuit can be formed on both sides of the board.
以上のように、この多層プリント配線板の製法は、基材
１０に第１のフッ素樹脂１１を保持させたのち、その第
１のフッ素樹脂１１より融点の低い第２のフッ素樹脂１
２を保持させてプリプレグをつくり、このプリプレグ１
と、少なくとも片面に内層回路が形成されている内層材
２と、外層回路となる外層材３とを所定枚ずつ、第１の
フッ素樹脂１１の融点より低く、第２のフッ素樹脂１２
の融点より高い温度で積層成形して多層プリント配線板
を得るようにしているので、寸法安定性の良い多層プリ
ント配線板を得ることができる。これは、成形時に第１
のフッ素樹脂１１がほとんど溶融しないため、プリプレ
グ自体が補強材の役目を果たすからである。寸法安定性
を良くするためには、第１のフッ素樹脂１１を多くして
、第２のフッ素樹脂１２を可能な限り少なくするように
することが望ましい。また、内層材のフッ素樹脂に、そ
の融点が成形温度より高いものを用いるようにすれば、
内層材も補強材の役目を果たすようになり、寸法安定性
をさらに向上させることができる。As described above, the manufacturing method of this multilayer printed wiring board involves holding the first fluororesin 11 on the base material 10, and then applying the second fluororesin 1 having a lower melting point than the first fluororesin 11.
2 is retained to make prepreg, and this prepreg 1
Then, a predetermined number of sheets of inner layer material 2 having an inner layer circuit formed on at least one side and outer layer material 3 serving as the outer layer circuit are heated to a temperature lower than the melting point of the first fluororesin 11 and a second fluororesin 12.
Since the multilayer printed wiring board is obtained by lamination molding at a temperature higher than the melting point of the multilayer printed wiring board, it is possible to obtain a multilayer printed wiring board with good dimensional stability. This is the first
This is because the fluororesin 11 hardly melts, so the prepreg itself serves as a reinforcing material. In order to improve dimensional stability, it is desirable to increase the amount of the first fluororesin 11 and decrease the amount of the second fluororesin 12 as much as possible. Also, if you use a fluororesin for the inner layer material whose melting point is higher than the molding temperature,
The inner layer material also plays the role of a reinforcing material, making it possible to further improve dimensional stability.
従来使われていた樹脂フィルムは、製造工程上、均一厚
みのものが得にくい。そのため、従来のように、樹脂フ
ィルムを用いれば、板厚精度が悪くなるが、この多層プ
リント配線板の製法のようにして、かつ、第２のフッ素
樹脂１２を多くすれば、樹脂フィルムを使用せずに多層
プリント配線板を得ることができる。そのため、板厚精
度を向上させることができるとともにコストの低下もで
きる。Due to the manufacturing process, it is difficult to obtain a uniform thickness for conventionally used resin films. Therefore, if a resin film is used as in the past, the board thickness accuracy will deteriorate, but if the manufacturing method of this multilayer printed wiring board is used and the amount of the second fluororesin 12 is increased, a resin film can be used. A multilayer printed wiring board can be obtained without Therefore, it is possible to improve plate thickness accuracy and reduce costs.
なお、内層材の樹脂は、エポキシ樹脂、ポリイミド樹脂
等を用いてもよいが、誘電率の低い多層プリント配線板
を得るためにはフッ素樹脂を用いるのが好ましい。外層
材は、前記実施例のごとく銅箔等の金属箔を用いてもよ
いし、片面金属箔張り積層板を用いてもよい。この片面
金属箔張り積層板を構成する樹脂は、フッ素樹脂であっ
ても、エポキシ樹脂またはポリイミド樹脂であってもよ
い。必要に応じて、第３図にみるように、プリプレグ１
．内層材２．外層材３とともにアンクラツド板（フッ素
樹脂、ユポキシ樹脂、ポリイミド樹脂等を基材に含浸さ
せたのち乾燥してプリプレグをつくり、このプリプレグ
所定枚を、必要に応して、フッ素樹脂、エポキシ樹脂、
ポリイミド樹脂等からなる樹脂フィルムを介在させるよ
うにして、積層成形してつくられたもの）５を積層成形
するようにしてもよい。寸法安定性を重視するなら、こ
れら片面金属箔張り積層板の樹脂およびアンクラツド板
５の樹脂にも、その融点が成形温度より高いものを用い
るようにするのが好ましい。Note that as the resin for the inner layer material, epoxy resin, polyimide resin, etc. may be used, but in order to obtain a multilayer printed wiring board with a low dielectric constant, it is preferable to use fluororesin. As the outer layer material, metal foil such as copper foil may be used as in the above embodiment, or a single-sided metal foil-clad laminate may be used. The resin constituting this single-sided metal foil-clad laminate may be a fluororesin, an epoxy resin, or a polyimide resin. If necessary, prepare prepreg 1 as shown in Figure 3.
．． Inner layer material 2. Together with the outer layer material 3, a prepreg is made by impregnating the base material with an unclad board (fluororesin, upoxy resin, polyimide resin, etc.) and drying it.
A resin film made of polyimide resin or the like may be interposed to form a layer (5) which is formed by layer molding. If dimensional stability is important, it is preferable to use a resin with a melting point higher than the molding temperature for the resin of the single-sided metal foil clad laminate and the resin of the unclad plate 5.
この発明に用いられるフッ素樹脂としては、前述した４
フツ化エチレン樹脂（ＰＴＦＥ）、４フッ化エチレン−
６フ・ノ化プロピレン共重合樹脂（ＦＥＰ）、４フッ化
エチレン−パーフルオロアルキルビニルエーテル共重合
樹脂（ＰＦＡ）があげられるが、３７フ化エチレン樹脂
、２フ・ノ化エチレン樹脂等であってもよい。As the fluororesin used in this invention, the above-mentioned 4
Fluorinated ethylene resin (PTFE), tetrafluoroethylene
Examples include 6-fluorinated propylene copolymer resin (FEP) and tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer resin (PFA), but 37-fluorinated ethylene resin, 2-fluorinated ethylene resin, etc. Good too.
つぎに、実施例と比較例とを示す。Next, examples and comparative examples will be shown.
（実施例１）
ガラス布（日東紡績例製ＷＥ−０５Ｂ−１）にＰＴＦＥ
（三井デュポンフロロケミカル■製３Ｏ−Ｊ）を５５
−１％含浸させ、乾燥（約４００℃）した後、さらに、
ＦＥＰ （三井デュポンフロロケミカル側製１２０ＦＥ
Ｐ）を合計樹脂分６５ｗｔ％になるように含浸させ、乾
燥してプリプレグを得た。第２図にみるように、このプ
リプレグ１と、フッ素樹脂（ＰＴＦＥ）を樹脂分とし、
両面に内層回路が形成された内層材（厚み０．８ｍｉ＋
）２と、銅箔（厚み１８μｍ）３とを重ね合わせ、温度
３００℃、圧力１０ｋｇ／ｃシ、時間９０分の条件で成
形し、多層プリント配線板を得た。(Example 1) PTFE on glass cloth (WE-05B-1 manufactured by Nittobo Co., Ltd.)
(Mitsui DuPont Fluorochemical ■3O-J) 55
After being impregnated with −1% and dried (about 400°C),
FEP (Mitsui DuPont Fluorochemical side 120FE
P) was impregnated to a total resin content of 65 wt% and dried to obtain a prepreg. As shown in Figure 2, this prepreg 1 and fluororesin (PTFE) are used as resin components,
Inner layer material with inner layer circuits formed on both sides (thickness 0.8mi+
) 2 and copper foil (thickness: 18 μm) 3 were stacked and molded at a temperature of 300° C., a pressure of 10 kg/c, and a time of 90 minutes to obtain a multilayer printed wiring board.
（実施例２）
実施例１と同じプリプレグ、内層材、銅箔を用い、第３
図にみるように、これらプリプレグ１゜内層材２．銅箔
３とともに、フッ素樹脂（ＰＴＦＥ）とガラス布とで構
成されたアンクラツド板（厚み０．２ｍ）５を重ね合わ
せ、実施例１と同じ条件で成形し、多層プリント配線板
を得た。(Example 2) Using the same prepreg, inner layer material, and copper foil as in Example 1, the third
As shown in the figure, these prepreg 1° inner layer material 2. An unclad board (thickness: 0.2 m) 5 made of fluororesin (PTFE) and glass cloth was laminated together with the copper foil 3 and molded under the same conditions as in Example 1 to obtain a multilayer printed wiring board.
（比較例）
ガラス布（日東紡績間装ＷＥ−０５Ｂ−１０４）にＰＴ
ＦＥ （三井デュポンフロロケミカル■製３Ｏ−Ｊ）を
５５−１％含浸させ、乾燥（約４００℃）してプリプレ
グを得た。このプリプレグと、実施例１と同じ内層材お
よび銅箔とを用い、第４図にみるように、プリプレグ１
′、内層材２．銅箔３とともに、ＦＥＰからなる樹脂フ
ィルム（厚み０．１ｍ）４を重ね合わせ、温度３７０°
Ｃ１圧力１０ｋｇ／ｃＪ、時間９０分の条件で成形し、
多層プリント配線板を得た。(Comparative example) PT on glass cloth (Nitto Boseki interior WE-05B-104)
It was impregnated with 55-1% FE (3O-J manufactured by DuPont Mitsui Fluorochemical Co., Ltd.) and dried (about 400°C) to obtain a prepreg. Using this prepreg, the same inner layer material and copper foil as in Example 1, as shown in FIG.
', inner layer material 2. A resin film (thickness: 0.1 m) 4 made of FEP is superimposed on the copper foil 3 and heated to a temperature of 370°.
Molding was performed under the conditions of C1 pressure 10 kg/cJ and time 90 minutes,
A multilayer printed wiring board was obtained.
以上、得られた多層プリント配線板について、寸法変化
率を測定したところ、寸法変化率は、比較例と比べて、
実施例１が約１／２に、実施例２が約１／３にそれぞれ
小さくなっていた。また、板厚精度を測定したところ、
板厚精度は、比較例と比べて、実施例１が０．３％、実
施例２が０．５％それぞれ向上していた。なお、寸法変
化率は、２５０１１四方の試料を１２０℃で２分−１５
分冷却−１２０℃で１５分−３０分冷却して、その寸法
変化を測定した。When the dimensional change rate was measured for the multilayer printed wiring board obtained above, the dimensional change rate was as follows compared to the comparative example.
The size of Example 1 was about 1/2, and that of Example 2 was about 1/3. In addition, when measuring the plate thickness accuracy,
The plate thickness accuracy was improved by 0.3% in Example 1 and by 0.5% in Example 2 compared to the comparative example. In addition, the dimensional change rate is 25011 square samples at 120℃ for 2 minutes -15
After cooling for 15 minutes to 30 minutes at -120°C, the dimensional change was measured.
この結果かられかるように、実施例１，２は、比較例と
比べて、寸法安定性が向上している。しかも、実施例１
，２は、比較例と比べて、板厚精度も向上している。As can be seen from the results, Examples 1 and 2 have improved dimensional stability compared to the comparative example. Moreover, Example 1
, 2 also has improved plate thickness accuracy compared to the comparative example.
この発明にかかる多層プリント配線板の製法は、前記実
施例に限定されない。内層材の内層回路は、片面にのみ
形成されていてもよい。The method for manufacturing a multilayer printed wiring board according to the present invention is not limited to the above embodiments. The inner layer circuit of the inner layer material may be formed only on one side.
以上に説明してきたように、この発明にかかる多層プリ
ント配線板の製法は、基材に第１のフッ素樹脂を保持さ
せたのち、その第１のフッ素樹脂より融点の低い第２の
フッ素樹脂を保持させてプリプレグをつくり、このプリ
プレグと、少なくとも片面に内層回路が形成されている
内層材と、外層回路となる外層材とを所定枚ずつ、第１
のフッ素樹脂の融点より低く、第２のフッ素樹脂の融点
より高い温度で積層成形して多層プリント配線板を得る
ようにしているので、得られる多層プリント配線板の寸
法安定性を向上させることができるAs explained above, the method for manufacturing a multilayer printed wiring board according to the present invention involves holding a first fluororesin in a base material, and then adding a second fluororesin having a lower melting point than that of the first fluororesin. This prepreg, an inner layer material on which an inner layer circuit is formed on at least one side, and an outer layer material that will become an outer layer circuit are assembled into a first
Since the multilayer printed wiring board is obtained by lamination molding at a temperature lower than the melting point of the second fluororesin and higher than the melting point of the second fluororesin, the dimensional stability of the obtained multilayer printed wiring board can be improved. can
第１図はこの発明にかかる多層プリント配線板の製法の
一実施例に用いられるプリプレグの断面を模式的にあら
れす説明図、第２図は前記実施例において、多層プリン
ト配線板を得る際の構成を模式的にあられす側面図、第
３図は別の実施例において、多層プリント配線板を得る
際の構成を模式的にあられす側面図、第４図は従来の製
法において、多層プリント配線板を得る際の構成を模式
的にあられす側面図である。
１・・・プリプレグ ２・・・内層材 ３・・・銅箔（
外層材） １０・・・基材 １１・・・第１のフッ素
樹脂 １２・・・第２のフッ素樹脂
代理人 弁理士 松 本 武 彦
手続補正書（自発）
昭和６１年 ９月 ４日
昭和６１年 ８月１５日提出の特許ＩＥｉＮ（５）２、
発明の名称
多層プリント配線板の製法
３、補正をする者
事件との関係 特許出願人
住 所 大阪府門真市大字門真１０４８番
地名 称（５８３’）松下電工株式会社
代表者 （（ＪＩＭ帝役藤井貞夫
４、代理人
６、補正の対象
明細書
７、補正の内容
（］）明細書第７頁第１０行ないし第８頁第６行に「な
お、・・・してもよい。−ｊとあるを、下記のごとくに
訂正する。
一記一FIG. 1 is an explanatory diagram schematically showing a cross section of a prepreg used in an embodiment of the method for manufacturing a multilayer printed wiring board according to the present invention, and FIG. FIG. 3 is a side view schematically showing the structure of a multilayer printed wiring board in another embodiment, and FIG. 4 is a side view schematically showing the structure of a multilayer printed wiring board in another embodiment. FIG. 2 is a side view schematically showing the configuration when obtaining a board. 1... Prepreg 2... Inner layer material 3... Copper foil (
Outer layer material) 10...Base material 11...First fluororesin 12...Second fluororesin agent Patent attorney Takehiko Matsumoto Procedural amendment (voluntary) September 4, 1988 Patent IEiN(5)2 filed on August 15,
Name of the invention: Manufacturing method for multilayer printed wiring boards 3; Relationship with the amended case Patent applicant address: 1048 Oaza Kadoma, Kadoma City, Osaka Name (583') Representative of Matsushita Electric Works Co., Ltd. ((JIM Teiyaku Fujii) Sadao 4, Agent 6, Specification subject to amendment 7, Contents of amendment (]) From page 7, line 10 to page 8, line 6 of the specification, ``In addition, you may...-j.'' Correct the following as shown below.
Claims (1)
第１のフッ素樹脂より融点の低い第２のフッ素樹脂を保
持させてプリプレグをつくり、このプリプレグと、少な
くとも片面に内層回路が形成されている内層材と、外層
回路となる外層材とを所定枚ずつ、第１のフッ素樹脂の
融点より低く、第２のフッ素樹脂の融点より高い温度で
積層成形して多層プリント配線板を得るようにする多層
プリント配線板の製法。(1) After holding a first fluororesin on the base material, a second fluororesin having a lower melting point than the first fluororesin is held to make a prepreg, and this prepreg and an inner layer circuit are formed on at least one side. A predetermined number of sheets of the formed inner layer material and the outer layer material that will become the outer layer circuit are laminated and molded at a temperature lower than the melting point of the first fluororesin and higher than the melting point of the second fluororesin to form a multilayer printed wiring board. A method for producing a multilayer printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19187586A JPH074822B2 (en) | 1986-08-15 | 1986-08-15 | Manufacturing method of multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19187586A JPH074822B2 (en) | 1986-08-15 | 1986-08-15 | Manufacturing method of multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6347127A true JPS6347127A (en) | 1988-02-27 |
| JPH074822B2 JPH074822B2 (en) | 1995-01-25 |
Family
ID=16281925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19187586A Expired - Fee Related JPH074822B2 (en) | 1986-08-15 | 1986-08-15 | Manufacturing method of multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH074822B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661358A (en) * | 1991-06-28 | 1994-03-04 | Digital Equip Corp <Dec> | Laminated thin-film circuit using "teflon pfa" or "teflon fep" as dielectric insulator and its formation method |
| US6249962B1 (en) | 1997-09-17 | 2001-06-26 | Telefonaktiebolaget Lm Ericsson (Publ) | Process for manufacturing a multi-layer circuit board with supporting layers of different materials |
-
1986
- 1986-08-15 JP JP19187586A patent/JPH074822B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661358A (en) * | 1991-06-28 | 1994-03-04 | Digital Equip Corp <Dec> | Laminated thin-film circuit using "teflon pfa" or "teflon fep" as dielectric insulator and its formation method |
| US6249962B1 (en) | 1997-09-17 | 2001-06-26 | Telefonaktiebolaget Lm Ericsson (Publ) | Process for manufacturing a multi-layer circuit board with supporting layers of different materials |
| US6717063B2 (en) | 1997-09-17 | 2004-04-06 | Telefonaktiebolaget Lm Ericsson (Publ) | Multi-layer circuit board with supporting layers of different materials |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH074822B2 (en) | 1995-01-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |