JPS6345668A - Task starting device - Google Patents

Abstract

PURPOSE:To start a task at the highest speed by transforming all sequences needed up to the start of a desired task set between optional processors into hardware excluding 1- or 2-machine instruction needed for a task starting processor to give an instruction to a task start receiving processor for task start. CONSTITUTION:A part or the whole of an interruption vector table of each processor is allocated to a table array 3 itself of a shared memory 2 and not onto a local memory 18. Thus a task starting processor can write the task starting head address itself directly to the interruption vector table of a task start receiving processor. Therefore this processor refers to the table array 3 in an interruption response cycle to shift the processing directly to a desired task after the task start is instructed by an interruption. Thus the overhead of software is minimized. In other words, the 1- or 2-machine instruction instructing the task start is supported by software. While other instructions are all supported by hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-processor system, and in particular to an inter-processor system suitable for high-speed task activation between each processor constituting a multi-processor system. The present invention relates to a task activation device.

[Conventional technology]

Dynamic task activation in conventional multi-processor systems is basically based on hardware interrupts from peripheral input/output devices or sensor systems to the processor, as seen in Japanese Patent Laid-Open No. 60-95678. The majority. This is the same basic concept of hardware interrupts when using a single processor. Advanced systems with high connectivity require a function to issue interrupts between processors, and as seen in Japanese Unexamined Patent Application Publication No. 60-95676, a method has been adopted in which processors are connected to each other using dedicated interconnected lines. In the case of a large-scale system with a large number of processors, the wiring becomes complicated, so it is common to not draw interrupt lines between arbitrary processors, but to use dedicated connections to satisfy specific functions. In addition, processing for determining the processor that activated the normal interrupt, the starting address of the interrupt task, and accepting the interrupt indicating that the interrupt has been accepted is performed by software. In addition, as in JP-A-60-95670, the attributes of the source processor and destination processor are indicated in one time division instead of using hardware interrupts as a method for dynamically transmitting instructions and data communication between processors. There is also a method in which a signal is sent out and each processor performs the necessary operations by monitoring the signal.

[Problem that the invention seeks to solve]

When realizing intelligent processing (AI, intelligent processing), a high-speed dynamic task switching mechanism is required in order to efficiently execute chained task activation associated with information processing and inference operations of sensors, etc. In particular, in a multi-processor system, it is necessary to provide a dynamic inter-processor instruction transmission and data communication mechanism with high real-time performance that can quickly start any task at any time between any processors making up the system.

The task activation method and interprocessor communication method in conventional multiprocessor systems used a time-division communication method, and therefore used a classic interrupt method that lacked dynamicity and real-time performance, resulting in a large number of tasks. When starting a task between arbitrary processors that causes switching overhead, it is necessary to use software to determine the task starting source, the task starting processor, the task starting address, and interrupt reception processing, etc., which results in a large amount of software overhead. Both methods lacked high speed.

An object of the present invention is to propose a task activation device that can quickly implement dynamic task activation between arbitrary processors in a multiprocessor system.

[Means for solving problems]

The above purpose is to provide a multi-processor system with a high-speed shared memory that can be accessed from any processor that makes up the system, and to create a table in the shared memory that contains the processor number of the task-initiating processor and the processor number of the task-initiating processor. A decoder circuit is provided for arranging an array, causing the task initiating processor to write information regarding the task initiating start address of the task initiating processor to a desired address in the table array, and decoding the access status at that time from the internal bus of the shared memory. By analyzing this, signal information separated into the task activation source processor number and the task activation source processor number is broadcast to the processors, and under the control of each processor, interrupts as many as the number of processors can be processed in parallel. An interrupt generation circuit and an interrupt control circuit are provided, and when the processor itself is the task activation source processor, interrupt control is performed by activating (interrupt generation state) the interrupt generation flip-flop corresponding to the task activation source processor in the interrupt generation circuit. Sends active interrupt signals to the circuit 1 The interrupt control circuit performs priority processing on multiple active interrupt signals, generates an interrupt to the processor, and sends the interrupt vector corresponding to the selected interrupt to the processor. Then, the task activation source processor refers to the interrupt vector table specified by the interrupt vector, transfers processing to the interrupt service task, and then transfers the information regarding the corresponding task activation start address specified to the table array on the shared memory. Receiving is achieved by taking and setting goals and moving processing to tasks. [Effect] Since the task activation source processor can directly read and write the interrupt vector table of each processor, one interrupt service task can be set as the task itself to be activated, and the processor automatically performs the interrupt service task in the interrupt response cycle. It is possible to take the starting task start address and move processing directly to the target task. In this case, the software overhead is only the process by which the task activation source processor writes the task activation start address to an appropriate address in the table array on the shared memory, which is about 1 to 2 machine instructions in terms of processor instructions. In addition, the operation to perform one interrupt acceptance process and clear the interrupt signal is generated in the same sequence as when an interrupt occurs when the task activation source processor accesses the table array in the shared memory and obtains information regarding the task activation start address. This can be done without any software overhead by configuring the circuit to clear the corresponding active flip-flop in the interrupt generation circuit and return it to inactive using the signal generated.

With the above method, most of the processing related to interrupts is implemented in hardware, and tasks can be started by issuing hardware interrupts from any processor to any processor at any time, allowing for high-speed dynamic task activation. It can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows a block diagram of the entire system when the task activation device of the present invention is implemented in a multi-processor system. Each processor element 14o
1411 are connected to the common bus 10 to which the shared memory system 1 is connected. The buffer switch 19 connects the common bus 10 to the internal bus 21 (address bus 22, data bus 23) of the processor elements L4o to 14°.
．． It has the role of connecting one of the control buses 24). Generally, the buffer switch 19 is controlled by an access arbitration mechanism to the bus, and is controlled by a bus access arbitration mechanism.
4o~14. can randomly access the shared memory system 1 without any inconsistency in the same way as local memory. The shared memory system 1 includes a shared memory 2 and a decoder circuit 4 that decodes the shared memory internal path 30 and the shared memory internal bus 30 and monitors the access status to the shared memory 2. Of these, the decoder circuit 4 is configured such that when the common bus 10 and the shared memory internal path 30 are functionally the same,
The shared memory 2 may be placed in each processor element to monitor the common bus 10. In order to realize task activation between processors in the most flexible manner, a So "Sn, a two-dimensional table array 3 of D o-D n is set corresponding to the task activation source processor number. For example, when instructing the processor element 141 to start up the processor element 14, the task The position of Ss and cross D1 on the shared memory is assigned as an address for storing activation information (information regarding the starting address of a task).The access situation to the table array 3 is determined by the decoder circuit 4 using the shared memory address bus. 5 and control bus 7, and activates the stone 11 as a signal indicating the source processor (task activation source) and the stone 1τ as a signal indicating the destination processor (task activation source).

FIG. 2 shows the signal input/output situation around the decoder circuit 4. Since the decoder circuit 4 does not monitor the shared memory data bus 6 and only monitors the access status of the table array 3, the source signal line 8 and destination signal are used to determine which processor actually accessed the table array 3. The input 9 is connected to each processor element 14o.
~14° is taken into the interrupt generation circuit 15.

FIG. 3 shows details of the 1-interrupt generation circuit 15. When S, cross D, of table array 3 is accessed, oQ- and Mei 11 are active (1, o active)
A pulse is generated. As a result, the gate 28 gives an active (■, 0 active) pulse output to the clock input of the Philips flop 27, making lNTm active (Lo active). The state is 6 π signal 2
The state when initialized by 9 (Lo active), that is, INTo to INT, is the state set to be inactive. The interlaced line 25 is input to an interrupt control circuit 16 that can control a plurality of interrupt requests horizontally.

FIG. 4 shows the signal input/output situation of the interrupt control circuit 16. “I N To” by Interloved Lines 25
When one or more of the IN "I"n become active, the interrupt control circuit 16 sends an interrupt 20 to the CPUI 7.
At the same time, one of the active ones INTo to INTn is selected according to a certain priority, and the corresponding interrupt vector 26 is outputted to the CPU's local data bus 23 in synchronization with the CPU's interrupt response cycle. Force the CPU to fetch during the interrupt response cycle. Note that lower priority items will be postponed. I
If N T t is selected, the interrupt vector table pointed to by its corresponding interrupt vector is:

There is a one-to-one correspondence with Sm cross Dll of table array 3. That is, the CPU 17 of the processor element 14 executes the Ss cross D on the table array 3.
1 is accessed, and transfers processing to the corresponding service task according to the contents of the interrupt vector table indicating the beginning of the service task8.
For interrupt service tasks, the processor
14, accesses (reads) the address of St cross D on table array 3 to start the target task.
Then, it obtains the information about the start address of the task written there, and moves the processing to the target task according to that information. At this time, an active pulse is generated again in SSm and DS, so that the interrupt output signal INT of the flip-flop 27 corresponding to 101τ in the interrupt generation circuit 15 of PE becomes inactive. Return to This operation indicates that the interrupt has been accepted and that the next interrupt can be accepted.
If the system is monitored, errors such as duplicate interrupts can be prevented.

The above operation sequence is for a very general case where the interrupt vector table of each processor and the table array 3 on the shared memory 2, which is a task activation table, are separated. Particularly, in the present invention, a part or all of the interrupt vector table of each processor is stored in the table array 3 of the shared memory 2 instead of in the local memory 18.
We are proposing a method to assign it to that item. This allows the task activation source processor to directly write the task activation start address itself into the interrupt vector table of the task activation source processor.

Therefore, when the task activation source processor is instructed to activate a task by an interrupt, it refers to the table array during the interrupt response cycle and directly transfers processing to the target task, thereby minimizing software overhead. That is, among all the operation sequences, 1 or 2 in which the task activation source processor instructs the task activation
Only machine instructions are supported by software; everything else is supported by hardware.

From the above, the advantages of the present invention will be enumerated.

1) Since most of the task activation sequences are implemented in hardware, and there is almost no software overhead, the fastest task activation can be achieved.

2) A task can be activated from any processor to any processor at any time.

3) It is possible to accept task activation requests from multiple processors at the same time.

4) Interrupt acceptance can be processed automatically.

5) A task activation instruction can be issued by simply writing the start address of the target task to a desired address in the table array.

6) Since a common bus can be used, wiring can be simplified compared to the functionality.

〔Effect of the invention〕

According to the present invention, the sequence up to the activation of a target task between arbitrary processors is performed by excluding one or two machine instructions necessary for the task activation source processor to instruct the task activation source processor to activate the task. By converting everything to hardware, software overhead can be minimized. This allows the fastest task startup to be supported.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a multi-processor system equipped with an embodiment of the device of the present invention, FIG. 2 is a diagram showing the signal input/output state of a decoder circuit constituting the present invention, and FIG. FIG. 4 is a block diagram of the interrupt generation circuit that constitutes the present invention. FIG. 4 is a diagram showing the signal input/output state of the interrupt control circuit that constitutes the present invention.

Claims (1)

[Claims] 1. In a multi-processor system, a shared memory that can be freely accessed by all the processors that make up the system, and an internal address bus and control bus of the shared memory are decoded to determine which address in the shared memory. a decoder circuit that analyzes whether the processor has been accessed and broadcasts that information; an interrupt generation circuit that extracts information related to itself from the broadcast information for each processor and generates an interrupt signal; An interrupt control mechanism that selects one of the interrupt information generated by the circuit, generates an interrupt to the processor, and sends an interrupt vector corresponding to the selected interrupt to the processor, A task characterized by automatically generating an interrupt to any processor by writing task activation information to an appropriate address in the shared memory, fetching the task activation information on the shared memory, and starting necessary task processing. Starting device. 2. In the task activation device according to claim 1, the task is characterized in that a signal used when the task activation destination processor fetches task activation information on a shared memory is used as task processing acceptance information. Starting device. 3. In the task activation device according to claim 1, a part or all of the interrupt vector table possessed by each processor is directly allocated on the shared memory, and any processor can directly execute the interrupt of the activated processor. A task characterized in that by writing a task starting address in a vector table, the starting processor directly fetches the corresponding task starting address when referring to the interrupt vector table in interrupt response processing. Starting device.