JPH01243123A - Information processing unit - Google Patents

Abstract

PURPOSE:To improve the utilization factor of each function unit by suppressing a utilizing request except for the utilizing request from a command unit accepted when a competition is generated due to the utilizing request from each of plural command units to one among plural kinds of function units. CONSTITUTION:When the utilizing requests of a function unit 9 are simultaneously generated through signal lines 103 and 203 at a competition arbitrating unit 5, a decision is executed by a round robin scheduling. Namely, when the utilizing request from an instruction unit 1 is accepted, the competition arbitrating unit 5 sends a hold instruction through a control line 108, an OR circuit 12 and a control line 213 to an instruction unit 2. The competition arbitrating unit 5 controls an operand selector 7 through a control line 109, sends output contents from a program register unit 3 through a signal line 111 to the function unit 9, and executes a control to cause the function unit 9 to execute the processing of the instruction unit 1 through a control line 110. Thus, the utilization factors of respective function units 9 and 10 can be improved.

Description

TECHNICAL FIELD The present invention relates to an information processing device, and more particularly to a pipelined information processing device having a plurality of types of functional units capable of pipeline processing.

BACKGROUND TECHNOLOGY Conventionally, this type of information processing device has multiple types of functional units such as a floating-point arithmetic unit, a fixed-point arithmetic unit, and a keyboard unit. Only one instruction unit is used to execute the program.

Even if each functional unit is pipelined and processing can be performed in each functional unit every cycle, the instruction unit will not continue to use the same functional unit every cycle, and all functional units 1 to 1 will not continue to be used. They cannot be used at the same time.

Further, an instruction issuing unit that issues instructions to an instruction unit is not necessarily able to issue an instruction every cycle due to reasons such as ensuring side effects caused by instructions.

Such conventional information processing devices are configured to have one instruction unit for multiple types of functional units 1 to 1, so each functional unit can accept processing every cycle through pipeline processing. Even though
Since the instruction unit cannot issue usage requests to each functional unit every cycle, there is a drawback that the usage rate of each functional unit is low.

Furthermore, in a multiprocessor configuration, since each processor has these functional units, there is a drawback that the performance of the system cannot be sufficiently improved compared to the increase in the amount of hardware.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to improve the utilization rate of each functional unit, and it is possible to improve the utilization rate of each functional unit, and to reduce the amount of hardware required. The purpose of the present invention is to provide an information processing device that can improve the performance of a system.

Configuration of the Invention An information processing device according to the present invention includes a plurality of instruction units,
to a plurality of types of functional units 1 that are shared and accessed by the plurality of instruction units and capable of pipeline processing;
When there is a slight conflict due to usage requests from each of the plurality of command units 1-, one of the usage requests from the plurality of command units 1- is iH selected according to a predetermined order, and the said usage request is It is characterized by comprising a selection means for sending to one of the functional units 1 to 1, and a suppression means for suppressing usage requests other than the usage request selected by the selection means.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the information processing apparatus according to the embodiment of the present invention includes instruction units l-1 and 2, program register units 3 and 4, contention arbitration units 5 and 6, operand selectors 7.8, and function unit 71. ~9,10, and OR concave IZ411.12.

The instruction units 1 to 1 and 2 are connected to an instruction supply unit (not shown) via signal lines 101 and 201. The instruction unit 1.2 also has control lines 102, 105, 202, 2
05 to program register units 1 to 3.4.

Furthermore, the instruction units 1, 2 are connected to the contention arbitration unit 5 via signal lines 103, 203, signal lines 104.
204 to the contention arbitration unit 6.

Program register units 3.4 each have registers 3-
i (i=1.2, . . . , n), 4-i, and is connected to the operand selector 7.8 via signal lines 106, 206.

The contention arbitration unit 5.6 is connected to the OR circuit 11 via control lines 107, 207 and to the OR circuit 12 via control lines 108, 208. The contention arbitration unit 5.6 is also connected via control lines 109, 209 to the operand selector 7.8 and via control lines 110.210 to the functional units 1-9, 10.

- F - The functional unit 9.10 is connected to the program register unit 1-3, 4 via signal lines 112, 212. Here, the functional units 9 and 10 include a floating point arithmetic unit, a fixed point arithmetic unit, and a cache unit 1 to the like.

Next, a case will be described in which, for example, the instruction units 1 to 1 execute instructions using the functional unit 9.

When the instruction unit 1 receives an instruction from the instruction supply unit 1 through the signal line 101, it decodes the instruction. Functional unit 9 to be used by decoding this instruction and register 3- in program register unit 1-3 necessary for processing
1, the register 3-2 for storing the result, etc. are determined.

The register 3-1 necessary for processing is instructed to the program register unit 3 via the control line 102, and the contents of the register 3-1 in the program register unit 3 are transferred to the signal line 1.
06 to the operand selector 7.

The instruction of the functional unit 9 to be used is output to the contention arbitration unit 5 via the signal line 103, and the contention arbitration unit 1 to
5, command units 1 to 1 inputted via the signal line 103
A check is made to see if the usage request from 1 is in conflict with the usage request from 2 to instruction unit 1.

The contention arbitration unit 5 sends the output from the program register unit 3 input via the signal line 106 to the functional unit 9 via the control line 109 if there is no conflict with the usage request from the instruction unit 1. Controls the operand selector 7.

Further, the conflict arbitration unit 5 controls the functional unit 9 via the control line 110 so as to perform processing according to the output content from the operand selector 7 input via the signal line 111.

The results processed by the functional unit 1-9 are sent to the program register unit 1-3 via the signal line 112, and are written in the register unit 71-3 by a write instruction input from the instruction unit 1 via the control line 105. Written to register 3-2.

When requests to use the functional unit 9 occur simultaneously in the contention arbitration unit 5 via the signal lines 103 and 203, a round tropin (
The round robin) method is used.

Now, if conflict arbitration units 1 to 5 accept a usage request from instruction unit 1, conflict arbitration unit 1
-5 sends a hold instruction to the instruction unit 2 via the control line 108, the OR circuit 12, and the control line 213. The instruction unit 2 is held in a state in which it outputs usage requests for the functional units 1 to 9 in response to a bold instruction input via the control line 213.

In addition, the contention arbitration units 1 to 5 control the operand selector 7 via the control line 109 to send the output contents from the program register unit 3 to the functional unit 9 via the signal line 111, and the content is sent via the control line 110. The functional unit 9 is controlled to perform the processing of the instruction unit 1.

When the processing of the instruction unit)-1 is executed in the functional units 1 to 9, the execution result is sent to the block register unit 71 via the signal line 112 and sent to the instruction unit via the control line 105. The data is written to the register 3-i in the program register unit 1-3 under the control of the program register unit 1-3.

Processing from the instruction unit 2 and processing in the functional unit 10 are also performed in the same manner as the processing operations described above.

In this way, by allowing multiple instruction units 1 and 2 to share and access multiple types of functional units 9.10, it is possible to do so without significantly increasing the hardware or reducing performance. , it is possible to configure a pipeline type information processing device having a multi-processor configuration. Therefore, each functional unit 1 to 9, 1
0 utilization rate can be improved, and a device with excellent cost performance can be configured.

In addition, functional unit 9.10 is Cache Uni-y)
In the case of something like □, the instruction unit 1.
Since there is no independent information for 2, some ingenuity is required to realize this, but the processor number (instruction unit 1 to
By using the main memory address space (number) as part of the main memory address, it becomes possible to handle the main memory address space referenced by multiple instruction units in a unified manner.

Incidentally, in one embodiment of the present invention, the same functional units
・When there is a conflict between usage requests, the conflict arbitration unit 1
Whether the instruction unit that outputs the usage request that was not accepted or rejected in step 5 is held in that state, or if the next instruction in that instruction unit is a usage request to the pond's functional unit, that command is used. Obviously, requests can be made to be executed first.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a plurality of instruction units share and access a plurality of types of functional units capable of pipeline processing, and one of the plurality of functional units 1 is accessed by a plurality of instruction units. On the other hand, when a conflict occurs due to usage requests from a plurality of instruction units 71 to 71, each functional unit is This has the effect that the utilization rate of yl~ can be improved, and the performance of the system in a multiprocessor configuration can be improved compared to an increase in the amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of codes of main parts 1.2...Instruction units 1 to 5.6...Conflict arbitration unit 7.8...Operand selector 9.10...
... Functional unit 11.12 ... OR circuit

Claims (1)

[Claims] (1) a plurality of instruction units, a plurality of types of functional units that are shared and accessed by the plurality of instruction units and capable of pipeline processing, and a When a conflict occurs due to usage requests from each of the plurality of instruction units, one of the usage requests from the plurality of instruction units is selected according to a predetermined order, and the usage request is assigned to one of the functional units. An information processing apparatus comprising: a selection means for transmitting a request to a user; and a suppression means for suppressing a use request other than the use request selected by the selection means.