JPS6345139B2 - - Google Patents

Abstract

PURPOSE:To obtain a restored signal close to an original signal waveform, by setting the sampling period newly based on the result of detection in the state of change of the signal on a time axis. CONSTITUTION:A sound signal having <=4kHz frequency band by a low-pass filter LPEr is converted into a digital signal of a specified number of bits (taken as 8 bits for the explanation hereinafter) at an AD converter ADC. The specified signal processing is executed for the digital signal outputted from the AD converter ADC under the control of a control circuit CCT, and the data of amplitude is combined with a numeral relating to the zero point interval and stored in a memory M2. The data set comprising the set of information relating to the amplitude and the zero point interval is read out and given to a DA converter DAC in the stored order in the memory M2, the amplitude is converted into the amplitude li of analog quantity, the information relating to the zero point interval is converted into electric amoung gammai of analog quantity, and they are given to an interpolation circuit CP.

Description

[Detailed description of the invention]

Conventional methods for reducing the amount of data when encoding an audio signal and transmitting or recording and reproducing it as a digital signal include logarithmically compressing the signal amplitude, taking the difference, or performing delta modulation. It is well known that various methods such as There was a problem. When the amount of data decreases significantly, the applicant's company does not determine the decrease in bits in the amplitude direction, but rather in the time axis direction, and uses the waveform and signal obtained from the sample value sequence. Proposed an approximation compression method for audio signals that can be expected to significantly reduce the amount of data by approximating the waveform so that the degree of difference from the original waveform is less than a certain ratio.
(Refer to Publication No. 37660), and the implementation of this proposed method has achieved a certain degree of effectiveness. As described in , in the already proposed method described in the above publication, the sampling period is not determined based on the fine peaks and troughs of the signal waveform, but is determined based on the integral value of the deviation of the signal waveform. In other words, the sampling period is determined in such a way that waveform approximation is performed such that the degree of difference between the waveform obtained from the previous sample value and the waveform of the original signal is less than a certain ratio, and the signal Since the sampling period was not determined based on the fine peaks and troughs of the waveform, there was a tendency for the reproduction of fine waveforms in the signal to be insufficient. The present applicant has previously proposed a device that eliminates the drawbacks of the previously proposed device described in the above-mentioned publication, and that enables better sampling according to the signal waveform to obtain a restored signal close to the original signal waveform. A digital encoding device for alternating current signals as shown in FIG. 1 has been proposed. FIG. 1 is a block diagram of a recording and reproducing device including the previously proposed digital encoding device for AC signals. In FIG. 1, MIC is a microphone, ADC is an AD converter, and CCT is a microcomputer. A control circuit consisting of
M1 is the first storage device (first memory, buffer memory), M2 is the second storage device (second memory), SP is the speaker, OP is the operation unit, Br is the recording button,
Bp is the play button, Bs is the stop button, and LPFr,
LPFp is a low-pass filter, DAC is a DA converter, and CP is an interpolation circuit. Figure 2 shows the changes in the AC signal on the time axis when the AC signal is encoded by the signal encoding device included in the recording/reproducing device shown in Figure 1. This is a waveform diagram for illustrating and explaining how the sampling period is made variable. In this figure 2, Sa is an AC signal to be encoded, and The OO line indicates the AC axis. In FIG. 2, t1, t2, t3... are time positions where the AC signal Sa successively cuts the AC axis O-O,
That is, they are the time positions of successive zero points in the AC signal Sa, and are also T12, T23, T34.
. . . etc. indicate the time interval between successive zero points at time positions t1, t2, . Now, successive zero point intervals T12, T23, T34... in the AC signal Sa indicate a constant time value corresponding to 1/2 of the period of the AC signal when the AC signal has a constant frequency. In the case of an audio signal, T12 and T2 in Fig. 2 correspond to the signal content.
3, T34, etc., the time value changes. By the way, conventionally, when sampling and quantizing an analog signal to generate a digital signal, the AC signal is converted into a digital signal using a sampling pulse Ps having a constant time interval Tp shown on the AC axis line O-O in FIG. Sa
As is well known, according to the conventional method, the AC signal Sa in Fig. 2 is sampled.
As is clear from the example, the number of sampled values sampled at successive zero point intervals is
The longer the zero point interval, the greater the number of samples, but in the previously proposed device shown in Fig. 1, the number of samples increases at each zero point interval, regardless of the length of the successive zero point intervals in the AC signal. The alternating current signal is encoded as the extracted state, thereby reducing the amount of data. In other words, in the previously proposed device shown in Figure 1, the intervals between successive zero points in the AC signal Sa are equalized by a predetermined number α (however, α is a predetermined integer of 2 or more). Digital alternating current signal that can reduce the amount of data by ensuring that the time value obtained when dividing the signal is the sampling period for obtaining the sample value from the signal portion corresponding to each zero point interval. The encoder can be configured to divide each zero point interval into equal parts by α, and it is necessary to determine from the reproduced signal whether α should be 2, 3, or 4 or more. It is determined appropriately by taking into account the degree of fidelity to be achieved, the cost of the encoding device, etc. Now, in the proposed device shown in FIG. 1, successive zero points are detected on the time axis in an AC signal to be digitally encoded, and the zero point intervals on the time axis are measured. The sample period is the time value obtained by dividing the measured zero point interval into α equal parts (α is a predetermined integer of 2 or more), and from the signal portion corresponding to the zero point interval (α - 1)
Therefore, as long as each of the above-mentioned operations is performed satisfactorily, the configuration of the device is such that most of the operations are performed by analog signal processing. The apparatus may be configured such that substantially all operations thereof are performed by digital signal processing; Since the configuration of the device can be simplified, the digital signal encoding device section in the recording/reproducing device shown in FIG. It is shown as belonging to. Next, the configuration and operation of the recording/reproducing apparatus shown in FIG. 1 will be explained with reference to the block diagram in FIG. 1. The microphone MIC in FIG. filter
Give to LPFr. In the example shown in the first figure, the signal source is the microphone MIC, but it goes without saying that the signal source may be another audio signal generator. The aforementioned low-pass filter LPFr is assumed to have a cut-off frequency of 4 KHz in the following description of the embodiment. The audio signal converted into a frequency band of 4KHz or less by the low-pass filter LPFr is converted into a predetermined number of bits (8 bits in the following explanation) by the AD converter ADC.
is converted into a digital signal. In the following explanation, the sampling frequency (sampling frequency) of the AD converter ADC is 8KHz, and the AD converter ADC always converts the input audio signal into 1/8000 second samples. The amplitude value of each sample is quantized and converted into an 8-bit digital signal. The digital signal output from the AD converter ADC is converted into a digital signal with a reduced amount of data by performing predetermined signal processing under the control of a control circuit CCT that includes a microcomputer. However, the signal processing operation is
In the device with the illustrated configuration, this is performed by the control circuit CCT, the first storage device M1 (first memory M1), the second storage device M2 (second memory M2), and the like. In the following description, the first memory M1 is assumed to be a 256-byte memory, and
The second memory M2 is said to be a 64K byte memory. Next, referring to the flowchart shown in FIG. 3, the operation section OP in the recording/reproducing apparatus shown in FIG.
The encoding of signals that is sequentially performed by operating the recording button Br will be explained. When the program starts ("Start" in Figure 3) by operating the record button Br on the operation unit OP, the zero point interval provided in the control circuit CCT is measured in step (1). The 8-bit counter for At step (2)
8 bits (1 byte) one after another from AD conversion ADC
The digital signal is stored in the 256-byte first memory M1.
Further, each time the 1-byte digital signal is stored in the first memory M1, an 8-bit counter for measuring the zero point interval is counted up by one. 1 stored in the first memory M1 in step (3)
It is determined whether the amplitude value of the AC signal with respect to that indicated by the digital signal of the byte is zero or not. If it is determined that it is not zero, the process returns to step (2), and if it is determined that it is zero, the process returns to step (4). ). In step (4), the zero interval indicated by the count value of the 8-bit counter for measuring the zero point interval is divided into α equal parts (however, α is a predetermined integer of 2 or more). Obtain numerical values that correspond to (α-1) division points such that , α is 3,
If α is 4, the value obtained in step (4) is α is 2.
A/2 if α is 3, A/3 if α is 3,
2A/3, if α is 4, A/4, 2A/4,
It is 3A/4. Generally, when the zero point interval is A, the values obtained in step (4) are A/α, 2A/
α, (α-1) as shown by (α-1)A/α
Becomes an individual. Note that the above number is {(N−
1) It is obtained as the quotient obtained as a result of the calculation of A}/N, but if the above calculation produces a remainder, the number of approximately equal parts (N-1) should be obtained. Of course. In the following explanation, for simplicity, the case where α is 2 will be described as an example. In step (5), 8 to measure the zero point interval.
The first bit corresponds to 1/2 of the count value of the bit counter.
Read the amplitude value data of the first memory M1 at the address position of the memory M1 of (Measure the amplitude value data read from the first memory M1 and the zero point interval indicating the time value of the zero point interval. It may be possible to store the data in the second memory M2 of 64 Kbytes in pairs with the count value of the 8-bit counter for Since the smaller the count value of the counter to be calculated, the smaller the number of bits required, in the following explanation,
The value to be used in combination with the amplitude value data read from the first memory M1 is 1/1 of the count value of the 8-bit counter for measuring the zero point interval.
2). In step (6), reset the 8-bit counter for measuring the zero point interval and set the count value to 0.
In addition, a 15-bit counter provided for counting the number of data sets stored in the second memory M2 is set to 1 each time a new data set is stored in the second memory M2. Count up one by one and proceed to step (7). In step (7), it is determined whether or not the second memory M2 has reached the full count, or whether the stop button Bs on the operation section OP has been pressed, and the state in which the second memory M2 has reached the full count is determined. Or, if it is detected that the stop button Bs is pressed, the program ends; otherwise, it returns to step (2). In the above explanation, to simplify the explanation, the determination of the zero point of the signal is simply performed using the first memory M1.
Although it was only stated that this is done depending on whether or not the amplitude value stored in Therefore, the zero point of the AC signal is not always sampled, and the polarity of the information indicating the amplitude values sequentially stored in the first memory M1 is reversed. In this case, a determination means is used, such as assuming that it indicates the zero point of AC. In addition, if it is determined in step (3) that the amplitude value of the original AC signal is zero, the count value of an 8-bit counter for measuring the zero point interval is determined in step (4). If the number of (α-1) numerical values obtained from Individual numerical values corresponding to (α-1) dividing points that can equally divide the zero interval indicated by the count value of an 8-bit counter for measuring the interval into α pieces. are sequentially read out for each address position of the first memory M1 in which numerical values of The zero point spacing and the associated numerical value are made into a pair and stored in the second memory M2. As is clear from the above explanation, in the previously proposed encoding device, the time values obtained when the zero point interval in an AC signal is equally divided by a predetermined number α are equal to each zero point interval. The sampling period (sampling interval) is set to obtain (α-1) sample values from the corresponding signal portion, thereby reducing the amount of data. For each of the above (α-1) sample values, add the information on the zero point interval from which the sample value was obtained and related information, and combine the sample value and the information on the zero point interval. It shall be assumed that
This allows for easy decoding. Next, decoding will be explained using the block diagram shown in the first figure and the flowchart shown in the fourth figure. First, when the program shown in the flowchart of Fig. 4 is started by operating the playback button Bp of the operation section OP in the recording/playback device, step (1P) is started.
Then, a 15-bit counter provided for counting the number of data sets stored in the second memory M2 is reset, and the process proceeds to step (2P).
The 15-bit counter counts up by one every time one data set is read from the second memory M2. In step (2P), information related to the amplitude value and the zero point interval (the count value of the 8-bit counter for measuring the zero point interval is divided into α equal parts) in the order stored in the second memory M2. The data set consisting of the obtained value (in the example described above, a value that is 1/2 of the count value of the 8-bit counter described above) is read out and applied to the DA converter DAC, and in step (3P), the data set is
The converter DAC converts the above-mentioned amplitude value into an analog quantity amplitude value li, and also converts the information related to the above-mentioned zero point interval into an analog quantity electrical quantity τi, and supplies them to the interpolation circuit CP. do. FIG. 5 is a block diagram showing an example of the configuration of the interpolation circuit CP and the configuration of related parts. In this FIG. 5, DIV is a divider, INT is an integrator, and D /A1 is a DA converter that performs DA conversion on the amplitude value read from the second memory M2 and outputs an analog amplitude value li;
A2 is a DA converter that converts the information related to the zero point interval read from the second memory M2 into an analog electrical quantity τi and outputs the same. The interpolator CP is DA to its divider DIV
Output signal li of converter D/A1 and DA converter D/A
2 output signal τi is given, Xi=li/τi (1) The signal Xi is output by performing the calculation as shown in equation (1). The output signal Xi from the divider DIV is integrated by the integrator INT and output as a signal Yi. Yi=∫Xidt (2) Signal interpolation by the interpolation circuit CP is performed such that the interpolation slope θ is equal to li/τi in FIG. The interpolated signal has a waveform that approximates the original AC signal by polygonal line approximation. In order to provide the time for interpolating the signal by the interpolation operation explained with reference to FIGS. 5 and 6, that is, the time for dividing the zero point interval time into α equal parts,
In step (4P), a program delay is created so that the time to pass through step (2P), step (3P), and step (4P) is equal to the time obtained by dividing the zero point interval time described above into α equal parts. Then, in step (5P), the amplitude value is sign-inverted and output, and in step (6P), a program delay is created in the same manner as in step (4P) described above. In step (7P), it is checked whether the 15-bit counter that counts the number of data read from the second memory M2 has reached a full count, or whether the stop button Bs has been pressed, and then the 15-bit counter is counted. If the count is full or the stop button
If Bs is being manipulated, the process ends; if not, the process returns to step (2P) and the next data set is read. In the recording and reproducing apparatus shown in the first diagram, an AD converter
The sampling period in the ADC is 1/1 as in the example mentioned above.
For example, in the case of 8000 seconds, if the average zero point interval is the measured value 4, the average zero point interval is
0.5ms, so if one byte is allocated and stored for each of the amplitude value and the information related to the zero point interval, the second memory M
If you use 64K byte memory M2 as 2, it will be about 16
Seconds of audio signals will be stored and played back. In addition, in the device shown in the first figure, the interpolation circuit CP
The output signal from the is given to the speaker SP through a low-pass filter LPFp to obtain reproduced sound. According to the previously proposed device shown in Figure 1, better results were obtained compared to the already proposed method described in the publication mentioned above, but in the already proposed device shown in Figure 1, the sampling period always changes. This became a problem, and improvements were required. FIG. 7 is a block diagram of a recording and reproducing apparatus implementing the variable sampling period encoding apparatus of the present invention, which can solve the problems of the existing proposed apparatus shown in FIG. 1.
In FIG. 7, the same drawing numerals as those used in FIG. 1 are used for components corresponding to the already proposed device shown in FIG. In Figure 7, MIC is a microphone, and ADC is
The AD converter, CCT, is a control circuit including a microcomputer, M1 is the first storage device (first memory, buffer memory), M2 is the second storage device (second memory), and SP is the control circuit including a microcomputer. speaker,
OP is the operation panel, Br is the record button, Bp is the play button, Bs is the stop button, LPF is the low pass filter, DAC1 and DAC2 are
The DA converter and VLPF are variable passband type low-pass filters. An embodiment of the encoding device having a variable sampling period according to the present invention will be described with reference to the block diagram shown in FIG. The encoding device included in the recording and reproducing device shown in FIG. The sampling period (sampling interval Tc) is set. Figure 8 is an example of the waveform of the signal Sa before encoding, and the 0-0 line in Figure 8 is shown for reference. In the waveform diagram shown in Fig. 8,
Tf is the time length of a signal portion obtained by dividing the signal Sa into certain time lengths on the time axis, and the time length Tf
Each signal portion is called a signal of one frame. In the signal Sa, each one-frame signal having a predetermined time length Tf crosses the AC axis 0-0 line multiple times within the time length Tf, that is, the signal Sa crosses the AC axis 0-0 line multiple times within the time length Tf. However, the number of zero points in each one frame signal differs depending on the frequency components of the signal in each one frame. For example, , to explain the waveform Sa shown in FIG.
There are four zero points in the one-frame signal up to this point, and the number of zero points is six, three, and four in subsequent one-frame signals successively on the time axis. In the encoding device shown in FIG. 7, as mentioned above, each signal portion of the signal Sa having a predetermined constant time length Tf, that is, each one frame signal, is divided into one frame signal. The amount of data is reduced by performing encoding such that a sequence of sample values is obtained for the signal of one frame using a sampling period Tc such that the time length is equally divided by a number related to the number of zero points that exist. In this respect, the signal shown in Fig. 8 mentioned above is
The following is an explanation using Sa as an example. That is, when the number of zero points of the signal of one frame successively on the time axis is 8, 4, 6, 3, or 4 as described above, as in the signal Sa shown in Figure 8. For example, for a signal of one frame with 8 zero points, the time length Tf is (8
×K) In order to obtain a sequence of sample values from the signal of one frame with a sampling period that is divided into equal parts,
For example, for a signal of one frame with four zero points, the sequence of sampled values from the signal of one frame will be Similarly, for each one-frame signal where the number of zero points is 6 or 3, the time length Tf is divided equally into (6 x K) or (3 x K). A sequence of sample values from each frame of the signal is obtained at a sampling period such that
When the number of zero points in one frame signal is Z (in the device of the present invention that digitally encodes an AC signal, the signal to be processed is an AC signal, and the DC signal is not a DC signal to be processed). (and Z does not read zero for a longer period than the period corresponding to the lowest frequency of the AC signal being processed during signal processing),
For the signal of one frame, a sequence of sample values is obtained at a sampling period such that the time length Tf is equally divided by (Z x K), and the encoding means described above is used. For example, recording and reproducing operations can be easily realized with a reduced amount of data. The data obtained by the above-mentioned encoding means, that is, the sample value sequence from each one frame signal having a predetermined time length Tf, is specified as the number Z of zero points in one frame signal. The data obtained by sampling with the sampling period obtained by equally dividing the time length Tf by the number (Z × K) having the following relationship is the data and the sampling period Tc. , the number N of sample values in one frame signal, and information such as the frame number are used for transmission or recording in pairs. Also, as is clear from the above, the sample values obtained corresponding to each one frame signal are:
Since each one-frame signal has a fixed sampling period, the low-pass filter used in the reproduction system is By variably controlling the passband in correspondence with the sampling period, it is possible to easily prevent aliasing distortion from occurring in the reproduced signal. That is, during reproduction, as will be described later, when reading from the storage device, data is read out at time intervals corresponding to a sampling period that has a specific relationship with the number of zero points in each frame of the signal, and then DA conversion is performed. is given as an input signal to a variable passband type low-pass filter, and a sample value indicating the amplitude value of the original signal described above and data indicating a sampling period are combined to obtain the sample value. For data indicating the sampling period of digital data,
After DA converting it, it is given as a control signal to the variable pass band type low pass filter described above, and the cutoff frequency of the variable pass band type low pass filter described above indicates the sampling period in the digital data described above. By changing the data using a control signal obtained by DA converting the data, a good reproduced signal can always be obtained. The above point will be specifically explained as follows. According to the well-known sampling theorem, the frequency band in which a sampled signal can be reproduced without distortion is a frequency band that is less than or equal to 1/2 of the sampling frequency (the reciprocal of the sampling period). The frequency band reproduced by is a frequency band that is less than 1/2 of the reciprocal of the sampling period (sampling frequency) of the sampling pulse used to encode the encoded signal, and is higher than the frequency band mentioned above. As is well known, in the upper frequency band there are signals that cause aliasing distortion in the reproduced signal. Therefore, in order to prevent aliasing distortion from being mixed into the reproduced signal, a low-pass filter (low-pass filter) used when reproducing the encoded signal is used to filter the signal that is being reproduced. A device with a pass characteristic that allows passing only signals in a frequency band of 1/2 or less of the sampling frequency of the sampling pulse used for encoding is used. If the signal being encoded is sampled using a sampling pulse with a repetition rate of 10KHz, the low-pass filter used when reproducing that signal will not introduce aliasing distortion into the reproduced signal. In order to do this, a filter is used that has a pass characteristic that allows only signals in a frequency band of 1/2 or less of the 10KHz sampling pulse mentioned above to pass, and for example, if the signal to be reproduced is , in encoding it
If the sample was sampled using a sampling pulse with a repetition frequency of 1KHz, the low-pass filter used when reproducing the signal would be the one described above in order to prevent aliasing distortion from being mixed into the reproduced signal.
A device having a passing characteristic that allows passing only signals in a frequency band of 1/2 or less of a 1 KHz sampling pulse will be used. by the way,
When the signal reproduction system reproduces a signal sampled with a high repetition frequency sampling pulse and a signal sampled with a low repetition frequency sampling pulse, for example, as in the above example,
Let's reproduce a signal sampled with a 10KHz sampling pulse, that is, a reproduction signal that has a frequency band up to 5KHz, and a signal sampled with a 1KHz sampling pulse, that is, a reproduction signal that has a frequency band up to 0.5KHz. In this case, it is natural to use a low-pass filter that can pass signals up to 5KHz in the reproduction system. In order to ensure good reproduction, if a low-pass filter is installed in the reproduction system that can pass signals up to 5KHz,
Although aliasing distortion will be mixed into the 0.5KHz signal, by changing the passband of the low-pass filter in accordance with the sampling period set for each frame signal, , a good reproduced signal can always be obtained. Next, the configuration and operation of the recording/reproducing apparatus shown in FIG. 7 will be explained. Microphone shown in Figure 7
The MIC converts sound waves into electrical signals (audio signals) and sends them to the low-pass filter LPF. In the recording and reproducing apparatus shown in FIG. 7, a microphone MIC is used as a signal source, but the signal source may be another type of audio signal generator or another signal generator. In the following example description, the low-pass filter LPF is as follows:
Its cutoff frequency is said to be 3KHz.
The audio signal converted into a frequency band signal of 3KHz or less by the low-pass filter LPF is converted into a digital signal with the required number of bits (8 bits in the following explanation) by the AD converter ADC, and then sent to the microcomputer. The above-mentioned AD converter ADC performs AD conversion using pulses with a repetition frequency of 8 KHz from a clock pulse generator CG. In the digital signal output from the AD converter ADC, the input audio signal is always sampled at a constant sampling period (1/8000 seconds in the example).
This is a quantized 8-bit digital signal, which is sequentially stored in the first storage device M1 (first memory M1 or buffer memory M1) under the control of the control circuit CCT. The buffer memory M1 mentioned above is assumed to have a storage capacity of 512 bytes in the following explanation example, and it is divided into two parts each having half the storage capacity, and these two parts are used to store data alternately. Used for writing and reading data. Now, the recording operation of the recording/playback device is performed using the operation section OP.
By operating the record button Br in
This is carried out according to the program shown in the flow chart shown in Fig. 9, and when the record button Br in the operation section OP is operated and the program shown in Fig. 9 starts ("Start" in Fig. 9). , a 9-bit sample counter, an 8-bit zero point counter, a 16-bit frame counter, etc. provided in the control circuit CCT are reset in step (1r). Before the record button Br is operated, that is, the 9th
Even before the "beginning" in the illustrated flowchart, the control circuit CCT of the recording/reproducing apparatus performs a step (10r) interrupt operation by receiving pulses from the clock pulse generator CG, and the AD converter The digital signal output from the ADC is sequentially stored in the buffer memory M1, and a 9-bit sample counter is counted up. At step (2r), the stored sample value is read from the buffer memory M1, and the 9-bit sample counter is counted up by 1. In step (3r), it is checked whether the sign of the sample value read in step (2r) is the same as the sign of the sample value immediately before it, and if there is no change in sign, it is assumed that the point is not zero and step ( Return to step 2r), and when there is a change in sign, assume that the sample value read in step (2r) is the zero point, proceed to step (4r), and in step (4r) count the 8-bit zero point counter by 1. rise. In step (5r), check whether the number of sample values sequentially read from the buffer memory M1 has reached 256 using the counted value of the 9-bit sample counter.
The number of sample values read from buffer memory M1 is
Once you reach 256 (that is, steps (2r) to (4r)
After repeating 256 times, proceed to step (6r), and if the number of sample values read from buffer memory M1 has not reached 256, proceed to step (2r).
Return to Here, the number of sample values 256 read out from the buffer memory M1 as described above is calculated as follows for one frame of signal Sa of time length Tf shown in FIG.
The AD converter ADC has a constant sampling period (1/8000
This is the number of sample values obtained by sampling in seconds). In step (6r), using the count value Zc of the 8-bit zero point counter, the predetermined number K, and the number 256 representing the time length Tf of the signal of one frame, the sample in the signal of one frame is calculated. The sampling period Tc required to obtain the value sequence is calculated, and the number of samples N is also calculated. Sampling period Tc = 256/Zc・K As buffer memory M1, the one with a storage capacity of 512 bytes as mentioned above is divided into two parts with a storage capacity of 1/2, and the two parts are used for writing and reading. The time length of one frame signal is
Assume that a signal with 256 samples in one frame is stored and read out in 32 milliseconds.
Now, for example, if the number K mentioned above is set to 2 and the number Zc of zero points in the signal of one frame is 32, the sampling period Tc is Tc = 256/32 x 2 = 4, that is, 4/8000=0.5 (milliseconds). In the above example, the number of samples N is 64, which is 256
The signal of one frame with a time length of 32 milliseconds is made up of 64 samples. All you have to do is process the remainder appropriately, such as rounding it down, rounding it up, or rounding it up to the nearest integer. If a low-pass filter with a cut-off frequency of 1 KHz or less, for example 750 Hz, is used as a low-pass filter installed in the reproduction system, then according to the well-known sampling theorem, the signal of one frame with the number of samples is 64. No aliasing distortion occurs. Also, if the average zero point interval Zc in the entire signal is 32, then the number of samples N = 256/Tc Next, in step (7r), the above-mentioned sampling period Tc is applied from the buffer memory M1 to obtain the sample value. In order to sequentially read sample values for each sampling period Tc for the signal of one frame from which a column is to be taken out, the count value of the 9-bit sample counter (address counter) at every Tc is used as an address signal in the buffer memory M1. N sample values are read out sequentially from and store it in the second storage device M2
(2nd memory M2) and step (8r)
Proceed to. In step (8r), the 16-bit frame counter is counted up by 1. In step (9r), check whether the 16-bit frame counter has reached a full count or whether the stop button Bs has been operated. If so, the process is over; if not, return to step (2r) and repeat each step above. 2 bytes corresponding to the count number Fc of the frame counter, 1 byte corresponding to the number of samples N, 1 byte corresponding to the sampling period Tc, and a 64-byte sample value string to create one frame signal. On the other hand, a second memory M2 with a storage capacity of 68 bytes is required, so if a 64K byte memory is used as the second memory M2, the second memory M2 will have 963
A frame, or approximately 30+ seconds of signal, will be stored. As is clear from the above description, the second memory M2 stores, for each frame of the signal, data with a sampling period Tc, a sequence of sample values, data with a number of samples N, and a frame number Fc (frame counter). A digital signal containing a set of count values Fc), etc. is stored, but the amount of data has been greatly reduced compared to the original digital signal stored in the first memory M1 (buffer memory M1). The amount of data is reduced by the above-mentioned encoding performed at the time of recording, making it possible to record and reproduce audio signals over a long period of time using a small capacity memory. Next, a case where the audio signal is reproduced by reading out the signal stored in the second memory M2 as described above will be described with reference to the flowchart shown in FIG. 10. When the playback button Bp on the operating section OP of the recording/playback device is operated, the program shown in Figure 10 starts ("Start" in Figure 10) and completes the full step (1rp).
At step (2rp), the frame counter and sample counter are reset, and at step (2rp) 1 is transferred from the second memory M2.
The number of samples N in the signal of the frame and the data of the sampling period Tc are read out, and then, in step (3rp), the sample values are read out from the second memory M2 in the order in which they were stored.
are read out one by one and given to the DA converter ADC1,
In addition, the data of sampling period Tc is DA conversion DAC2
given to. At step (4rp), step (2rp) ~
Waiting is performed so that the time required for one round (5rp) matches the time length indicated by the sampling period Tc. In step (5rp), it is determined whether or not reading of the N sample values has been completed. If the reading has not been completed yet, the process returns to step (2rp), and if it has been completed, the process advances to step (6rp). Step (6rp)
Now check whether the frame counter has reached full count or whether the stop button Bs has been operated.
If the frame counter has reached full count or if the stop button Bs has been operated, the process ends; otherwise, the process returns to step (2rp). DA converter in the above step (3rp)
By supplying digital data to DAC1 and DAC2, analog signals corresponding to successive sample values within one frame signal are supplied as input signals from the DA converter DAC1 to the variable passband type low-pass filter VLPF. Also, the sampling period of the sample value in one frame signal is output from the DA converter DAC2.
An analog signal corresponding to Tc is given to a variable pass band type low pass filter VLPF as its control signal. FIG. 11 is a block circuit diagram showing a configuration example of the DA converters DAC1 and DAC2 and a variable pass band type low pass filter VLPF. The higher cutoff frequency in the variable range of cutoff frequency is resistor R5, R
8 and capacitors C1 and C2, and the lower cutoff frequency in the variable range of cutoff frequency is determined by resistors R6 and R7 and capacitors C1 and C2.
2, and furthermore, the intermediate frequency value of the cut-off frequency variable range described above is determined by the DA converter.
an analog switch ASW that is switched by data input with a sampling period Tc input to DAC2;
variable resistors R2, each connected in series;
By varying R3, it is adjusted to a predetermined frequency value corresponding to the data of the sampling period Tc. An example of the correspondence between the sampling period Tc, the sampling frequency fs corresponding to the sampling period Tc, and the cutoff frequency fc of the low-pass filter is shown in Table 1 below.

[Table] The variable passband type low-pass filter VLPF shown in Fig. 11 has a resistance selected by the analog switch ASW according to the data value of the sampling period Tc given to the DA converter DAC2. Amplifier A1
The gain of the photocoupler PC changes accordingly.
1, PC2 (Photo couplers PC1 and PC2 may have the same configuration, and it is a variable resistor.
A photoresistor (e.g.
Cds) VR, the cutoff frequency changes by changing the resistance value of VR, and the pass band is variably controlled. In addition, in FIG. 11, R1, R4, R
5 to R8 are resistors, R2 and R3 are variable resistors, A
1, A2 is an amplifier, C1, C2 is a capacitor,
PC1 and PC2 are photocouplers. In the description of the embodiments so far, the coding device with a variable sampling period of the present invention is used in a recording/reproducing device, but the device of the present invention can convert it into a digital signal. It goes without saying that the present invention may also be used as an encoding device in a transmission system. As is clear from the detailed explanation above, the encoding device with variable sampling period of the present invention has the following features:
means for sampling and quantizing the signal to be encoded at a predetermined sampling period; means for storing the digital signal obtained by said means; and a predetermined fixed time period in said signal. Means for detecting the number Z of zero points for each signal of one frame by treating the signal for each length Tf as a signal of one frame, and a predetermined coefficient for the number Z of zero points obtained by the detection means. means for setting, for each one-frame signal, a new sampling period corresponding to the time length obtained by equally dividing the time length Tf of the one-frame signal described above by a value Z·K multiplied by K; , selectively reading the digital signal stored in the storage means using the new sampling period, and indicating the selectively read digital signal and the new sampling period. a variable sampling period encoding device comprising means for obtaining data in pairs with data; and means for sampling and quantizing a signal to be encoded at a predetermined sampling period; and said means. a first storage means for storing a digital signal obtained by the above-mentioned method;
means for detecting the number Z of zero points for each signal of one frame; and a value Z.
The time length of one frame signal as described above by K
means for setting a new sampling period corresponding to the time length obtained by equally dividing Tf for each one-frame signal; and storing the above-mentioned new sampling period in the above-mentioned first storage means. means for selectively reading the digital signal read out, and obtaining data in which the selectively read out digital signal and data indicating the new sampling period are set; and the set of data. Since this is an encoding device with a variable sampling period, the encoded signal has a greatly reduced amount of data, and is also easy to decode. It is clear that the apparatus of the present invention can satisfactorily eliminate all the drawbacks of the prior art.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a recording and reproducing device including the already proposed digital encoding device for AC signals, FIGS. 2 and 8 are waveform example diagrams for explanation, and FIG.
4, 9 and 10 are flowcharts, and FIG. 5 is a block diagram of an example configuration of an interpolation circuit.
FIG. 6 is a characteristic example diagram, FIG. 7 is a block diagram of a recording/reproducing device including the encoding device with variable sampling period of the present invention, and FIG. 11 is a variable passband type low-pass filter. FIG. 2 is a block circuit diagram showing an example of the configuration. MIC…Microphone, LPF, LPFr, LPFp…
Low-pass filter, ADC...AD converter, CG...clock pulse generator, CCT...control circuit including microcomputer, OP...operation unit,
DAC, DAC1, DAC2...DA converter, M1...first storage device (first memory, buffer memory),
M2...Second storage device (second memory), VLPF
...Variable passband type low-pass filter, CP...Interpolation circuit.

Claims (1)

[Scope of Claims] 1. Means for sampling and quantizing a signal to be encoded at a predetermined sampling period, means for storing a digital signal obtained by the above-mentioned means, and 1. Means for detecting the number Z of zero points for each signal of one frame with a signal for each predetermined fixed time length Tf as a signal of one frame, and the number of zero points obtained by the above-mentioned detection means. Each new sampling period corresponding to the time length obtained by equally dividing the time length Tf of one frame signal described above by the value Z・K obtained by multiplying Z by a predetermined coefficient K is calculated.
means for selectively reading the digital signals stored in the storage means using the new sampling period, and the selectively read digital signals;
and means for obtaining data in pairs with the data indicating the new sampling period. 2. Means for sampling and quantizing the signal to be encoded at a predetermined sampling period, first storage means for storing the digital signal obtained by the above-mentioned means, and a predetermined method for the above-mentioned signal. The signal for each fixed time length Tf is considered to be one frame signal, and each
A means for detecting the number Z of zero points for each frame signal, and a numerical value Z·K obtained by multiplying the number Z of zero points obtained by the detecting means by a predetermined coefficient K. means for setting, for each frame signal, a new sampling period corresponding to the time length obtained by equally dividing the time length Tf of the frame signal;
Using the new sampling period described above, the first
means for selectively reading the digital signal stored in the storage means and obtaining data that is a set of the selectively read digital signal and data indicating the new sampling period; and second storage means for storing the aforementioned set of data.