GB2084433A - Methods and apparatus or encoding and constructing signals - Google Patents

Abstract

Where a signal is represented by a succession of first and second signals representing respective characteristics of portions of the signal waveform and the first and second signals are drawn from respective sets of primary symbols, the apparatus and methods described may be used to effect a reduction in the number of symbols used. First signals in the form of quantised durations of half cycles of a signal to be encoded are derived by zero logic 12 and second signals in the form of a number of events in a half cycle are derived by event logic 13. On application to a map circuit 15, the number of secondary symbols required in a set capable of representing each half cycle is reduced compared with the number of primary symbols (quanta and events). Methods and apparatus for reconstructing signals encoded by secondary symbols are also described.

Description

SPECIFICATION Methods and apparatus for encoding and constructing signals The present invention relates to methods and apparatus for encoding and constructing signals, and it is particularly, but not exclusively, concerned with the encoding of speech signals or waveforms.

Patent Application 7910929 describes and claims methods and apparatus for encoding signals, having complex waveforms, in the form of a succession of pairs of signals in which one signal represents the duration of a subdivision (for example between zero crossings) and the other signal represents a characteristic shape of the subdivision (for example the number of minima). For bandwidth limited signals this encoding allows each subdivision to be described by pairs of signals in which each signal is selected from limited respective sets of predetermined signals.

According to a first aspect of the present invention there is provided apparatus for encoding varying signals, comprising means for generating a succession of pairs of first and second signals in which, in each pair, the first signal represents a first number representative of a first characteristic of a portion of the signal to be encoded and the second signal represents a second number representative of a second characteristic of the said portion, the first and second numbers being selected from predetermined sets of first and second numbers, respectively, and the apparatus also comprising means for generating a succession of secondary signals, each secondary signal being selected from a predetermined set of secondary signals in accordance with a pair of first and second signals, and the apparatus being such that a useful reconstruction of a signal which has been encoded can be carried out from the succession of secondary signals only.

The main advantage of the present invention is that where waveforms are represented by pairs of signals, so reducing bit rate, a further reduction in bit rate is achieved. For example by using the invention speech may be adequately represented by about 1 ,000 symbols per second where each symbol represents a pair comprising one first signal and one second signal relating to one half cycle.

This is a reduction in the number of distinct symbols per second required for example in any of the conventional direct waveform coding schemes described by L. S. Moye in a paper entitled "Digital Transmission of Speech at Low Bit Rates", Electrical Communication, Volume 47, Number 4, 1972.

Further it has been discovered that the symbols which result from a speech waveform encoded by generating first and second signals for every half cycle are highly redundant and that a large percentage may be omitted to reduce the average symbol rate further without loss of speech intelligibility. By this means speech may be adequately represented by about 300 symbols per second.

In view of the low bit rate needed to encode speech, the invention is advantageous for recording, since the number of bits to be stored per second of speech is much reduced. In transmission by line or radio the low bit rate means that a narrower bandwidth is required for transmission than for conventional systems.

The reduction of speech signals to a low number of symbols enables speech synthesisers to be simplified since the symbols may then be stored in a small memory and called for decoding according to the speech sound required. Other sounds can also be economically synthesised in a similar way.

According to a second aspect of the invention there is provided apparatus for constructing a required signal from a succession of signals in which each signal is one of a predetermined set of secondary signals each of which represents a first number and a second number from respective predetermined sets of first and second numbers, each first number and each second number representing a respective first and second characteristic of a portion of the required signal, the apparatus comprising means for deriving, from a succession of said secondary signals, pairs of first and second signals in which the first signal represents a said first number, and means for deriving analogue signals from the pairs of signals derived, the analogue signals having portions with characteristics in accordance with the numbers represented by the first and second signals of the derived pairs.

It will be appreciated that what amounts to a useful reconstruction depends on the use of the invention. For example, in some circumstances it may be sufficient if reconstructed speech can be understood without, for example, the speaker being identifiable from the reconstructed speech, while in other circumstances, for instance in telephony provided by a pubiic service a higher standard is required.

For other types of signal than speech other standards are appropriate depending on the circumstances.

As has been mentioned, each first signal may represent a number indicating the said duration of a half cycle and each second signal may represent a number indicating a number of events, as hereinafter defined, occurring in a half cycle of the signal to be encoded.

In this specification an "event" which occurs in a said portion such as a half cycle of a signal to be encoded means any occurrence in such a sub-division which can be identified, for example a complex zero of a predetermined type or types, or a complex zero which can be identified by association with a minimum or a maximum or a point of inflection; or an "event" may even be the attainment by the signal to be encoded of a specified value. Complex zeros are discussed in Patent Application 791 0929.

For convenience in this specification and claims two types of maxima and minima are mentioned; firstly magnitude maxima and magnitude minima which refer to maxima and minima on the bsis of magnitude not polarity; and secondly polarity maxima and polarity minima which refer to value in the positive sense not magnitude.

In this specification and claims the term a "half cycle" of a signal means the interval between successive attainments by the signal of a predetermined datum value, the said value being a value attained by the signal from time to time and not necessarily being zero. The datum value is usually constant but may vary in a predetermined way.Where the datum is zero, or is offset to zero, the duration of a half cycle may be determined exactly by mesuring the interval between real zeros (RZ) in the signal to be encoded or it may be determined approximately by, for example, measuring the interval between the first polarity maximum in a positive half cycle and the first polarity minimum in the succeeding negative half cycle or vice versa, these maxima and minima being known as pseudo zeros (PZ); or by measuring the interval between zeros found by interpolation between the last polarity maximum in a positive half cycle and the first polarity minimum in the succeeding negative half cycle or vice versa, these zeros being known as interpolation zeros (IZ). Both pseudo and interpolation zeros are discussed below.Since according to the above definition polarity maximum and minimum here refer to the value of the signal in the positive sense, the first polarity minimum of a negative half cycle is the first magnitude maximum in that half cycle, that is magnitude disregarding polarity.

It will be clear from the above that in determining the lengths, shapes or number of events, a half cycle need not be determined between real zeros, but may for example be determined between corresponding points in successive portions of a signal waveform which occur between real zeros.

Further, it should be noted from the above definition of the term "half cycle" that where a signal is wholly positive or wholly negative with respect to the datum, that is it reaches but does not cross the datum, the half cycle extends between the signal reaching the datum and the next time the signal reaches the datum.

The methods and apparatus of the invention may be applied to any varying waveform but the invention is particularly advantageous in encoding electrical signals representing speech and other sound signals. Other examples of waveforms which can usefully be coded include sonar, radar, waveforms generated by remote sensors and by medical and other instrumentation transducers, where a simple code is useful in recognising the significance of a signal received.

The signal to be encoded may be derived from another signal, such as signal representing speech for example by single or multiple integration or differentiation.

In apparatus according to the first aspect of the invention the means for generating secondary signals may include reduction mapping logic means, such as a programmable read only memory (PROM) for translating symbols, the first and second signals, into a reduced number of secondary symbols. By using reduction mapping logic two reductions in the number of bits required for transmission can be made: Firstly, a number of primary symbols (first and second signals) having values which are adjacent may be grouped so that when applied to the mapping logic they generate the same secondary symbol. For example at the higher end of the speech frequency spectrum, three primary symbols represented by X, Y and Z may all be represented by a single secondary symbol Y'.At the lower end of the spectrum, where the durations of half cycles are long, larger groups of primary symbols may be represented by the same secondary symbol.

Secondly, since the input signals are bandwidth limited only a certain number of partial symbols representing durations of segments can occur. For example in speech waveforms, limited to between 300 Hz and 3 kHz with a certain sampling rate of say 20,000 samples per second, only half cycle durations longer than a certain number of quanta are likeiy to occur. The harmonic content of speech is well known and it is also found that those partial symbols representing the number of events are strictly limited (that is to those symbols corresponding to the predetermined set of second signals) and in addition each of these partial symbols only occurs with a certain limited number of partial symbols representing half cycle duration.

As a result it has been found that the mapping logic need only have 27 or fewer secondary symbols (these being described as an alphabet of symbols) which can each be represented by a 5 bit binary number when linearly encoded.

These remarks apply to speech in the English language but are believed to be true at least for other Western European languages. They may also be validsmore widely.

A further bandwidth reduction may be achieved by omitting some symbols using sequence reduction logic which omits symbols on a systematic basis by, for example, omitting every second symbol or every third symbol or every second and third symbol. Alternatively the sequence reduction logic may recognise all or some symbols and then omit one or more succeeding symbols in accordance with the symbol detected. The first of these alternatives does not detract from intelligibility on reconstruction provided, for example, at least one in three to one in eight of the original samples is retained but at the extreme reconstructed speech is "musical" in character if a repetitive reconstruction process is adopted. In the second alternative it is known that certain symbols occur in long sequences of repetitive clusters. If one of these symbols is transmitted and the next, for example, seven removed, then a more natural reconstruction is possible by reproducing the sequence of eight typical symbols from the cluster each time a symbol described above is detected.

The quality of waveforms reconstructed from signals encoded according to the method of the invention can be improved by including "envelope" information specifying amplitude, packing (that is waveform shape) or frequency ratio, for example. In one embodiment a symbol representing the amplitude of the signal to be encoded may be included at specified intervals in the encoded signal.

In apparatus according to the second aspect of the present invention the means for deriving pairs of first and second signals may comprise decode mapping logic, for example a PROM, which receives the secondary symbols and provides output signals at first and second output channels representative of first and second signals. The decode mapping logic may also have channels which provide a signal specifying silence, and/or envelope information such as amplitude or packing or frequency ratio information if such information is incorporated in the encoded signal.

Where symbols were omitted in encoding the apparatus according to the second aspect of the invention may include, optionally as part of the reconstruction logic, sequence insertion logic.

The insertion logic carries out the inverse of the reduction logic, for example by inserting half cycles having the same waveform as the preceding half cycle if symbols were removed on a systematic linear basis. Instead, where symbols were removed according to a symbol detected, then the insertion logic is constructed to generate half cycles according to the symbols which were removed so that the original long sequence of symbols is reconstructed on the detection of the first symbol of the sequence.

Computers, including microcomputers and microprocessors, may be employed in putting the methods and various forms of apparatus of the invention into practice. Thus some or all the method steps may be carried out using a computer and all or part of such apparatus may be formed by a computer.

Where digital computers are used analogue-to-digital converters and digital-to-analogue converters are also usually required.

Certain embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram including apparatus according to the first aspect of the invention, for encoding speech signals, Figures 2 and 3 are waveforms used in explaining the operation of the apparatus of Figure 1, Figure 4 is a block circuit diagram including apparatus according to the second aspect of the invention for reconstructing speech waveforms from code symbols generated by the apparatus of Figure 1, Figures 5 and 6 are waveforms used in explaining the operation of Figure 4, Figure 7 is a block diagram of part of an encoder including apparatus according to the first aspect of the invention, Figures 8(a) to 8(h) show waveforms used in explaining the operation of Figure 7, Figure 9 is a block diagram of part of a decoder including apparatus according to the second aspect of the invention, Figure 10 shows a waveform used in explaining the operation of Figure 9, Figure 11 shows an example of the envelope logic 14 of Figure 1, Figure 1 2 shows an example of a stuffing circuit which may be used for the circuit 1 7 of Figure 1, and Figure 1 3 is a block diagram of a radio link between the apparatus of Figure 1 and that of Figure 4.

In Figures 1, 4, 7, 9, 11, 12 and 13 a single line between blocks may either be a single connection, or channel, or a group of connections or channels.

In Figure 1 an audio signal, for example from an amplifier coupled to the output of a microphone, is passed to a preprocessing circuit 10 where the signal may be band-pass filtered, and subjected to constant volume amplification so that small but significant fluctuations are amplified to a suitable level for subsequent circuits. Constant volume amplification is important where the input signal has a wide dynamic range. In the preprocessing circuit 10 the input signal may also for example be differentiated or integrated according to noise conditions, low frequency noise being reduced by differentiation and high frequency noise by integration. In addition a d.c. signal may be added for the purpose of eliminating, as is explained below, the large number of zero crossings which occur when noise appears in periods of silence.In addition the preprocessing circuit may carry out one or more of the following known processes:-- syllabic companding, spectral shaping, frequency shifting and spectral inversion.

The output signal from the preprocessor 10 is passed to an A/D converter 11 which may for example be a conventional pulse code modulation (PCM) encoder and which is driven by a clock pulse generator 21 to take, for 3 KHz speech bandwidth for example, about 20,000 samples per second, each sample being encoded as a 10 bit number.

The A/D converter 11 is in general driven by a clock pulse generator 21 having a rate several times faster than the Nyquist sampling rate, a factor of two to ten times the Nyquist rate being typical. In this way, the highest frequencies will be coded by two to ten samples respectively, ensuring that no significant required contributions of the input waveform are lost. Since the durations of half cycles are measured by the number of operations or samples from the A/D converter, each time quantum in which such durations are measured occurs several times in a half cycle. Thus for 20,000 samples per second each quantum equals 1/20,000th of a second.

The output from the A/D converter 11 is passed to three logic circuits: a zero logic circuit 12, an event logic circuit 1 3 and an envelope logic circuit 14.

If the zero logic is to determine the intervals between real zeros then a counter may be used to count clock pulses and this counter may be caused to read out and be reset to zero each time the polarity bit from the ND converter changes sign. Thus the first signals mentioned above are derived. More details of the zero logic are given below in connection with Figure 7.

As has been mentioned, under certain conditions, it is useful to be able to determine the duration of half cycles by measuring the time interval between IZs or PZs. For this reason the zero logic 12 may also determine when such zeros occur. Interpolated zeros are obtained by interpolation between the last polarity maximum before an RZ zero and the first polarity minimum (i.e. the first magnitude maximum disregarding polarity) after the RZ The differences between the three types of zeros will now be exemplified with reference to Figure 2 which shows an arbitrary waveform intended to represent a speech waveform after any preprocessing which may have taken place in the preprocessor 10 but before analogue to digital conversion.RZs in this waveform are of course the points 22 and PZs are represented by the points 23 and it can be seen that very approximately the intervals between successive points 23 are equal to intervals between successive points 22. One type of IZ is illustrated at point 24 and it is found by constructing a mathematical model in the IZ/PC logic of a straight line between the last polarity maximum 25 before a real zero and the first polarity minimum 23 after a real zero. The point where the straight line cuts the time axis is one type of interpolation zero.

The event logic 1 3 identifies and counts the number of magnitude maxima and/6r magnitude minima in one half cycle. If the number of magnitude minima only is required the logic 1 3 may subtract one from a count of magnitude maxima and minima and then divide by two. Alternatively the event may count magnitude minima directly. Thus the second signals mentioned above are derived.

When a magnitude maximum or minimum occurs, successive samples in the neighbourhood may be greater than or smaller than the previous sample due to the effect of noise or to uncertainty in digitising the samples. For this reason the logic circuit 13 includes fluctuation logic which determines when a magnitude maximum or minimum has really occurred. More details of the event logic are also given below in connection with Figure 7.

The envelope logic circuit 14 may derive signals containing amplitude information and packing or frequency ratio information. To obtain amplitude information the envelope logic computes the average of the peak values of the input waveform over a number of successive time coded samples. Dependent upon the application this may be averaged over as many as 20-30 time coded samples, or as few as one or two time coded samples.

The envelope logic may also compute and code information regarding the way in which the CPZs are packed within the RZ time interval. This facilitates more effective reconstruction at the receiver. This information may only be required for certain symbols or groups of symbols. As an example of the utility of packing, a long RZ interval with only two DCPZs can be more realistically reconstructed if the transmitted code indicates that the two DCPZs are packed closely together or that they are widely spaced.

Signals from the zero logic circuit 12 and the event logic 1 3 are applied to a map and code logic circuit 15 which may for example be a programmed read only memory (PROM). The circuit 1 5 substitutes numbers representing the secondary symbols of an alphabet for each pair of numbers or primary symbols generated in the logic circuits 12 and 13. As has already been mentioned the number of primary symbols which can be generated is limited if the output signal from the preprocessing circuit 10 is band limited for example to signals between 300 Hz and 3 KHz. Furthermore primary symbols can be grouped and the symbols of each group can be represented by the same secondary symbol, the groups being selected on a non-linear basis. The constitution of such groups has already been discussed and it has been stated that in this way the secondary symbols in the alphabet at the output of the circuit 31 can easily be reduced to 27 without significant loss of intelligibility on decoding. An example of input combinations and output symbols is given in Table 1.

TABLE 1

Length of Number of Magnitude Minima half cycle (in time quanta) 0 1 2 3 4 5 1) 2) 3) 1 4) 2 5) 3 6) 4 7) 8) 9) 5:: 10) 6 11) 16) 9 17) 10 11 18) 19) 20) 21) 12 13 22) 14 23) 15 24) 25) 26) 27) 16 17 28) 18 19 29) 20 30) TABLE 1 (Continued)

Length of = Number of Magnitude Minima half cycle (in time quanta) 0 1 2 3 4 5 31) 32) 33) 21 22 34) 23 24 25 35) 36) 37) 26 38) 39) 40) The first column gives the length of each half cycle and brackets indicate the lengths which are grouped and coded using the same symbol. Each of the other columns is headed with a number of magnitude minima and contains a number representing one character in the alphabet of secondary symbols. For example, a half cycle of duration 22 quanta and one magnitude minima is coded 1 3 as is one of duration 1 9 quanta with one magnitude minima. In Table I the above mentioned predetermined set of second signals is represented by the six numbers 0 to 5 at the heads of the columns (except the first column).

It will be clear to those familiar with entering look-up tables into PROMs how to enter Table I into a PROM. Suitable PROMs for the circuit 1 5 and the other PROMs mentioned in this specification include the INTEL types 2704 and 8704 which are 512 x 8 bit PROMs. The use of these devices is fully described in the manufacturefs data. In general a PROM receives an x bit address and can be programmed to provide a y bit output, and input and/or output may be parallel or series. The devices specifically mentioned above employ a nine bit address and provide an eight bit output. In effect each combination of a number in the first column of Table I with a number in the row representing magnitude minima is a possible input signal to the PROM which must be catered for at the input side of the PROM in binary form.Thus the PROM is programmed to give an output symbol (in binary form) for each possible input signal, the symbols being those of the alphabet of Table I. Where spaces occur in the table a symbol cannot occur, due to band limiting but the PROM is nevertheless programmed with the symbol to the left of the space in case due to erroneous working such an input combination does occur; for example a half cycle of duration nine quanta with two or more minima is coded 6. Silence is coded as symbol 27 (not shown in Table I) and whenever a "half cycle" of duration 41 to, say, 64 time quanta occurs it is coded as symbol 27. For durations longer than 64 quanta counting is in 64 time quanta units as is explained in connection with Figure 7.

The waveform of Figure 3 represents a speech waveform but it includes an interval 26 of silence in which a noise signal occurs.

Since the noise signal has many zero crossings it would cause counts to be generated in the counters of the zero and event logic circuits 12 and 13 which would give rise to misleading encoded signals. The horizontal axis 27 in Figure 3 relates to the waveform at the input of the preprocessor 10 but the chain dotted horizontal axis 28 relates to the same waveform after the addition of a d.c. signal in the preprocessor 10. It will be seen that no zero crossings occur in the interval 26 in the output signal from the preprocessor 10. Thus if the counter of the zero logic circuit 12 measures an interval of greater than a predetermined duration it is an indication that an interval of silence has occurred.

Quite a high proportion of secondary symbols may be omitted before transmission without significant loss of intelligibility on decoding. This technique has also been mentioned above where both the omission of fairly large groups of symbols representing short half cycles and perhaps every other symbol representing a long half cycle and have been discussed. In Figure 1 sequence reduction logic 1 6 is provided to omit secondary symbols on the basis of Table II, for example.

TABLE II

Secondary Symbol Divide by 1) 2) 10 3) 4) 5) 6) 6 7) 8) 9) 10) 11) 3 12) 13) 14) 15) 16) to 2 40) For instance using Table II where secondary symbol 5 occurs only every sixth symbol is passed to the next circuit. The sequence reduction logic 1 6 may comprise a first-in first-out (FIFO) store (not shown in Figure 1) comprising a series of registers.A number read into the store is transferred in parallel from register to register when clock pulses are received and also read out in this way. If the circuit receiving numbers read out is activated to a read mode only every sixth of those pulses applied to the FIFO store then five symbols are omitted.

The sequence logic 1 6 may alternatively be implemented using a PROM (not shown) as address signals and is programmed to provide the numbers shown in the right hand column of Table II. These numbers are read into a counter (not shown) which is decremented each time the MSB signal from the A/D converter 11 changes sign. The counter is connected to a gated buffer circuit (not shown) positioned as part of the logic circuit 1 6 between the output of the circuit 1 5 and the input of the circuit 20. Each time the counter reaches zero the gated buffer is enabled allowing one symbol to reach the circuit 1 7 and the PROM is enabled to receive another symbol from the circuit 1 5.

After sequence reduction the secondary symbols are passed to a stuffing/mapping logic circuit 1 7 where the amplitude information from the logic 14 is "stuffed" into the symbol stream or mapped into the code. in the former process after every pth symbol, a symbol representative of peak average amplitude at that time is inserted, where p may for example be in the range 1 to 20 and is typically 8. In the latter process if the original time coded alphabet consists of the 26 symbols 1 to 26 then symbols 27 to 52 may for example be utilised for amplitudes between zero and a first level, symbols 53 to 79 for amplitudes between the first and a second level and so on. It should be noted that for some applications, the transmission/stuffing/mapping of envelope information may be restricted to low amplitude symbols only, or to other special groups of symbols.

As has been mentioned, the envelope logic 14 may also include circuits for providing a packing signal indicating the way in which events are packed into, or distributed in, each half cycle. For example the position of each maximum and minimum in terms of the number of time quanta from the beginning of a half cycle may be stored and signals representing some or all of these signals may be mapped, or possibly stuffed, into the stream of signals from the sequence logic circuit 1 6. A five-bit code allows thirty-two symbols to be transmitted, and thus if twenty-six or twenty-seven symbols are used as secondary symbols five or six symbols may be used for packing information, assuming amplitude information is stuffed not mapped.For selected symbols representing, for example, long half cycles with few minima one of two symbols is derived from the positions of minima. This scheme allows five or six of the symbols in bottom left corner Table I to be duplicated to represent different packing and then selected on the basis of the packing detected in the signal received. Packing information may either be mapped using a PROM employed for the circuit 1 5 or a further PROM may be positioned somewhere in the series of circuits between the circuit 1 5 and the circuit 20. Some further information on deriving packing information is given later in relation to Figure 7.

While the symbols from the logic circuit 1 7 may be transmitted at regular intervals by way of a buffer store 1 9 under the control of a transmitter clock pulse generator 18, as 5 bit numbers, for example, a further reduction in bit rate and therefore bandwidth may be achieved by the use of Entropy codes as codes mentioned above, such as "Huffman" codes. For example with multiple bit PCM the symbols used in the code may be positive or negative and each may have two states such as two levels. Each symbol then begins with a positive or negative signal having a magnitude of two units which is then followed in some cases by a further one or more positive or negative one unit signals.The most used symbols are the shortest and comprise simply one of the positive and negative two unit signals, the next most frequently used signals comprise a two unit signal (positive or negative), and so on.

Such output symbols may be generated by a transmission code logic circuit 20 comprising a further PROM (not shown) and then passed to the buffer store 1 9.

Signals arrive at the buffer store 1 9 at an irregular rate for various reasons including the use of symbols of similar length for half cycles of differing lengths, the use of the sequence and stuffing/mapping logic and the use of the circuit 20. A radio transmitter 30 (see Figure 13) for example or a land line need to be regularly loaded and this aim is achieved by the buffer store 1 9 whose output is clocked regularly from stored signals sufficient to even out signals for transmission.

For decoding after transmission by way of for example a radio or telephone line link the encoded signals may be applied to the arrangement shown in Figure 4. A buffer store 40 receives signals for example from the transmitter 30 (Figure 3) by way of a receiver 31 which, where Entropy codes are used is preceded by a decoder (not shown), which converts the Entropy code symbols into digital signals. Signals received by the buffer store 40 are read out sequentially without discontinuity under the control of an input clock pulse generator 41. The store 40 may be a conventional FIFO store or a set of FIFO stores.Signals from the store 40 are applied to a decode logic circuit 42 where the inverse of the operations carried out by the map and code logic circuit 31 and the stuff/map logic circuit 1 2 of Figure 1 are carried out for example by applying digital signals representing secondary symbols to a PROM which then provides as its output, signals in four channels 43 to 46 representing the duration of each half cycle, the number of minima occurring in each half cycle, each amplitude signal which was coded, and a packing signal specifying the way in which the signal is to be reconstructed, respectively.

Basically the PROM is programmed so that for example when one of the secondary symbols shown in the columns of Table I (other than the first column) is received a primary symbol in two parts is generated at the PROM output. The first part is a number representing the number in the first column opposite the symbol, and the second part is a number representing the number of minima at the head of the column containing the symbol. Note that where a secondary symbol was generated from any of a number of time quanta in a group, only a particular number of time quanta is regenerated from the symbol. This number is different, in some cases, for different numbers of minima for symbols derived from the same group.For example the secondary symbol 9 causes the regeneration of a first part of a primary symbol representing 1 6, since in Table I the symbol 9 is opposite 1 6, but the symbol 10, generated from the same group of time quanta 14 to 18, causes the regeneration of a first part of a primary symbol representing 1 7.

The symbol 27 is decoded as a primary symbol having a first part of 50 and a second part as zero.

The programming of the PROM in the logic circuit 42 will now be clear from Table I but is should be noted that where amplitude is to be recovered also, Table I may be extended to form several fields each as shown in Table I but each corresponding to a separate amplitude as illustrated in Table Ill::- TABLE Ill

TABLE I 1st AMP symbols 1 to 26 RANGE As TABLE I, but 2nd AMP symbols 28 to 54 RANGE As TABLE I, but 3rd AMP symbols 55 to 81 RANGE Each received signal as mentioned above is coded 1 to 26, 28 to 54, or 55 to 81 corresponding to the three sections df Table Ill and assuming that symbol 27 is reserved to denote silence, so that if for example symbol 28 is received, it is decoded by the PROM as 3 quanta of duration, zero magnitude minima, and within the second amplitude range.

Packing information, mentioned above, and dealing with the way CPZs are packed within half cycles is dealt with in a similar way to amplitude information.

Alternatively, if amplitude and/or packing information is in the form of extra symbols "stuffed" into the bit stream received by the decode logic 42, a FIFO store, appropriately clocked, may be used to read the additional symbols into the channel 46.

The channels 43 to 46 are applied to a reconstruction circuit 47 which may also comprise a PROM.

In its simplest form the waveform reconstructed has a rectangular envelope as shown in Figure 5.

If each symbol received by the reconstruction logic comprises a number A representing the length of a half cycle and a number B representing the number of magnitude minima in that half cycle then the reconstruction circuit 47 first derives M and N according to the following equations A M=2B+ 1 and N = (2B + 1) The reconstruction circuit is then designed to provide N pulses at a fixed amplitude followed by N pulses at half the fixed amplitude followed by N pulses at the fixed amplitude and so on until M groups of N pulses have been generated. For example with reference to Figure 5 if A = 12 and B = 1 then the circuit 47 provides internally the numbers N = 4 and M = 3. The internal generator accordingly generates a block of four full amplitude pulses 48, a block of four half amplitude pulses 49 and then a block of four amplitude pulses 50.By this time the process of producing pulses has been carried out three times and a waveform half cycle has been generated. If the next symbol received by the circuit 47 has A = 5 B = 2 then the resulting waveform is as shown at 51 in Figure 5.

For silence A=64 B=O, so a full height pulse, typically of many periods of 64 time quanta is produced. A fixed voltage of this type produces a period of silence.

With this simple reconstruction strategy, the ratio of maximum to minimum value of the reconstructed waveform is fixed at 2:1 and the time intervals between discontinuities in each half cycle are evenly spaced. However, any other suitable fixed ratio and/or interval may be used dependent on the characteristics of the signal being processed.

This simple, evenly spaced, rectangular waveform is highly intelligible but is clearly non-optimum and some of the factors which can advantageously be taken into account in devising other reconstruction strategies have already been mentioned.

However another strategy will be illustrated here with the aid of Figure 6. When PZ coding is used then the last time interval of the reconstructed signal may be extended at the expense of the preceding ones to give improved quality. Thus if A = 1 2 and B = 1 the reconstructed waveform may have a block of four full-height pulses followed by a block of three half height pulses followed by a block of five full height pulses as shown in Figure 6.

Where a PROM is used in generating rectangular waveforms such as those shown in Figures 5 and 6, the symbol represented by the numbers A and B is presented to the PROM and the resultant mapped output is unique for that symbol. It may consist of a series of bits, appearing at different PROM output terminals in parallel, each corresponding to a pulse and specifying whether that pulse is to be full height or half height, for example by taking the values "one" and "zero", respectively. These bits are then passed to pulse generating circuit (not shown) for generating equal length pulses each of one of the required two amplitudes.

However a smoothed version of the rectangular waveform may be produced by grouping the output bits from the PROM as words having, for example, four bits in each word specifying the amplitude of a pulse to be generated. Such a bit stream is then passed to a digital-to-analogue converter to generate the required waveform and quantisation noise can be removed from the waveform by a linear low pass filter.

An alternative way of deriving a smoothed form of the rectangular waveform is to use a pair of commercially available dynamic filters each of which receives the rectangular waveform and whose outputs are summed. One of the dynamic filters which is a band-pass filter passes the high frequencies corresponding to the maxima and minima, and the other dynamic filter which is a low-pass filter passes only the low frequencies corresponding to half cycle duration. The outputs from the filters are added and a smoothed waveform is generated.

In order to ensure that the reconstruction circuit 47 always generates an appropriate output, a signal indicative of the number of symbols held by the store 40 is passed to the circuit 47 by way of a channel 53. In this way slight variations in the clock rate from a clock 54 controlling the logic 47 can be made, if required, to spread out symbols and lose time if the buffer store 40 is nearly empty or to squeeze up symbols and gain time if the store 40 is nearly full. In this way at least a partial correction is made in irregularities in the rate at which signals pass between the buffer store 40 and the output of the logic 47.

Gross variations in the reconstruction clock rate from the generator 54 will alter the spectral occupancy of the output signal. For some applications the reconstruction clock rate will not be the same as the quantisation clock rate. In the processing of helium speech for instance the difference may be a factor of four or five times.

Where symbols have been omitted before a transmission using sequence reduction logic sequence insertion logic 56 is used to re-introduce symbols. If the logic 56 includes a FIFO store and for example all symbols were reduced by a factor of three before transmission, the FIFO store may be clocked three times each time one symbol is in the output register so that this symbol is readout three times. Where long groups of symbols representing short half cycles were omitted another PROM may be used to generate a typical group of such symbols each time one such symbol is applied to the input of the PROM. For example the PROM may receive signals at its address terminals and be programmed to generate an appropriate output number depending on the symbol which can then be used to clock the FIFO and provide a number of symbols equal to the number read out from the PROM.

The sequence logic 56 also allows symbols to be repeated, or withheld dependent upon the size of the buffer store 40 and its symbol occupancy. Thus if the buffer store is nearly empty, the sequence logic may repeat successive samples more often than otherwise required, to prevent the buffer store emptying further. Similarly if the buffer store is rapidly filling up, the logic may repeat successive samples less often than otherwise, or even suppress samples to prevent the buffer store overflowing.

This latter strategy may be used to reduce the size of buffer store needed and to prevent discontinuities or gaps occurring in the symbol stream.

The waveform generated by the reconstruction logic 47 is passed to a processing circuit 55 which may be the inverse of the preprocessing circuit 10 and therefore may subtract a d.c. signal and/or integrate or differentiate the waveform received to provide the final output waveform. Low-pass or band-pass filtering and spectral shaping or inversion may also be carried out together with expanding, or any inverse amplitude processing required as a result of the preprocessing adopted. Post processing may also include dynamic filtering as described above in connection with waveform reconstruction if not inciuded in the logic circuit 47.

One embodiment of an encoder according to the invention will now be described in more detail with reference to Figure 7. The zero logic 12 and the event logic 13 of Figure 1 is shown in more detail in Figure 7 where the A/D converter 11 and a PROM 15' used as the circuit 1 5 are also shown.

That output of the A/D converter 11 which signals that the converter is ready for read-out is applied to a dual monostable circuit 60, that is two monostable circuits in series, one providing a delay and one providing pulses. The pulses are passed to the converter 11 by way of a connection 58 to cause the next sample to be read out, the delay being chosen so that read-out is at the appropriate time. The pulses are a suitable le igth for a counter 61. Each count reached by the counter 61 is proportional to the length of a half cycle of the signal applied to the A/D converter 11 since the counter is reset at the end of each half cycle in the way which will now be explained. The most significant bit (MSB), that is the sign bit, from the A/D converter 11 is applied to a differentiator 62 so that each edge of the MSB waveform produces a pulse.A monostable circuit 63 changes this pulse into a pulse of predetermined duration (see Figure 8(c)) which is applied to a further differentiator 64. The negative going output of the differentiator 64 (Figure 8(d)) resets the counter 61 immediately after the end of each half cycle.

As has been mentioned silence periods are counted in 64 time-quanta units, each such unit producing the symbol 27 at the output of the PROM 1 5'. For this purpose the "carry" instruction from the counter 61 which can hold a maximum count of 64 is passed by way of a connection 59 to "enable" the PROM15' before the counter returns to zero. This process is repeated until the next RZ, IZ or PZ is detected. Additional or alternative logic may be employed to enable groups of 64 quanta or numbers other than 64 to be selected for representation by the symbol 27 or another "non speech" symbol such as 28 or 29.

The output from the A/D converter 11 is passed to a register 65 under the control of the clock pulse generator 21 each time the A/D converter is ready for read-out as signalled by the dual monostable 60 along line 58 and the current contents of the register 65 are passed on to a register 67 at the same time.

Thus a comparator 68 is able to compare the current and previous output from the A/D converter in order to determine whether a maximum or minimum has occurred. The output from the comparator 68 is passed by way of a gated buffer circuit 70 to a bistable circuit 71, the object of the gated buffer being to prevent minor fluctuations in level, due to last bit uncertainty or noise, being treated as a genuine maximum or minimum. The control of this buffer is explained below.

Provided the gated buffer 70 is open the bistable circuit 71 changes state each time the current sample is greater than the previous sample or vice versa. For example Figure 8(a) shows a waveform applied to the input of the A/D converter 11 and the waveform of Figure 8(e) shows how the bistable circuit 71 changes state to conform to this waveform. An EX-NOR gate 72 receives one input from the bistable circuit 71, and one from the MSB output of the A/D converter 11 so that its output is as shown in Figure 8(f).It will be seen that the arrowed edges of the exclusive NOR output of Figure 8(f) are equivalent to the number of polarity minima in each positive half cycle and polarity maxima in each negative half cycle of the waveform of Figure 8(a) and this number is counted by a counter 73, the edges designated 57 being gated out by a gate 69 controlled by the output of the monostable 63. This counter is reset each time the differentiator 64 provides a reset pulse (see Figure 8(d)).

The arrangement of Figure 7 allows PZs to be used instead of RZs by taking the output of the EX-NOR gate 72 and applying it to an R/S flip-flop circuit 74 which is reset by the signal from the differentiator 64 and has an output waveform as shown in Figure 8(g). The output from the latch circuit 74 is passed to a bistable circuit 75 which it will be seen from Figure 8(h) changes state each time the first polarity maxima occurs in a positive half cycle and the first polarity minima in a negative half cycle; that is the waveform of Figure 8(h) changes state at every pseudo zero.The output from the bistable circuit 75 is treated in the same way as the most significant bit from the A/D converter 11 to provide an alternative input for the counter 61 and a PROM enable signal for the PROM 1 5' by the use of semiconductor switches 76 and 77, differentiators 78 and 79 and a monostable circuit 80.

The outputs from the counters 61 and 73 are applied to the PROM 15' when the PROM enable signal is received by way of the switch 76; and the PROM output is taken to the sequence logic 16 as shown in Figure 1. Signals to and from the PROM 15' may be transferred either as serial pulses in a single channel, or as parallel pulses in parallel channels.

One example of the fluctuation logic controlling the gated buffer circuit 70 will now be described.

A number, for example four, of the least significant bits in the registers 65 and 76 are passed to a different circuit 82 which provides an output proportional to the difference between the applied signals These differences are summed in an up/down counter 83 so that where fluctuation occurs the sum contained by the counter 83 increases and decreases. However if the sum accumulated becomes greater than a predetermined reference value which is proportional to the fluctuation error allowed, then a comparator 84 provides an output for a bistable circuit 85 which opens the gated buffer circuit 70. At the same time the sum circuit 83 is reset.

By varying the reference value allowances can be made for differing expected errors in the comparator 68 and for differing noise levels.

An example of the envelope logic 14 is now described in more detail with reference to Figure 11.

Samples from the A/D converter 11 are passed first to a register 1 35 and then to a register 1 36. A comparator 137 compares the sample in the register 136 with that in the register 135 and if the former is larger than the latter an enable signal is sent via a connection 138 causing the sample in the register 136 to be passed to a register 139.

The MSB signal from the A/D converter 11 is passed as an enabling signal to the register 1 39 to cause it to pass its contents to an adder 140 each time a half cycle ends. Thus at the end of each half cycle the register 139 contains the sample having the largest amplitude in that half cycle and this sample is added to the contents of the adder 140.

The MSB signal is also passed to a frequency divider 141 which provides a read-out signal for the adder 1 40 after the MSB signal has changed R times, where R is the number of samples over which the average is to be taken. The contents of the adder 40 are divided by R in a divider circuit 1 42 to provide the average maximum half cycle amplitude before being passed to a PROM 143. The programming of the PROM is such that-it provides a look-up table in which each amplitude average gives rise to a digital signal or symbol ready for stuffing or mapping in circuit 1 7. The registers 65 and 67 and the comparator 68 of Figure 1 may be used instead of the additional registers 135 and 136, and the comparator 137.

The stuffing/mapping logic circuit may be a PROM when mapping is to be carried out, and if so then part of each address supplied to the PROM comes from the sequence logic 1 6 while the remainder comes from the PROM 143 of Figure 11. The mapping PROM is programmed to provide, according to applied address signals, output symbols which may for example be as indicated in the first column of Table Ill above.

For stuffing the arrangement shown in Figure 12 may be used. Gated buffer circuits 1 45 and 146 are connected to receive signals from the map and code logic circuit 1 5 and the envelope logic circuit 14, respectively, of Figure 1 and their outputs are both connected to the transmission code logic circuit 20. The MSB signal from the A/D converter 11 is applied by way of a NAND gate 147 to allow signals to be gated from the buffer circuit 145 to the circuit 20 each time the MSB signal changes, except when a signal from a divide-by-eight circuit 148 is applied to the NAND gate. The divide circuit 148 also receives the MSB signal but only provides an output signal for every eighth change of the MSB signal.

The buffer circuit 146 is enabled by signals from the divide circuit 148 so that on each eighth MSB change a signal from the envelope logic is passed to the transmission logic 20 but at this time the NAND gate 147 is closed and no signal is read from the buffer 145. Since signals from the circuit 1 6 are held by the buffer 145 for a long time compared with the time the NAND gate 147 is closed, all signals from the circuit 1 6 reach the circuit 20; further signals from the envelope logic 14 are simply injected between signals from the circuit 1 6.

The registers 65 and 67 and the comparator 68 may also be used to derive packing information.

Further counters (not shown), one for, and associated with, each of the five possible minima of Table I, are then provided and each counts pulses from the dual monostable circuit 60 until its associated minima is detected. Thus each counter holds a number representing the time between the beginning of a half cycle and the occurrence of a minimum. When intervals between minima are required the contents of different counters are subtracted. One or more divider circuits (not shown) are used to divide the contents of the counter 61 at the end of each half cycle by the contents of the said further counters, to provide a ratio which may, for example be simply classified as greater or smaller than four. The former indicates that minima are relatively close together and the latter that they are relatively widely spaced.

Thus a binary signal is provided which indicates one of these possibilities and is suitable for application to one of the PROMs already mentioned in connection with packing.

An example of the reconstruction logic 47 in Figure 4 is now described in more detail with reference to Figure 9.

Signals from the buffer store 40 are applied to a PROM 87 forming the decode logic 42 shown in Figure 4. However in the system described in relation to Figure 9 the output of the PROM while comprising the length of half cycle signal A in channel 43 and the number of minima B in channel 44, also contains packing information in channel 88 and averaged amplitude information in channel 89. A logic circuit 91 which may be a PROM generates the two numbers M and N already referred to in connection with Figure 5. Numbers P, and P2 mentioned below are also generated from information in the channel 88. These numbers are read out in channels 92 to 95, respectively. Alternatively the outputs of the PROM 87 generate the numbers M, N, P1 and P2 directly through the PROM program and the logic circuit 91 is omitted.The possible outputs from the PROM 87 can be regarded as defining a set of possible shapes for half cycles of analogue signals generated by the apparatus of Figure 9. From the number M, N, P, and P2 a waveform similar to that shown in Figure 5 can be built up but the packing information allows modification by the addition of a number of full height preload pulses at the beginning of each half cycle and another number of full height post load pulses at the end of each half cycle.

For example a half cycle such as that shown in Figure 10 might be specified for reconstruction by a predetermined preload signal P, = 1, M = 3, N = 4, and a postload signal P2 = 2, in which case, as shown in Figure 10, there would be a first single full height pulse 150 corresponding to P, = 1, three groups of pulses 151 corresponding to M = 3, four pulses in each group corresponding to N = 4 and two full height pulses at the end 1 52 corresponding to P2 = 2. The packing may be similar for each half cycle or it may vary either with A and B or with an envelope signal sent from the encoder either as a separate signal or as part of the alphabet of transmitted symbols.

The information in the channels 92 to 95, where logic circuit 91 is employed, is passed to a FIFO store 96 where it is read out to counters 97, 98 and 99 and a shift register 100. The counter 97 receives the preload information P. The number representing this information is counted down to zero by means of the reconstruction clock 54 which passes pulses by way of a multiplexer 1 02 which is under the control of a counter 103.

While the counter 97 is being counted down to zero, a bistable circuit 104 applies an input to an amplifier circuit 105 comprising two summing amplifiers in series. The bistable 104 is connected to the second summing amplifier which also receives an input from the first summing amplifier. The polarity of this latter input is under the control of a bistable circuit 11 8. The phases of the output signals of the two bistable circuits are such that the output of the amplifier circuit 105 is maximum positive until the counter 97 reaches zero.An AND gate 106 then passes a signal by way of an OR gate 107 to the counter 103 which then causes the multiplexer 102 to start passing clock pulses to a counter 108 which has received the number N from the register 1 00. As the counter 108 is counted down to zero the amplifier 105 continues to provide its maximum positive output. However when the counter 108 reaches zero an AND gate 109 is opened and the bistable circuit 104 is set to its other state so that the output of the amplifier 1 05 is now at reduced positive level. If the pulses of Figure 10 correspond to the clock pulses of the reconstruction clock 54 it will be seen that pulses corresponding to the preload information P, and the first group of N pulses have now been generated at the output of the amplifier circuit 105.

The output from the gate 109 causes a monostable circuit 112 to provide an output signal for OR gates 113 and 114 resetting the counter 108 and reading the same number N into the counter 108 from the shift register 1 00. In addition the output pulse from the gate 109 decrements counter 98 to which the number M has been transferred.

The cycle of reading the counter 108 down is now repeated until the gate 109 again indicates that the counter is empty when the bistable 104 changes it state again so that the output of the amplifier 105 returns to the maximum positive level and the counter 98 is counted down by one more step. In this way it can be seen that a number of blocks of pulses N of alternate maximum and reduced amplitude are generated at the output of the amplifier 1 05 but when the counter 98 reaches zero as indicated by the output of an AND gate 11 5 an enable signal is applied to an AND gate 11 6. After the counter 108 is counted down again to zero the signal from the output of the gate 109 opens and the AND gate 11 6 which moves the multiplexer 102 on one more stage by way of the OR gate 107 and the multiplexer control counter 103.Clock pulses are now routed to the counter 99 which has received the postload number P2. While the counter 99 is counted down the amplifier 105 provides its maximum positive output but when a gate 11 7 indicates that the counter 99 is empty the counter 103 is reset to zero and the bistable circuit 11 8 is operated to change the level of an input signal to the first summing amplifier in the amplifier circuit 105. This first summing amplifier receives a positive going square wave from the bistable 11 8 and a negative offset voltage, of relative levels such that when the bsitable 11 8 changes state, the output of the first summing amplifier changes polarity. Thus the output of the amplifier circuit 105 also changes polarity.The relative levels of the input signals to the second summing amplifier are such that the maximum positive and negative excursions are equal as are the reduced level positive and negative excursions.

In order to reset the circuit for the reconstruction of the next half cycle the output from the gate 117 changes the state of a bistable circuit 120 applying an enable signal to an AND gate 121. As soon as the FIFO 96 is ready for read-out an enable signal is applied to an AND gate 122 which opens at the next clock pulse opening the AND gate 121 and applying enable signals to the AND gates 123 and 124.

When a read signal is applied to the AND gate 123 a monostable circuit 85 provides a pulse which presets the counters 97 to 99 and 108. When a write pulse is applied to the AND gate 124 a monostable circuit 126 receives an input pulse by way of an OR gate 127 and the FIFO 96 is caused to read-out into the counters 97 to 99 and the register 100. At the same time the bistable circuit 120 is set to its other state in which the AND gate 121 is not enabled. Thus it can be seen that the reconstruction logic 47 is now set up to provide the next half cycle with the opposite polarity to that of the preceding half cycle.

The amplitude information read out from the PROM 87 in channel 89 is passed to register 1 53 and thence after conversion in a digital-to-analogue converter 1 54 to the control input of an amplifier 1 55 having a variable gain controlled by signals applied to its control input. Thus an amplitude in accordance with the amplitude information is imparted to the signal from the amplifier circuit 105.

Where following the omission of symbols during encoding, it is required to insert symbols during decoding the read input to the gate 1 23 can be enabled after each half cycle of reconstruction to read the same information from the FIFO 96 as was previously read. In this way one symbol can be repeated several times. By enabling the dump terminal of the OR gate 127, symbols read into the FIFO 96 can be dumped and therefore omitted. This is a facility which is useful in the reconstruction of helium speech where the FIFO 96 wuld be coupled direct to the counters 61 and 73 of Figure 7.

It will be apparent that the invention may be put into effect in many other ways from those specifically described. For example the circuits and logic specifically mentioned may be replaced by alternatives and the system may be redesigned, for example, following the many different criteria discussed in the specification. For example the circuits and logic may be replaced in whole or in part by computer, but where digital computers are used analogue-to-digital converters may be required for input signals and digital-to-analogue converters may be required to provide output signals. Thus the whole of Figure 1 ,for example, to the right of the A/D converter may be replaced by a computor comprising a microprocessor, and the whole of Figure 4 at least to the left of the circuit 55 may be replaced by a similar type of computer with the addition of a D/A converter.The programming and assembly of such computers will be apparent to those skilled in the microprocessor art from the above description and drawings, Figures 1 and 4 being easily changed into appropriate' flow charts. Where encoding and decoding at the same location, for example for dealing with helium speech, or decoding from stored symbols is carried out, a single computer, for instance of the type outlined, may be used. Thus the five aspects of the invention as covered by the claims below include methods and apparatus comprising computers.

Coding and decoding will be different according to the application for which the invention is used.

In processing helium speech for example there is no requirement to economise in bandwidth and usually no need to transmit coded signals over more than short or very short distances. Symbols are then omitted on a systematic basis so that there are fewer symbols per unit time and passed to a reconstruction circuit which may be a modified version of the reconstruction circuit 47. A waveform for audio reproduction equipment is then generated by stretching the duration of each encoded half cycle, in addition to providing the required number of minima. In this way the pitch of the helium speech is reduced and the speech is made intelligible.

Alternatives to linear digitising as carried out by the ND convertor 11 and subsequent encoding may be employed. For example use may be made of a linear delta-modulator digitiser in which an analogue signal is applied to a comparator where it is compared with, for example, the integrated comparator output, a "1" being generated if the analogue signal is larger than the integrated output and a "0" being generated otherwise. Thus a delta-mod output 1 1 1 1 1 1 1 100000 would indicate a polarity maxima or a polarity minima, dependent upon the sign of the output of the voltage comparator and "second signals" can be derived. RZs (and other features of shape) can also be derived from the deltamod output, in known ways, allowing "first signals" to be obtained.

Other digitising options are available to provide a time coded format. One simple version for use when low frequency background noise is absent is the 'Two Channel Count' Time Coder. Here, the RZ time intervals of the original input waveform are quantised and counted to give "first signals" and, in parallel with this operation the RZ time intervals of the differentiated input waveform are counted to give "second signals" and the two counts combined after allowances have been made (in the logic circuitry) for the phase shifts and time delays associated with the differentiating network.

Claims (30)

1. Apparatus for encoding varying signals, comprising means for generating a succession of pairs of first and second signals in which, in each pair, the first signal represents a first number representative of a first characteristic of a portion of the signal to be encoded and the second signal represents a second number representative of a second characteristic of the said portion, the first and second numbers being selected from predetermined sets of first and second numbers, respectively, and the apparatus also comprising means for generating a succession of secondary signals, each secondary signal being selected from a predetermined set of secondary signals in accordance with a pair of first and second signals, and the apparatus being such that a useful reconstruction of a signal which has been encoded can be carried out from the succession of secondary signals only.

2. Apparatus according to Claim 1 wherein each said portion is a half cycle as hereinbefore defined.

3. Apparatus according to Claim 2 wherein the means for generating pairs of first and second signals is constructed to provide first signals representative of the intervals between successive zeros of one af the following types: real zeros, pseudo zeros and interpolation zeros.

4. Apparatus according to Claim 2 or 3 wherein the means for generating pairs of first and second signals is constructed to generate digital signals each representative of a number indicating the length of a half cycle.

5. Apparatus according to Claim 2 wherein the means for generating pairs of first and second signals is constructed to provide second signals representative of the number of complex zeros of predetermined type or types in a half cycle.

6. Apparatus according to Claim 1 or 5 wherein the means for generating pairs of first and second signals is constructed to provide second signals representative of the number of events of one or more of the following types in each half cycle: magnitude maxima, magnitude minima, points of inflection.

7. Apparatus according to Claim 6 comprising an analogue-to-digital converter for converting the signal to be coded into digital samples, a comparator for comparing the magnitudes of successive samples to detect the occurrence of magnitude maxima and/or minima in the signal to be coded, and a counter coupled to the output of the comparator for counting the number of magnitude maxima and/or magnitude minima.

8. Apparatus according to Claim 4 or 5 including a pulse generator, a counter coupled to the pulse generator, and means for resetting the counter at the end of each half cycle of the signal to be coded, whereby the counter provides a counter representing the duration of each half cycle.

9. Apparatus according to Claim 8 wherein the analogue-to-digital converter has an output terminal at which a polarity signal representative of the polarity of the said samples appears, and the counter is coupled to the said terminal to be reset when the polarity signal changes.

10. Apparatus according to Claim 8 including logic means coupled to the comparator for generating a pseudo zero signal each time a first maximum magnitude occurs in a half cycle of the signal to be encoded and means for resetting the counter each time a pseudo zero signal occurs.

11. Apparatus according to any preceding claim wherein the means for generating secondary signals provides the same secondary signal for different pairs of signals in at least one group of said pairs in which first signals have adjacent or closely related values.

12. Apparatus according to any preceding claim wherein the means for generating secondary signals comprises a programmable read-only memory with outputs of the means for generating first and second signals coupled to address terminals of the memory.

1 3. Apparatus according to any preceding claim including sequence-reduction logic for omitting secondary signals on a systematic basis.

14. Apparatus according to Claim 1 3 wherein every rth to (r + 5)th secondary signal is omitted where rand s are integers and r is in the range two to eight and s is in the range 0 to seven.

1 5. Apparatus according to Claim 1 3 wherein the sequence-reduction logic includes means for recognising at least one secondary signal and for omitting at least one successive secondary signal after each said one signal is recognised.

1 6. Apparatus according to any preceding claim including means for providing an amplitude signal representative of the average peak amplitude over a plurality of half cycles of the signal to be encoded, and means for coding the amplitude signal for transmrssion with the secondary signals.

17. Apparatus according to any preceding claim including means for providing a packing signal for each coded said portion representative of the position of derived complex zeros in that portion, and means for coding the packing signal for transmission with the secondary signal.

1 8. Apparatus for constructing a required signal from a succession of signals in which each signal is one of a predetermined set of secondary signals each of which represents a first number and a second number from respective predetermined sets of first and second numbers, each first number and each second number representing a respective first and second characteristic of a portion of the required signal, the apparatus comprising means for deriving from a succession of said secondary signals, pairs of first and second signals, in which the first signal represents a said first number and the second signal represents a said second number, and means for deriving analogue signals from the pairs of signals derived, the analogue signals having portions with the characteristics in accordance with the numbers represented by the first and second signals of the derived pairs.

1 9. Apparatus according to Claim 1 8 for signal construction in which the first signals each represent the duration of a half cycle, as hereinbefore defined, and the means for deriving analogue signals derives analogue signal half cycles of durations derived from the first signals.

20. Apparatus according to Claim 1 8 for signal construction in which the second signals each represent the number of events as hereinbefore specified, occurring in a half cycle of the signal which has been encoded, and the means for deriving analogue signals derives half cycles each having a number of events, as hereinbefore specified, determined by a respective second signal.

21. Apparatus according to Claim 1 8, 1 9 or 20 wherein the means for deriving pairs of first and second signals comprises a programmable read-only memory connected to receive signals representing secondary signals at its address terminals and to provide pairs of the said first and second signals at its output terminals.

22. A method of encoding varying signals comprising means for generating a succession of pairs of first and second signals in which, in each pair, the first signal represents a first number representative of a first characteristic of a portion of the signal to be encoded and the second signal represents a second number representative of a second characteristic of the said portion, the first and second numbers being selected from predetermined sets of first and second numbers, respectively, and generating a succession of secondary signals, each secondary signal being selected from a predetermined set of secondary signals in accordance with a pair of first and second signals, and the method being such that a useful reconstruction of a signal which has been encoded can be carried out from the succession of secondary signals only.

23. A method according to Claim 22 wherein each said portion is a half cycle as hereinbefore defined.

24. A method according to Claim 23 wherein the datum is zero, or is offset to zero, and the first signals are generated by determining the interval between real zeros, or pseudo zeros as hereinbefore defined, or interpolation zeros as hereinbefore defined.

25. A method according to Claim 22 wherein each second signal represents the number of predetermined events as hereinbefore defined occurring in a said portion of the signal to be encoded.

26. A method according to any of Claims 22 to 25 wherein at least one possible secondary signal is capable of selection by any one of pairs of first and second signals in a group of signal pairs in which first and/or second signals have adjacent or closely related values.

27. A method of constructing a required signal from a succession of signals in which each signal is one of a predetermined set of secondary signals each of which represents a first number and a second number from respective predetermined sets of first and second numbers, each first number and each second number representing a respective first and second characteristic of a portion of the required signal, the method comprising deriving from a succession of said secondary signals, pairs of first and second signals, in which the first signal represents a said first number and the second signal represents a said second number, and deriving analogue signals from the pairs of signals derived, the analogue signals having portions with the characteristics in accordance with the numbers represented by the first and second signals of the derived pairs.

28. A method according to Claim 27 wherein construction is carried out from first and second signals, in which the second signals which each represent the number of events as hereinbefore defined, occurring in a half cycle, as hereinbefore defined, of the signal which has been encoded, and each half cycle of the said analogue signals has a number of the said events determined by a respective second signal.

29. A computer or computers programmed to carry out all or part of a method according to any of Claims 22 to 28.

30. Apparatus according to any of Claims 1 to 21 comprising one or more programmed computers.