JPS6344518U - - Google Patents
Info
- Publication number
- JPS6344518U JPS6344518U JP13803786U JP13803786U JPS6344518U JP S6344518 U JPS6344518 U JP S6344518U JP 13803786 U JP13803786 U JP 13803786U JP 13803786 U JP13803786 U JP 13803786U JP S6344518 U JPS6344518 U JP S6344518U
- Authority
- JP
- Japan
- Prior art keywords
- double
- signal
- wave rectified
- adder
- calculation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000010363 phase shift Effects 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案になるエンベロープ検波回路の
第１実施例を示すブロツク系統図、第２図及び第
３図は夫々本考案回路の第１実施例の動作説明用
信号波形図及び周波数特性図、第４図は本考案回
路の第２実施例を示すブロツク系統図、第５図及
び第７図は夫々本考案回路の要部になる演算手段
の他の実施例を示す回路系統図、第６図及び第８
図は夫々第５図及び第７図図示回路系統の動作説
明用信号波形図、第９図は従来のエンベロープ検
波回路の一例を示すブロツク系統図、第１０図及
び第１１図は夫々第９図図示ブロツク系統の動作
説明用信号波形図及び周波数特性図である。
１１……交流信号入力端子、１２，１５，２１
……両波整流回路、１３……移相回路、１４，２
２，４３，４４……加算器、１６……低域フイル
タ（ＬＰＦ）、１７……エンベロープ検波信号出
力端子、２３……遅延線、３１，３２，４１，４
２……両波整流信号入力端子、３３……演算信号
出力端子、４５……加算信号出力端子、Ｒ……抵
抗、Ｔ１，Ｔ２……トランジスタ、Ｆ３……リツ
プル周波数成分、……低域通過特性。
FIG. 1 is a block system diagram showing a first embodiment of the envelope detection circuit according to the present invention, and FIGS. 2 and 3 are signal waveform diagrams and frequency characteristic diagrams for explaining the operation of the first embodiment of the circuit according to the present invention, respectively. , FIG. 4 is a block system diagram showing a second embodiment of the circuit of the present invention, FIGS. Figures 6 and 8
The figures are signal waveform diagrams for explaining the operation of the circuit system shown in Figures 5 and 7, respectively. Figure 9 is a block diagram showing an example of a conventional envelope detection circuit. Figures 10 and 11 are Figure 9, respectively. FIG. 3 is a signal waveform diagram and a frequency characteristic diagram for explaining the operation of the illustrated block system. 11...AC signal input terminal, 12, 15, 21
...Double wave rectifier circuit, 13...Phase shift circuit, 14,2
2, 43, 44...Adder, 16...Low pass filter (LPF), 17...Envelope detection signal output terminal, 23...Delay line, 31, 32, 41, 4
2...Double-wave rectification signal input terminal, 33...Calculated signal output terminal, 45...Additional signal output terminal, R...Resistor, T1 , T2 ...Transistor, F3 ...Ripple frequency component,... Low-pass characteristics.
Claims (1)
、該交流信号を両波整流して第１の両波整流信号
を発生する両波整流回路と、該第１の両波整流信
号と同一の波形を有し、かつ、それに対して略（
２ｎ−１）×Ｔ／４（但し、ｎは自然数）の時間
分位相がずれた第２の両波整流信号を発生する手
段と、該第１及び第２の両波整流信号の間で演算
を行なつて略４ｍｆ（但し、ｍは１又は２）のリ
ツプル周波数を有する演算信号を生成する演算手
段と、該演算手段の出力演算信号より該リツプル
周波数を除去して該交流信号のエンベロープ検波
信号を出力する低域フイルタとよりなるエンベロ
ープ検波回路。 (2) 該演算手段は、該第１及び第２の両波整流
信号を夫々加算する加算器である実用新案登録請
求の範囲第１項記載のエンベロープ検波回路。 (3) 該演算手段は、該第１及び第２の両波整流
信号のうち大なるレベルの方の両波整流信号を選
択して出力する最大値選択回路である実用新案登
録請求の範囲第１項記載のエンベロープ検波回路
。 (4) 該演算手段は、該第１及び第２の両波整流
信号を夫々加算する第１の加算器と、該第１及び
第２の両波整流信号のうち大なるレベルの方の両
波整流信号を選択して出力する最大値選択回路と
、該第１の加算器及び該最大値選択回路の両出力
信号を夫々加算して得た加算信号を前記演算信号
として出力する第２の加算器とよりなる実用新案
登録請求の範囲第１項記載のエンベロープ検波回
路。[Claims for Utility Model Registration] (1) A double-wave rectifier circuit which is supplied with an alternating current signal with a period T (frequency f) and which double-wave rectifies the alternating current signal to generate a first double-wave rectified signal; It has the same waveform as the first double-wave rectified signal, and approximately (
means for generating a second double-wave rectified signal whose phase is shifted by a time of 2n-1)×T/4 (where n is a natural number), and a calculation between the first and second double-wave rectified signals. a calculation means for generating a calculation signal having a ripple frequency of approximately 4mf (where m is 1 or 2) by performing the following steps; and envelope detection of the alternating current signal by removing the ripple frequency from the output calculation signal of the calculation means. An envelope detection circuit consisting of a low-pass filter that outputs a signal. (2) The envelope detection circuit according to claim 1, wherein the calculation means is an adder that adds the first and second double-wave rectified signals, respectively. (3) The calculation means is a maximum value selection circuit that selects and outputs the higher level double-wave rectified signal of the first and second double-wave rectified signals. The envelope detection circuit described in item 1. (4) The arithmetic means includes a first adder that adds the first and second double-wave rectified signals, respectively, and a first adder that adds the first and second double-wave rectified signals, respectively, and an adder that adds the first and second double-wave rectified signals, whichever has a higher level. a maximum value selection circuit that selects and outputs a wave rectified signal; and a second circuit that outputs an added signal obtained by adding both output signals of the first adder and the maximum value selection circuit as the calculation signal. An envelope detection circuit according to claim 1, which comprises an adder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13803786U JPS6344518U (en) | 1986-09-09 | 1986-09-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13803786U JPS6344518U (en) | 1986-09-09 | 1986-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6344518U true JPS6344518U (en) | 1988-03-25 |
Family
ID=31042651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13803786U Pending JPS6344518U (en) | 1986-09-09 | 1986-09-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6344518U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993021495A1 (en) * | 1992-04-16 | 1993-10-28 | Kabushiki Kaisha Ace Denken | Metal detector for locating metallic body |
-
1986
- 1986-09-09 JP JP13803786U patent/JPS6344518U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993021495A1 (en) * | 1992-04-16 | 1993-10-28 | Kabushiki Kaisha Ace Denken | Metal detector for locating metallic body |
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