JPH0281513A - Frequency multiplier circuit - Google Patents
Frequency multiplier circuitInfo
- Publication number
- JPH0281513A JPH0281513A JP23306988A JP23306988A JPH0281513A JP H0281513 A JPH0281513 A JP H0281513A JP 23306988 A JP23306988 A JP 23306988A JP 23306988 A JP23306988 A JP 23306988A JP H0281513 A JPH0281513 A JP H0281513A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- waveform shaping
- phase shifter
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims abstract description 22
- 238000010586 diagram Methods 0.000 description 5
- 230000010363 phase shift Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、周波数逓倍回路に関する。[Detailed description of the invention] (b) Industrial application fields The present invention relates to a frequency multiplier circuit.
(ロ)従来の技術
従来、第4図のAに示すような交流信号を周波数逓倍し
て、クロック信号等を得るのに、第3図に示すように入
力される交流信号Aを、全波整流回路31で全波整流し
て、第4図のBに示す波形信号を出力し、この全波整流
された信号Bを波形整形回路32で波形整形し、第4図
のCに示す如きパルス信号を得ている。(B) Conventional technology Conventionally, when frequency-multiplying an AC signal as shown in A in Fig. 4 to obtain a clock signal, etc., the input AC signal A as shown in Fig. 3 is The rectifier circuit 31 performs full-wave rectification to output the waveform signal shown in B in FIG. I'm getting a signal.
(ハ)発明が解決しようとする課題
上記従来の周波数逓倍回路では、全波整流回路を用いて
いるため、回路が複雑となる上、得られたパルス信号の
デユーティサイクルが50%でなく、50%のものを得
ようとすれば、ワンショットマルチ回路等、さらに余分
の回路を付加せねばならず、回路が一層複雑になるとい
う問題があった。(c) Problems to be Solved by the Invention The conventional frequency multiplier circuit described above uses a full-wave rectifier circuit, which makes the circuit complex, and the duty cycle of the obtained pulse signal is not 50%. In order to obtain 50%, it is necessary to add an extra circuit such as a one-shot multi-circuit, which causes the problem that the circuit becomes even more complicated.
この発明は、上記問題点に着目してなされたものであっ
て、簡単な構成でデユーティサイクル50%の逓倍をな
し得る周波数逓倍回路を提供することを目的としている
。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a frequency multiplier circuit capable of multiplying the duty cycle by 50% with a simple configuration.
(ニ)課題を解決するための手段及び作用この発明の周
波数逓倍回路は、入力信号を受けて位相を90°移相す
る移相器(2)と、前記入力信号に受けて、零クロスで
波形整形し、矩形波信号を出力する第1の波形整形回路
(3)と、前記移相器の出力を受けて零クロスで波形整
形し、矩形波信号を出力する第2の波形整形回路(4)
と、前記第1及び第2の波形整形回路の出力を入力を受
けて、両人力の排他論理和を出力する論理回路(5)と
から構成されている。(d) Means and operation for solving the problems The frequency multiplier circuit of the present invention includes a phase shifter (2) that receives an input signal and shifts the phase by 90 degrees, and a phase shifter (2) that receives the input signal and shifts the phase by 90 degrees. A first waveform shaping circuit (3) that shapes a waveform and outputs a rectangular wave signal, and a second waveform shaping circuit (3) that receives the output of the phase shifter, shapes the waveform at a zero cross, and outputs a rectangular wave signal. 4)
and a logic circuit (5) which receives the outputs of the first and second waveform shaping circuits and outputs the exclusive OR of both of them.
この周波数逓倍回路では、入力信号の位相が移相器で9
0°移相される。そして、入力信号と移相器の出力がそ
れぞれ第1と第2の波形整形回路に入力され、零クロス
で波形整形され、デユーティ50%の矩形波信号が出力
される。これらの矩形波信号は、90’だけ互いに移相
のずれた波形であり、論理回路に入力され、排他論理和
か取られ、デユーティ50%で周波数が倍に逓倍された
パルス信号が出力される。In this frequency multiplier circuit, the phase of the input signal is changed to 9 by the phase shifter.
0° phase shifted. Then, the input signal and the output of the phase shifter are input to the first and second waveform shaping circuits, respectively, where the waveforms are shaped by the zero cross, and a rectangular wave signal with a duty of 50% is output. These rectangular wave signals have waveforms with a phase shift of 90' from each other, and are input to a logic circuit, exclusive ORed, and a pulse signal whose frequency is doubled with a duty of 50% is output. .
(ホ)実施例
以下、実施例により、この発明をさらに詳細に説明する
。(E) Examples The present invention will be explained in more detail with reference to Examples below.
第1図は、この発明の一実施例を示す周波数逓倍回路の
回路図である。この周波数逓倍回路は、入力端子1に入
力される入力信号への位相を90゜位相する移相器2と
、入力信号Aを零クロスで波形整形する第1の波形整形
回路3と、移相器2の出力を同じく零クロスで波形整形
する第2の波形整形回路4と、これら第1の波形整形回
路3と第2の波形整形回路4の出力が入力に接続され、
その両人力の排他論理和を出力端子6から出力する論理
回路5とから構成されている。FIG. 1 is a circuit diagram of a frequency multiplier circuit showing one embodiment of the present invention. This frequency multiplier circuit includes a phase shifter 2 that shifts the phase of the input signal input to the input terminal 1 by 90 degrees, a first waveform shaping circuit 3 that shapes the waveform of the input signal A at zero crosses, and a phase shifter 2 that shifts the phase of the input signal input to the input terminal 1 by 90 degrees. A second waveform shaping circuit 4 that also shapes the waveform of the output of the device 2 with a zero cross, and the outputs of the first waveform shaping circuit 3 and the second waveform shaping circuit 4 are connected to the input,
It is comprised of a logic circuit 5 which outputs the exclusive OR of both the inputs from an output terminal 6.
移相器2は、抵抗RとコンデンサCからなる45°の移
相回路を2段縦続接続して構成しているが、この移相回
路は1段あるいは3段等で90゜を移相する回路であっ
てもよい。The phase shifter 2 is constructed by cascading two stages of a 45° phase shift circuit consisting of a resistor R and a capacitor C, but this phase shift circuit shifts the phase by 90° in one or three stages. It may also be a circuit.
以上のように構成される周波数逓倍回路において、全入
力端子1に、第2図のAに示す交流の入力信号を加える
と、この信号への位相が移相器2で90°移相され、第
2図のBに示す波形信号が出力される。90°の移相を
受けているので、入力信号Aに対し、移相器2から出力
される信号Bは90°の位相差を持っている。入力信号
Aは、第1の波形整形回路3へ、移相器2の出力、つま
り信号Bは、第2の波形整形回路4へ、それぞれ入力さ
れ、零クロスで波形整形され、第1の波形整形回路3か
らは第2図のCに示す矩形波信号が出力され、第2の波
形整形回路4からは第2図のDに示す矩形波信号が出力
される。信号Cと信号りは、信号Aと信号Bの関係と同
様に90°の位相差を持っている。信号Cと信号りは、
論理回路5に入力され、論理処理される。信号Cと信号
りは、90°の位相差を持つゆえ、入力信号AのO〜9
0°では、信号Cが“H” (ハイ)であるに対し、信
°号りは“L” (ロー)であり、両者は論理不一致で
、排他論理和機能により論理回路5は出力端子6に“H
”を出力する(第2図のE参照)。次に、入力信号Aの
90〜18o°では信号C1信号りとも“HIIであり
、両者の論理は−敗し、したがって、論理回路5は、出
力端子6に“L”を出力する(第2図のE参照)。続い
て入力信号Aの180〜270°では信号Cが“L”で
あるに対し、信号りは“H”であり、両者は論理不一致
である。したがって、論理回路5は出力端子6に“H”
を出力する(第2図のE参照)。In the frequency multiplier circuit configured as described above, when an AC input signal shown in A in FIG. 2 is applied to all input terminals 1, the phase of this signal is shifted by 90 degrees by the phase shifter 2, A waveform signal shown in FIG. 2B is output. Since the phase has been shifted by 90 degrees, the signal B output from the phase shifter 2 has a phase difference of 90 degrees with respect to the input signal A. The input signal A is inputted to the first waveform shaping circuit 3, and the output of the phase shifter 2, that is, the signal B, is inputted to the second waveform shaping circuit 4, where the waveform is shaped at the zero cross, and the first waveform is The shaping circuit 3 outputs a rectangular wave signal shown in C in FIG. 2, and the second waveform shaping circuit 4 outputs a rectangular wave signal shown in D in FIG. Signal C and signal R have a phase difference of 90°, similar to the relationship between signal A and signal B. Signal C and signal RI are
The signal is input to the logic circuit 5 and subjected to logical processing. Since signal C and signal A have a phase difference of 90°, input signal A is
At 0°, the signal C is “H” (high), while the signal C is “L” (low), and the two are logically inconsistent, so the logic circuit 5 outputs the output terminal 6 due to the exclusive OR function. to “H”
(See E in FIG. 2).Next, when the input signal A is 90° to 18°, both the signal C1 and the signal C1 are "HII", and both logics fail, so the logic circuit 5 "L" is output to the output terminal 6 (see E in FIG. 2). Subsequently, at 180 to 270 degrees of input signal A, signal C is "L", while signal A is "H", and the two are logically inconsistent. Therefore, the logic circuit 5 outputs "H" to the output terminal 6.
(See E in Figure 2).
さらに、入力信号への270〜360°では信号C1信
号りともL”であり、両者は論理−敗であり、論理回路
5は、出力端子6に°L゛を出力する(第2図のE参照
)。そして、以後も時間の経過とともに、同様の動作を
繰返す。その結果、出力信号Eは、入力信号Aの位相9
0°毎に“Fビと°′L°“が反転する。つまり、デユ
ーティが50%で、周波数が入力信号の倍であるパルス
信号として出力される。Further, at 270 to 360 degrees to the input signal, the signal C1 is also L'', both are logic-defective, and the logic circuit 5 outputs °L'' to the output terminal 6 (E in Fig. 2). ).Then, the same operation is repeated as time passes.As a result, the output signal E becomes the phase 9 of the input signal A.
“F Bi and °′L°” are reversed every 0°. That is, it is output as a pulse signal with a duty of 50% and a frequency twice that of the input signal.
(へ)発明の効果
この発明によれば、90°の移相器と波形整形回路と、
排他論理和機能を持つ論理回路とで、回路を構成するも
のであり、全波整流回路は使用しないので、簡単な回路
構成で周波数逓倍回路を実現できる。しかも、90°の
移相器を使用することでデユーティサイクル50%で2
倍に逓倍されたパルス信号を確実に得ることができる。(f) Effects of the invention According to this invention, a 90° phase shifter and a waveform shaping circuit,
The circuit is configured with a logic circuit having an exclusive OR function, and a full-wave rectifier circuit is not used, so a frequency multiplier circuit can be realized with a simple circuit configuration. Moreover, by using a 90° phase shifter, 2
It is possible to reliably obtain a multiplied pulse signal.
第1図は、この発明の一実施例を示す周波数逓倍回路の
回路図、第2図は同実施例周波数逓倍回路の動作を説明
するための各部信号波形図、第3図は従来の周波数逓倍
回路の概略構成を示すブロック図、第4図は、同周波数
逓倍回路の動作を説明するための各部信号波形図である
。
に入力端子、 2:移相器、
3:第1の波形整形回路、
4:第2の波形整形回路、
5:論理回路、 6:出力端子。
特許出願人 ローム株式会社
代理人 弁理士 中 村 茂 信Fig. 1 is a circuit diagram of a frequency multiplier circuit showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part to explain the operation of the frequency multiplier circuit of the same embodiment, and Fig. 3 is a conventional frequency multiplier circuit. FIG. 4, a block diagram showing a schematic configuration of the circuit, is a signal waveform diagram of each part for explaining the operation of the frequency multiplier circuit. 2: Phase shifter, 3: First waveform shaping circuit, 4: Second waveform shaping circuit, 5: Logic circuit, 6: Output terminal. Patent applicant: ROHM Co., Ltd. Agent: Patent attorney: Shigeru Nakamura
Claims (1)
、前記入力信号を受けて、零クロスで波形整形し、矩形
波信号を出力する第1の波形整形回路と、前記移相器の
出力を受けて零クロスで波形整形し、矩形波信号を出力
する第2の波形整形回路と、前記第1及び第2の波形整
形回路の出力を入力に受けて、両入力の排他論理和を出
力する論理回路とからなる周波数逓倍回路。(1) A phase shifter that receives an input signal and shifts the phase by 90°; a first waveform shaping circuit that receives the input signal, shapes the waveform at a zero cross, and outputs a rectangular wave signal; a second waveform shaping circuit that receives the output of the phase converter, shapes the waveform with a zero cross, and outputs a rectangular wave signal; and a second waveform shaping circuit that receives the outputs of the first and second waveform shaping circuits as inputs, and excludes both inputs. A frequency multiplier circuit consisting of a logic circuit that outputs a logical sum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23306988A JPH0281513A (en) | 1988-09-17 | 1988-09-17 | Frequency multiplier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23306988A JPH0281513A (en) | 1988-09-17 | 1988-09-17 | Frequency multiplier circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0281513A true JPH0281513A (en) | 1990-03-22 |
Family
ID=16949317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23306988A Pending JPH0281513A (en) | 1988-09-17 | 1988-09-17 | Frequency multiplier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0281513A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5120989A (en) * | 1991-02-04 | 1992-06-09 | The United States Of America As Represented By The Secretary Of The Army | Simplified clock distribution in electronic systems |
JP2008216908A (en) * | 2007-03-07 | 2008-09-18 | Ricoh Co Ltd | Optical scanner and image forming apparatus |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5394857A (en) * | 1977-01-31 | 1978-08-19 | Toshiba Corp | Oscillation frequency converter circuit |
JPS58191522A (en) * | 1982-05-04 | 1983-11-08 | Toshiba Corp | Frequency multiplier circuit for smiconductor integrated circuit |
JPS59119919A (en) * | 1982-12-25 | 1984-07-11 | Fujitsu Ltd | Generating system of interpolating pulse |
JPS60154711A (en) * | 1984-01-25 | 1985-08-14 | Fujitsu Ltd | Frequency doubling circuit |
JPS6378610A (en) * | 1986-09-22 | 1988-04-08 | Nec Corp | Double clock generation circuit |
-
1988
- 1988-09-17 JP JP23306988A patent/JPH0281513A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5394857A (en) * | 1977-01-31 | 1978-08-19 | Toshiba Corp | Oscillation frequency converter circuit |
JPS58191522A (en) * | 1982-05-04 | 1983-11-08 | Toshiba Corp | Frequency multiplier circuit for smiconductor integrated circuit |
JPS59119919A (en) * | 1982-12-25 | 1984-07-11 | Fujitsu Ltd | Generating system of interpolating pulse |
JPS60154711A (en) * | 1984-01-25 | 1985-08-14 | Fujitsu Ltd | Frequency doubling circuit |
JPS6378610A (en) * | 1986-09-22 | 1988-04-08 | Nec Corp | Double clock generation circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5120989A (en) * | 1991-02-04 | 1992-06-09 | The United States Of America As Represented By The Secretary Of The Army | Simplified clock distribution in electronic systems |
JP2008216908A (en) * | 2007-03-07 | 2008-09-18 | Ricoh Co Ltd | Optical scanner and image forming apparatus |
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