JPH0718175Y2 - Full wave rectifier circuit - Google Patents
Full wave rectifier circuitInfo
- Publication number
- JPH0718175Y2 JPH0718175Y2 JP13444189U JP13444189U JPH0718175Y2 JP H0718175 Y2 JPH0718175 Y2 JP H0718175Y2 JP 13444189 U JP13444189 U JP 13444189U JP 13444189 U JP13444189 U JP 13444189U JP H0718175 Y2 JPH0718175 Y2 JP H0718175Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- absolute value
- output
- wave rectifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Rectifiers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【考案の詳細な説明】 [産業上の利用分野] 本考案は全波整流回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a full-wave rectifier circuit.
[従来の技術] 第4図(1)は従来の全波整流回路のブロック図、第4
図(2)はその回路図、第5図は各部の信号波形図であ
る。[Prior Art] FIG. 4 (1) is a block diagram of a conventional full-wave rectifier circuit.
FIG. 2B is a circuit diagram thereof, and FIG. 5 is a signal waveform diagram of each part.
この全波整流回路は絶対値回路7と積分回路8とからな
り、オペアンプ、ダイオードにより入力信号S11の絶対
値(両波)検波を行ない、コンデンサーにより整流(積
分)を行なうものである。This full-wave rectification circuit is composed of an absolute value circuit 7 and an integration circuit 8. The absolute value (both waves) of the input signal S 11 is detected by an operational amplifier and a diode, and the capacitor rectifies (integrates).
[考案が解決しようとする課題] 上述した従来の全波整流回路には次のような欠点があっ
た。[Problems to be Solved by the Invention] The conventional full-wave rectifier circuit described above has the following drawbacks.
第4図(2)において、コンデンサーCが取り付けられ
ていない場合の出力S13は第5図(2)に示す波形であ
り、コンデンサーCを取り付けると第5図(3)に示す
ように目的とする整流化された波形となる。ここで、当
然ながらCの値、すなわち容量を大きくすると積分効果
が大となり整流波形のリップル含有値が小さくなる。し
かしながら、その積分効果のため、第5図(2)および
(3)の比較で示すように、波形の遅れにより忠実度が
劣ってしまう。このリップル量と波形の忠実度は、相反
する関係であるため、従来回路では両者の妥協点を最適
値とし、コンデンサーCの容量値を決めていた。しかし
ながら、本来得るべき波形とはリップル含有量も少な
く、波形の遅れもない出力が必要であることは当然であ
る。In FIG. 4 (2), the output S 13 when the condenser C is not attached has the waveform shown in FIG. 5 (2), and when the condenser C is attached, the output is as shown in FIG. 5 (3). It becomes a rectified waveform. Here, as a matter of course, when the value of C, that is, the capacitance is increased, the integration effect is increased and the ripple content value of the rectified waveform is decreased. However, due to the integration effect, as shown in the comparison between (2) and (3) in FIG. 5, the fidelity deteriorates due to the delay of the waveform. Since the ripple amount and the fidelity of the waveform are in a contradictory relationship, the conventional circuit has determined the capacitance value of the capacitor C by making the compromise point between them the optimum value. However, it is natural that an output that does not have a ripple content and a waveform delay is required with respect to the waveform that should be obtained originally.
本考案の目的は、リップル量が少なく、かつ遅れの少な
い忠実度の良い整流出力が得られる全波整流回路を提供
することである。An object of the present invention is to provide a full-wave rectification circuit which has a small amount of ripples, a delay, and a high-fidelity rectified output.
[課題を解決するための手段] 本考案の全波整流回路は、 入力信号である正弦波交流バースト信号の位相を90°進
め、または遅らせる位相シフターと、入力信号の絶対信
号,位相シフターの出力信号の絶対値信号をそれぞれ出
力する第1,第2の絶対値回路と、 第1,第2の絶対値回路の絶対値信号をそれぞれ平滑する
第1,第2の積分回路と、 第1の積分回路の出力と第2の積分回路の出力の平均信
号を出力する平均値回路とを有する。[Means for Solving the Problems] The full-wave rectifier circuit of the present invention is a phase shifter that advances or delays the phase of a sinusoidal AC burst signal that is an input signal by 90 °, and outputs an absolute signal and a phase shifter of the input signal. First and second absolute value circuits that output the absolute value signals of the signals, respectively, first and second integration circuits that smooth the absolute value signals of the first and second absolute value circuits, and the first It has an average value circuit which outputs an average signal of the output of the integrating circuit and the output of the second integrating circuit.
[作用] 第1,第2の絶対値回路の絶対値信号はそれぞれ入力信
号,位相シフターの出力信号に対して周波数が2倍とな
る。よって、90°位相がずれたものが、周波数が2倍と
なったため、両絶対値信号は180°位相がずれることに
なる。したがって、両積分回路の出力信号に対して周波
数が2倍で、位相が互いに180°ずれた正弦波リップル
を含んでおり、平均値回路を通すことによりリップル成
分を含まない整流出力が得られる。[Operation] The absolute value signals of the first and second absolute value circuits have twice the frequency of the input signal and the output signal of the phase shifter, respectively. Therefore, since the phase shifted by 90 ° doubles the frequency, both absolute value signals are shifted by 180 °. Therefore, a rectified output that does not include a ripple component is obtained by passing the sine wave ripple whose frequency is twice that of the output signals of both integrator circuits and whose phases are shifted from each other by 180 °, and which passes through the average value circuit.
ここで、整流用の積分時定数はリップル成分が正弦波と
して残る程度の小さな値でよいため、整流出力の入力信
号に対する遅れはほとんど少ない。Here, since the integration time constant for rectification may be a small value such that the ripple component remains as a sine wave, there is almost no delay in the rectified output with respect to the input signal.
[実施例] 次に、本考案の実施例について図面を参照して説明す
る。[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.
第1図は本考案の一実施例を示す全波整流回路のブロッ
ク図、第2図はその各部の信号の波形図である。FIG. 1 is a block diagram of a full-wave rectifier circuit showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of signals of respective parts thereof.
この全波整流回路は、入力信号である交流信号S1の位相
を90°遅らせる位相シフター1と、入力信号S1の絶対値
信号S3,位相シフター1の出力信号S2の絶対値信号S4を
それぞれ出力する絶対値回路2,3と、絶対値回路2,3の絶
対値信号S3,S4をそれぞれ平滑する積分回路4,5と、積
分回路4の出力S5と積分回路5の出力S6の平均値信号S7
を出力する平均値回路6とからなっている。This full-wave rectifier circuit includes a phase shifter 1 that delays the phase of an AC signal S 1 that is an input signal by 90 °, an absolute value signal S 3 of the input signal S 1, and an absolute value signal S 2 of an output signal S 2 of the phase shifter 1. 4 an absolute value circuit 2 and 3 and outputs respectively, the absolute value signal S 3 of the absolute value circuit 2, S 4 and an integration circuit 4 and 5 respectively smooth, integral with the output S 5 of the integrating circuit 4 circuit 5 Output S 6 mean value signal S 7
And an average value circuit 6 for outputting
積分回路4,5の出力信号S5,S6は入力信号S1に対して周
波数が2倍で、互いに位相が180°ずれた正弦波リップ
ルを含んだ等しい直流電圧である。ここで重要なこと
は、積分回路4,5の積分時定数は、信号を完全に直流化
する値ではなく、図示のようにリップル成分が正弦波と
して残る程度の値であることである。信号S5,S6の直流
成分をeO,リップル成分の振幅をeAとすると、信号S5は
eO+eAsin(ωt+θ),信号S6は、eO+eAsin(ωt+
π+θ)で表わされる。この両者S5,S6を平均値回路6
を通すことによりeOなる直流電圧成分からなる信号S7が
取り出せる。The output signals S 5 and S 6 of the integrator circuits 4 and 5 have the same frequency as that of the input signal S 1 and are equal DC voltages including sine wave ripples whose phases are shifted by 180 °. What is important here is that the integration time constants of the integrator circuits 4 and 5 are not values for completely converting the signals into direct current, but values for which ripple components remain as sine waves as shown in the figure. If the direct current component of the signals S 5 and S 6 is e O and the amplitude of the ripple component is e A , the signal S 5 is
e O + e A sin (ωt + θ), the signal S 6 is e O + e A sin (ωt +
π + θ). These two S 5 and S 6 are connected to the average value circuit 6
A signal S 7 composed of a direct current voltage component e O can be taken out by passing through.
このように、本実施例によれば、リップル成分を含まな
い直流化出力S7を得ることができ、しかも前述のように
整流用の積分時定数も最小値にでき、波形の忠実度良く
出力が行なえる。As described above, according to the present embodiment, it is possible to obtain the DC output S 7 that does not include the ripple component, and further, as described above, the integration time constant for rectification can be minimized, and the waveform can be output with good fidelity. Can be done.
なお、位相シフター1では、入力信号S1の位相を90°進
めても同じである。Note that the phase shifter 1 is the same even if the phase of the input signal S 1 is advanced by 90 °.
第3図は全波整流回路の具体例の回路図で、第1図のブ
ロック図に対応している。FIG. 3 is a circuit diagram of a specific example of the full-wave rectifier circuit and corresponds to the block diagram of FIG.
第3の回路はオペアンプを用いた一般的な既存回路であ
り、その動作については、前述までの説明で充分であ
り、ここではその説明を省略する。The third circuit is a general existing circuit using an operational amplifier, and the description of the operation thereof is sufficient, and the description thereof is omitted here.
[考案の効果] 以上説明したように本考案は、正弦波交流バースト信号
を全波整流した信号と、前記正弦波交流バースト信号を
90°位相シフトした全波整流信号との平均値をとること
により、リップル量を減らして、しかも波形の忠実度の
良い整流出力が得られる効果がある。[Effect of the Invention] As described above, the present invention provides a signal obtained by full-wave rectifying a sine wave AC burst signal and the sine wave AC burst signal.
By taking the average value with the full-wave rectified signal that is phase-shifted by 90 °, it is possible to reduce the amount of ripples and obtain a rectified output with good waveform fidelity.
第1図は本考案の一実施例を示す全波整流回路のブロッ
ク図、第2図はその各部の信号の波形図、第3図は本考
案の全波整流回路の具体例の回路図、第4図(1),
(2)はそれぞれ従来の全波整流回路のブロック図と回
路図、第5図はその各部の信号の波形図である。 1……位相シフター、2、3……絶対値回路、4、5…
…積分回路、6……平均値回路、S1〜S7……信号。FIG. 1 is a block diagram of a full-wave rectifier circuit showing an embodiment of the present invention, FIG. 2 is a waveform diagram of signals of respective parts, and FIG. 3 is a circuit diagram of a specific example of the full-wave rectifier circuit of the present invention. Figure 4 (1),
(2) is a block diagram and a circuit diagram of a conventional full-wave rectifier circuit, respectively, and FIG. 5 is a waveform diagram of signals of respective parts. 1 ... Phase shifter 2, 3 ... Absolute value circuit 4, 5, ...
… Integrator circuit, 6 …… Average value circuit, S 1 to S 7 …… Signal.
Claims (1)
位相を90°進め、または遅らせる位相シフターと、 入力信号の絶対値信号,位相シフターの出力信号の絶対
値信号をそれぞれ出力する第1,第2の絶対値回路と、 第1,第2の絶対値回路の絶対値信号をそれぞれ平滑する
第1,第2の積分回路と、 第1の積分回路の出力と第2の積分回路の出力の平均値
信号を出力する平均値回路とを有する全波整流回路。1. A phase shifter for advancing or delaying the phase of a sinusoidal AC burst signal as an input signal by 90 °, and an absolute value signal of an input signal and an absolute value signal of an output signal of the phase shifter. A second absolute value circuit, first and second integrator circuits that smooth the absolute value signals of the first and second absolute value circuits, respectively, an output of the first integrator circuit and an output of the second integrator circuit Full-wave rectification circuit having an average value circuit for outputting the average value signal of
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13444189U JPH0718175Y2 (en) | 1989-11-21 | 1989-11-21 | Full wave rectifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13444189U JPH0718175Y2 (en) | 1989-11-21 | 1989-11-21 | Full wave rectifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0373022U JPH0373022U (en) | 1991-07-23 |
JPH0718175Y2 true JPH0718175Y2 (en) | 1995-04-26 |
Family
ID=31681780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13444189U Expired - Lifetime JPH0718175Y2 (en) | 1989-11-21 | 1989-11-21 | Full wave rectifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0718175Y2 (en) |
-
1989
- 1989-11-21 JP JP13444189U patent/JPH0718175Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0373022U (en) | 1991-07-23 |
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