JPH02168852A - Constant voltage power source circuit - Google Patents

Constant voltage power source circuit

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Publication number
JPH02168852A
JPH02168852A JP32544588A JP32544588A JPH02168852A JP H02168852 A JPH02168852 A JP H02168852A JP 32544588 A JP32544588 A JP 32544588A JP 32544588 A JP32544588 A JP 32544588A JP H02168852 A JPH02168852 A JP H02168852A
Authority
JP
Japan
Prior art keywords
constant voltage
circuit
voltage power
delay circuits
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32544588A
Other languages
Japanese (ja)
Inventor
Yoshihisa Suzuki
義久 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32544588A priority Critical patent/JPH02168852A/en
Publication of JPH02168852A publication Critical patent/JPH02168852A/en
Pending legal-status Critical Current

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  • Power Conversion In General (AREA)
  • Rectifiers (AREA)

Abstract

PURPOSE:To eliminate almost all ripple components by arranging (n) delay circuits in parallel with a rectifier circuit and further providing an adder circuit for adding and averaging the outputs from the delay circuits. CONSTITUTION:Phases of ripple components are shifted by t1, t2,...tnms(t1 t2 ...tn 10ms), respectively, from that of a rectified output voltage V1 through delay circuits 2, then voltages V1, V2,...Vn are added in an adder 3. By such arrangement, ripple components can be eliminated almost perfectly.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、定電圧電源回路に関し、特に、整流回路にお
いて発生するリップルを無視できる程度まで軽減して一
定電圧を得る定電圧電源回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a constant voltage power supply circuit, and more particularly to a constant voltage power supply circuit that obtains a constant voltage by reducing ripples generated in a rectifier circuit to a negligible extent.

従来の技術 従来、この種の電源回路は、交流久方を直流に変換する
際に出力は脈流として現れ(第4図b)、それを緩和す
るために出力側にコンデンサが並列に挿入される。しか
しながら、それても出力電圧にリップルが残る(第4図
C)。コンデンサの容量が大きい程リップルを小さくす
ることができ、電圧変動を少なくできるが、逆に大型化
につながり、コストも高くなるという欠点があった。
Conventional technology Conventionally, in this type of power supply circuit, when converting AC into DC, the output appears as a pulsating current (Figure 4b), and a capacitor is inserted in parallel on the output side to alleviate this. Ru. However, a ripple still remains in the output voltage (FIG. 4C). The larger the capacitance of the capacitor, the smaller the ripple and the less voltage fluctuation, but this has the drawback of increasing the size and cost.

発明が解決しようとする課題 上述した従来の電源回路は、交流を直流に変換した直後
の出力は第4図すのように脈流であるので、これを平滑
fヒするために第2図のようにコンデンサCが挿入され
る。
Problems to be Solved by the Invention In the conventional power supply circuit described above, the output immediately after converting alternating current to direct current is a pulsating current as shown in Figure 4. In order to smooth this, the output shown in Figure 2 is used. Capacitor C is inserted as follows.

しかしながら、それても第4図Cに示すようにリップル
か残ってしまう。このリップルは、負荷のインピーダン
スとコンデンサCどの時定数によって定すり、コンデン
サCの容量を大きくすればリップルは減少するか、逆に
大型1ヒ、高コスト化の課題が生じるという欠点がある
However, even in this case, ripples remain as shown in FIG. 4C. This ripple is determined by the impedance of the load and the time constant of the capacitor C.If the capacitance of the capacitor C is increased, the ripple can be reduced, but on the other hand, there is a problem of large size and high cost.

本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記欠点
を解消し、簡単な構成によりリップル成分を殆ど含まな
い良好な定電圧を得ることを可能とした新規な定電圧電
源回路を提供することにある− 発明の従来技術に対する相違点 」二連した従来の電源回路に対し、本発明の定電圧電源
回路は、リップル成分を殆ど解消てきる」二に、精度か
ほぼ等しい従来の電源回路よりも小型化でき、またコス
l−を低くできる可能性を持つという相違点を有する。
The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a new constant voltage power supply circuit which eliminates the above-mentioned drawbacks inherent in the conventional technology and which makes it possible to obtain a good constant voltage containing almost no ripple components with a simple configuration. Differences between the invention and the prior art: ``Compared to the conventional dual power supply circuit, the constant voltage power supply circuit of the present invention almost eliminates the ripple component.'' Second, the accuracy is almost the same as that of the conventional power supply circuit. It also has the difference that it can be made smaller and has the possibility of lowering the cost l-.

課題を解決するだめの手段 前記1」的を達成する為に、本発明に係る定電圧電源回
路は、交流を直流に変換するだめの整流回路と、該整流
回路から得られる電圧波形よりn個の位相の異なった電
圧波形を得るために前記整流回路に並列に接続されたn
個の並列遅延回路と、該n個の遅延回路の出力を加え合
わせて平均化された定電圧を得るための加算回路とを備
えて構成される。
Means for Solving the Problems In order to achieve the above-mentioned object 1, the constant voltage power supply circuit according to the present invention includes a rectifier circuit for converting alternating current into direct current, and n voltage waveforms obtained from the rectifier circuit. n connected in parallel to the rectifier circuit to obtain voltage waveforms with different phases.
The device is configured to include: n parallel delay circuits; and an adder circuit for adding the outputs of the n delay circuits to obtain an averaged constant voltage.

実施例 次に、本発明をその好ましい一実施例について図面を参
照して具体的に説明する。
Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

第1図は本発明の一実施例を示す回路構成図である。FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

第1図を参照するに、整流回路1は、リップルを含んだ
直流電圧1(第4図C〉を発生ずる。整流回路]の出力
をn個の遅延回路2でn通りの位相の電圧波形に分け、
これらの出力を加算器3て合成して平均化された定電圧
−■を得る。
Referring to FIG. 1, a rectifier circuit 1 generates a DC voltage 1 containing ripples (C in FIG. 4). Divided into
These outputs are combined by an adder 3 to obtain an averaged constant voltage -■.

第4図は、回路の各部における電圧波形である。FIG. 4 shows voltage waveforms at various parts of the circuit.

例えは、元の交流電圧(VIN) aか50[Hz]と
すれば、整流回路1によってます脈流(vO)lDとな
り、更にコンデンサで100[Hzlのリップル成分を
持った電圧(穎)Cとされる。リップル成分の周期はT
]、/fより10[ms]である。電圧v1と遅延回路
2によって電圧V1より位相がそれぞれL+、t2.−
、 t、[ms](1+≠L2≠ ≠し。≠10m5 
)な(すすれた電圧Vl、V2旨(第4図d、e、f)
とを加算器3によって加え合わせると、リップル成分を
無視てきる定電圧(−V) gか得られる。
For example, if the original AC voltage (VIN) is 50 [Hz], the rectifier circuit 1 creates a pulsating current (VO) 1D, and the capacitor further increases the voltage (VIN) with a ripple component of 100 [Hz] C. It is said that The period of the ripple component is T
], /f is 10 [ms]. Due to the voltage v1 and the delay circuit 2, the phases are L+, t2 . −
, t, [ms] (1+≠L2≠ ≠shi.≠10m5
) (sloped voltages Vl, V2 (Fig. 4 d, e, f)
By adding them together by the adder 3, a constant voltage (-V) g that can ignore the ripple component is obtained.

発明の詳細 な説明したように、本発明によれは、整流回路に少なく
とも1個以」二の遅延回路と加算器を接続することによ
り、リップル成分を殆ど無視てきる定電圧を得られると
いう効果か生ずる。
As described in detail, according to the present invention, by connecting at least one or two delay circuits and an adder to a rectifier circuit, it is possible to obtain a constant voltage that can almost ignore ripple components. will occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路構成図、第2図は
第1図に示された整流回路の一例を示す回路図、第3図
は第1図に示された遅延回路の一例を示す回路図、第4
図は第1図に示した回路における特定位置での電圧波形
図である。 R、l−1,+ r2・抵抗、1(+〜n)・遅延時間
、AO演算増幅器、T=、1〜ランス、D ダイオード
、CC11コンデンサ、1 ・整流回路、2・・遅延回
路、3 加算器、4 演算増幅器 特許出願人   日本電気株式会社 代 理 人   弁理士 熊谷雄太部 ■
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the rectifier circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the rectifier circuit shown in FIG. 1. Circuit diagram showing an example, No. 4
This figure is a voltage waveform diagram at a specific position in the circuit shown in FIG. 1. R, l-1, + r2・Resistance, 1(+~n)・Delay time, AO operational amplifier, T=, 1~Lance, D diode, CC11 capacitor, 1・Rectifier circuit, 2・・Delay circuit, 3 Adder, 4 Operational amplifier patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai■

Claims (1)

【特許請求の範囲】[Claims] 交流信号が印加される整流回路と、前記整流回路の出力
信号が印加される複数の遅延回路と、前記各遅延回路の
出力信号を加え合わせるための加算器とを具備し、前記
加算器の出力端子より直流信号を得ることを特徴とする
定電圧電源回路。
A rectifier circuit to which an alternating current signal is applied, a plurality of delay circuits to which output signals of the rectifier circuit are applied, and an adder for adding together the output signals of the respective delay circuits, the output of the adder A constant voltage power supply circuit characterized by obtaining a DC signal from a terminal.
JP32544588A 1988-12-22 1988-12-22 Constant voltage power source circuit Pending JPH02168852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32544588A JPH02168852A (en) 1988-12-22 1988-12-22 Constant voltage power source circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32544588A JPH02168852A (en) 1988-12-22 1988-12-22 Constant voltage power source circuit

Publications (1)

Publication Number Publication Date
JPH02168852A true JPH02168852A (en) 1990-06-28

Family

ID=18176941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32544588A Pending JPH02168852A (en) 1988-12-22 1988-12-22 Constant voltage power source circuit

Country Status (1)

Country Link
JP (1) JPH02168852A (en)

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