KR960003562B1 - Demodulator system - Google Patents

Abstract

The frequency of synchronous rectified signal is doubled to increase gain and to decrease ripple so that position of a motor is detected precisely. The apparatus includes an amplifier(8) for amplifying output signal of a current booster(2), a delay(9) for delaying the phase of output signal of the amplifier by 90 degrees, inverters(10,11) for inverting output signal of the delay(9), an analog switch(5) for selecting output signals of the delay(9) or inverter(11), an analog switch(4) for selecting output signals of the delay(9) or inverter(10), and an adder(6) for adding output signals of the analog switches(4,5).

Description

Resolver Signal Demodulation System

A and b of FIG. 1 are diagrams illustrating a demodulation system of a conventional resolver signal.

A to e in FIG. 2 are input / output waveform diagrams of respective parts of FIG.

3 is a block diagram of a resolver signal excitation system of the present invention.

4 is a diagram illustrating a demodulator system configuration of a resolver signal of the present invention.

5 is a and i are input and output waveform diagrams of the parts shown in FIGS. 3 and 4, respectively.

* Explanation of symbols for main parts of the drawings

1: Function generator 2: Current booster

3: comparison unit 4, 5: analog switch

6: adder 7: low pass filter

8: amplification unit 9: phase delay unit,

10,11: inverter section

The present invention is based on the demodulation of the resolver signal. In particular, in the position detection device of the motor by the synchronous rectification method, the frequency of the synchronous rectification is doubled in the position detection device of the motor by the synchronous rectification method. The present invention relates to a demodulation system of a resolver signal which improves the accuracy and detects the correct motor position.

As shown in FIG. 1, the demodulation system of the conventional resolver signal includes a function generator (1) for generating a sine wave and a triangular wave signal of an excitation frequency required for the resolver, and the function generator (1). excitation frequency current booster unit (2), a synchronization clock signal (S ₀₎ by comparing the triangular wave signal is equal to the output and the excitation frequency (f ₀₎ from the generator (1) the function to the amplified output (f ₀₎ Is switched on and off in accordance with a comparator 3 comprising a resistor R ₁ (R ₂ ) and a comparator CP ₁ , and a synchronous clock signal S ₀ output from the comparator 3. High signal S of excitation frequency f ₀ output from current booster section 2 ) And a low signal (S ^_ ) through the resistor (R ₃ ) (R ₄ ) to rectify and output the analog switch (4) (5), and the signal output from the analog switch (4) (5) to the output terminal (S _out), the operational amplifier (a ₁₎ and a resistor ₍₅₎ (R ₆₎ to the holding portion 6 and the output terminal (S _out1) filters the output signal of the rectifying section (6) for outputting a It consists of a low pass filter part 7 for outputting with a.

The operation and other problems of the conventional resolver signal demodulation system configured as described above are as follows.

First, when the sine wave signal of the excitation frequency required for the resolver is outputted from the function generator 1, the current booster unit 2 amplifies the sine wave signal output from the function generator 1 to generate an excitation frequency as shown in FIG. will print (f ₀ ). In addition, the triangular wave signal synchronized with the excitation frequency f ₀ is outputted from the function generator 1, through the resistor R ₁ of the comparator ₃ , and then the non-inverting terminal (+) of the comparator CP ₁ . When applied to the comparator (CP ₁ ) is compared to the ground potential applied to its inverting terminal (-) to output a synchronous clock signal (S ₀ ) as shown in c of FIG.

The excitation frequency f ₀ output from the current booster unit 2 is divided into a high signal S ⁺ and a low signal S ₋ and an analog switch unit (R ₃ ) through each of the resistors R ₃ (R ₄ ). 4) (5) is applied to the fixed terminals (a) and (b), and the synchronous clock signal S ₀ output from the comparator 3 is the movable terminal c of the analog switches 4 and 5 described above. Is entered. At this time, when the high potential synchronous clock signal S ₀ is output from the comparator 3, the resistor R ₃ is connected to the fixed terminal a of the movable terminal c of the analog switch 4 and 5. The high signal (S ⁺ ) of the excitation frequency (f ₀ ) through is applied to the non-inverting terminal (+) of the operational amplifier (A ₁ ) configured in the rectifier (6). Accordingly, a high signal such as d in FIG. 2 is output to the output terminal S _out of the operational amplifier A ₁ , and conversely, when the synchronous clock signal S ₀ is output low from the comparator 3, the analog switch 4 is output. non-inversion of a) an operational amplifier _{(a 1) -) (5} ) the movable terminal (c) is a low signal (S of the excitation frequency (f ₀₎ with is connected to its fixed terminal (b) resistance (R ₄₎ of the To the terminals. Accordingly, the operational amplifier A ₁ inverts the input low signal S ⁻ to a high signal and outputs a high signal such as d in FIG. 2 to the output terminal S _out , and is output from the rectifying unit 6. The signal is filtered through the low pass filter 7 as shown in b of FIG. 2 and then output to the output terminal S _out1 , which is converted into position information through an analog / digital conversion process.

However, such a conventional demodulation system of the resolver signal has a ripple corresponding to the excitation frequency of the excitation frequency rectified and outputted from the rectifying unit, which is twice the excitation frequency. It has a ripple adversely affects the accurate position information, there was a problem that can not obtain a high accuracy position.

In view of the conventional problems, the present invention includes a phase delay unit, an inverter unit, and a multiplier unit, so that the synchronous rectification doubles the frequency, improves the ripple of the demodulated signal, and improves the resolution of the resolver signal so as to detect accurate position information of the motor. Invented a demodulation system, which will be described below in detail with reference to the accompanying drawings.

3 is a configuration diagram of the resolver signal excitation unit system of the present invention, and FIG. 4 is a configuration diagram of a demodulator system of the resolver signal of the present invention. As shown in FIG. 4, a sine wave, a triangular wave, and a square wave signal of an excitation frequency required for the resolver are illustrated. The function generator 1 to generate, the current booster 2 for amplifying and outputting the excitation frequency f _{0 of} the function generator 1, and the excitation frequency f ₀ from the function generator 1 ) and a synchronous clock signal (S ₀₎ (resistors (R ₁ -R _4), and a comparator (CP ₁₎ (CP ₂₎ for generating an S ₁₎ by respectively comparing the respective triangular wave signal and a square wave signal which is equal to the output And a resistor R ₅ -R for amplifying the high signal S ⁺ and the low signal S ⁻ of the excitation frequency f ₀ outputted from the current booster 2 to the predetermined level. ₈ ), an amplifier ₈ consisting of a differential amplifier A ₁ , a resistor R ₉ -R ₁₁ , a cone for delaying the phase of the resolver signal output from the amplifier 8 by 90 °. Phase delay unit 9 comprising a denser C ₁ and operational amplifier A ₂ , resistors R ₁₅ -R ₁₇ and operational amplifier A ₄ for inverting the output signal of the phase delay unit 9. And an analog switch for switching between the phase delay unit 9 and the inverter unit 11 so as to switch between the inverter unit 11 and the synchronous clock signal S ₁ output from the comparison unit 3. (5), an inverter unit (10) comprising resistors (R ₁₂ -R ₁₄ ) and operational amplifiers (A ₃ ) for inverting and outputting resolver signals of the amplifier (8), and the comparison unit (3). The switching signal is switched according to the synchronous clock signal S _{0 of} the analog switch 4 for selecting output signals of the amplifier 8 and the inverter 10, and the signals selected from the analog switches 4 and 5 The adder 6 composed of the resistors R ₁₅ -R ₂₁ , which are synthesized and output to the output terminal S _out , and the operational amplifier A ₅ , and the output signal of the adder 6 is filtered. a low output to the (S _out1) It constitutes a spill taboo 7.

Referring to the operation and effect of the present invention configured as described above with reference to FIGS. 3 to 5 as follows.

First, when the sine wave signal of the excitation frequency required for the resolver is output from the function generator 1, the current booster 2 amplifies the sine wave signal output from the function generator 1 to generate an excitation frequency as shown in FIG. will print (f ₀ ).

In addition, the triangular wave signal synchronized with the excitation frequency f ₀ and the square wave signal 90 ° out of phase with the triangular wave signal are output from the function generator 1 so that each resistor R ₁ of the comparator 3 (R) ₃₎ after then through applied to the comparator (CP ₁₎ (non-inverting terminal (+) of CP _2), the comparator (CP ₁₎ (CP ₂₎ has its inverting terminal (- compared to the ground potential applied to) the fifth The synchronization clock signal S ₀ as shown in b and c of FIG. 10 and the synchronization clock signal S ₁ earlier than 90 ° out of phase are output. The high signal (S ⁺ ) and the low signal (S ⁻ ) of the resolver signal output from the current booster unit (2) pass through each resistor (R ₅ ) (R ₆ ) of the amplifier unit (8) and then the differential amplifier ( In A ₁ ), the difference is amplified, as in d of FIG. 5, and the amplified resolver signal is a phase delay part ₉ composed of resistors R _9- R ₁₁ , capacitors ₁ , and operational amplifiers A ₂ . After the phase is delayed by 90 ° as shown in FIG. 5E, the inverter 11 is input to the fixed terminal (a) of the analog switch (5) and the resistor (R ₁₅ -R ₁₇ ) and the operational amplifier (A ₄ ). Inverted through and applied to the fixed terminal (b) of the analog switch (5).

In addition, the resolver signal output from the amplifier 8 is inverted through the inverter unit 10 including the resistors R ₁₂ -R ₁₄ and the operational amplifiers A ₃ to fix the terminal b of the analog switch 4. Is entered. At this time, when the high potential synchronous clock signal S ₀ is output from the comparator 3, the movable terminal c of the analog switch 4 is connected to its fixed terminal a, so that a high signal such as f in FIG. When the in-resolver signal is outputted, on the contrary, when the low potential synchronous clock signal S ₀ is output from the comparator 3, the movable terminal c of the analog switch 4 is connected to its fixed terminal b. The inverter unit 10 outputs a resolver signal that is an inverted high signal. In addition, when the synchronous clock signal S ₁ is output from the comparator 3 at high potential, the movable terminal c of the analog switch 5 is connected to its fixed terminal b so that the inverter unit 11 as shown in FIG. When the inverted resolver signal is inverted to a high signal through the output signal, and the synchronous clock signal S ₁ is output at the low potential from the comparator 3, the movable terminal c of the analog switch 5 becomes its fixed terminal. It is connected to (a) and outputs a high potential resolver signal through the phase delay unit 9. The resolver signal synchronously rectified by the analog switches 4 and ₅ is synthesized as shown in FIG. 5 by the adder 6 including the resistors R _{18 and} R ₂₁ and the operational amplifier A ₅ , as shown in FIG. It is output as (S _out1 ).

As described in detail above, the present invention uses an adder, a phase delay unit, and an inverter unit to double the frequency of the synchronous normal to reduce the ripple of the demodulated signal and to double the enhancement, thereby enabling high accuracy analog / digital conversion. In addition, the position of the motor can be accurately detected by the converted digital value.

Claims (1)

The excitation signal f ₀ generated by the function generator 1 is amplified by the current booster 2 and the synchronous clock signal S ₀ output from the function generator 1 is synchronized with the comparator 3. In a demodulation system of a resolver signal for demodulating a resolver signal according to the compared synchronous clock signal (S ₀ ), the excitation frequency (f ₀ ) of the current booster (2) is set to a predetermined level. An amplifying section 8 for amplifying, a phase delay section 9 for phase-delaying the resolver signal amplified by the amplifying section 8, and a resolver signal of the phase delay section 9 inverted and outputted. An analog switch for switching between the inverter unit 11 and the synchronous clock signal S ₁ output from the comparison unit 3 to select the output signals of the phase delay unit 9 and the inverter unit 11; 5) and, according to the synchronous clock signal (S ₀₎ of the drive unit 10, the comparison unit 3, which output to turn the resolver signal in the amplifying section 8's An analog switch 4 for selecting and outputting the output signals of the amplifying unit 8 and the inverter unit 10 and an adder for synthesizing and outputting a resolver signal selected from the analog switches 4 and 5; 6) A demodulation system for a resolver signal, characterized in that: