JPS6343928B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fail-safe counting device, and more particularly, to a counting device that safely fails due to a failure in a constituent circuit.

For example, regarding train operation management, in order to ensure signal safety in a certain blocked section, the number of axles of a train that entered the blocked section is compared with the number of axles of a train that left the blocked section, and the number of axles of the train that entered the blocked section is checked. A train detection device is used to detect the presence or absence of trains.

This train detection device consists of two axle counters, one for counting the axles of an incoming train, one for counting the axles of an outgoing train, and a collation device for comparing the counts of both counters. In order to ensure fail-safety for the blocked section when the train detection device fails, it is not enough that the failure mode of each component simply indicates an asymmetric failure mode. If the counted value is greater than the actual number of axles entering the blocked section (the side where the counted value advances), and the axle counter for the entering train fails, the counted value will be It is necessary for the failure to occur on the side where the number of axles is less than the actual number of advancing axles (the side where the counted value does not advance).

The present invention relates to a counting device that can be used as an outgoing train axle counter of the above two axle counters.

[Technical Problem to be Solved] When a counting device outputs count values in parallel, a memory device consisting of a memory circuit group that outputs count values for each bit is required. Therefore,
As mentioned above, in order for the output value to be biased toward a specific side (the side where the counted value advances) when the counting device fails, the storage device, which is a component of the counting device, must also suffer from a similar asymmetric failure mode. It must be something that shows.

Conventional counting devices, including their memory devices, are composed of IC (integrated circuit) elements, discrete gates such as C-MOS or TTL, or flip-flops, so the output signal cannot be affected by failures. There is an error in either the logic value "1" or "0" (this is called symmetrical error output characteristic), and since no fail-safe processing is applied, the output will not necessarily remain constant even when an accident or failure occurs in the circuit system. (safe side output) and outputs a random signal, and a counting device that exhibits the above-mentioned asymmetric failure mode on the specific side has not yet been supplied on the market.

This invention aims to provide a fail-safe counting device that exhibits an asymmetric failure mode in which all output voltages are always deflected to 0 when a failure occurs in a component circuit, that is, a failure occurs on the side where the count value advances. It is.

[Means for Solving Problems] In order to solve the above problems, a counting device according to the present invention has the following features: (a) A preset signal inputted to a first input terminal via a backflow prevention circuit and a set signal inputted to a second input terminal. It has a memory device comprising n-stage memory circuits in parallel, each consisting of an asymmetrical error AND circuit that outputs an output based on the logical product of of the counting input signal having the polarity when counting is to be performed, and the voltage of the polarity of the counting input signal at the previous stage of the memory circuit i (i=2, 3, ..., n) of the storage device, that is, the i-1st stage of the memory circuit, respectively. an asymmetric error AND circuit that stores and outputs the output voltage of the preceding storage circuit by ANDing it with the output voltage;
(c) a steering gate circuit comprising n-1 stage gate circuits in parallel, each having a logic gate that bypasses a voltage signal of a polarity when not to be counted among the counting input signals; (c) the storage device; The voltage of the polarity when counting is not to be performed among the count input signals is input to the second input terminal of the first stage memory circuit as the set signal, and the second input terminal of the second stage and subsequent stage memory circuits is inputted to the second input terminal of the first stage memory circuit. The present invention is characterized in that the output signal of the asymmetric error AND circuit of the gate circuit corresponding to the memory circuit and the bias signal of the logic gate are connected so as to be inputted as the set signal, respectively.

[Example of this invention] Next, this invention will be explained based on the drawings.

As shown in FIG. 1, the counting device according to the present invention generally includes (a) an n-1 stage (three stages in the illustrated example) gate circuit;
Steering gate circuit STG consisting of G ₁ to _{G 3}
and (b) n-stage (four-stage in the illustrated example) storage circuit LS ₁ ~
It is equipped with a storage device MY consisting of LS ₄ .

Each of the gate circuits G ₁ to G 3 of the steering gate circuit STG has diodes _D 1 to _{G 3} connected to similar asymmetric error AND circuits AL ₁ to AL ₃ , respectively.
It is made by connecting D ₃ in parallel. Each of the asymmetric error AND circuits AL ₁ to _{AL 3} has positive input terminals a, b, a negative input terminal e, and two positive output terminals c ₁ , c ₂ .
A counting input signal CP of positive and negative polarity voltage is input to the input terminal e, and the input terminal e is connected to its output terminal c ₁ via diodes D ₁ to D ₃ to form a logical sum with the output signal of the terminal c ₁ . Moreover, the positive voltage output from the output terminal _c2 is fed back to the input terminals a and b.

Furthermore, each storage circuit LS ₁ to LS of the storage device MY
LS ₄ is similarly composed of an asymmetric error AND circuit having a first input terminal a to which a reset signal is input, a second input terminal b to which a set signal is input, and an output terminal c. Positive voltage outputs CV ₁ to _{CV 4} are generated by satisfying the AND condition of the preset signal and the set signal.

A preset signal RS (positive voltage) is input to the input terminal a of all the memory circuits via diodes D ₄ to D ₇ as reverse current blocking circuits. The first-stage storage circuit LS ₁ receives the counting input signal CP, and the second-stage and subsequent storage circuits LS ₂ to _{LS 4} are gate circuits G ₁ to _{G 3} corresponding to the steering gate circuits STG, respectively.
The positive voltage outputs ST ₁ to _{ST 3} are inputted to each positive input terminal b as a set signal. Each positive voltage output CV ₁ -CV ₄ is then fed back to its own positive input terminal a.

Furthermore, each storage circuit LS ₁ to LS of the storage device MY
The positive voltage outputs CV ₁ to _{CV 3} of LS ₃ are inputted to the positive input terminals a and b of the asymmetric error AND circuits AL ₁ to _{AL 3} of the subsequent gate circuits of the steering gate circuit STG, respectively. When a positive polarity voltage output is generated in the memory circuits LS ₁ to _{LS 3} in the preceding stage of the gate circuit, while the count input signal CP is negative,
A positive output voltage is generated at the output terminal _c1 of the asymmetric error AND circuits _AL1 to _AL3 .

That is, the asymmetric error AND circuits AL ₁ to AL ₃ and LS ₁ to _{LS 4} are all asymmetric error logic circuits with phase non-inversion characteristics.

Note that the diodes D ₁ to _{D 3} are used as counting input signals.
c ₁ output of CP and asymmetric error AND circuit AL ₁ ~ _{AL 3}
ST ₁ to _{ST 3} are separated by polarity, and when the count input signal CP has positive polarity, this is used as the input voltage of the direct storage circuits LS ₁ to _{LS 3} , and
The diodes _D4 to _D7 prevent the preset signal RS and the outputs _CV1 to _CV4 of the memory circuit MY from influencing each other.

By the way, the asymmetric error AND circuit AL ₁ ~
AL ₃ each has a configuration as shown in FIG. 2, and the asymmetric error AND circuits used in the storage circuits LS ₁ to _{LS 4} each have a configuration as shown in FIG. 3, as an example. In other words, the asymmetric error AND circuit is roughly divided into three parts: an oscillation part, an amplification part, and a rectification output part.To explain the one in Figure 2, when a positive voltage is applied to terminal a, oscillation occurs. Circuit 1 oscillates, and the oscillation output is connected to the capacitor.
It is applied to the base terminal of transistor Q ₁ via C ₁ . When a positive voltage is applied to terminal b, the resistance
The transistor _Q1 is driven through _R2 , and its output is applied to the base terminal of the transistor _Q2 through the coupling capacitor C2, and the output is applied to the base terminal of the transistor _Q2 through the coupling capacitor C2.
When a negative voltage is applied to the transistor Q2, the transistor _Q2 is driven through the resistor _R4 , so its output excites the primary winding of the transformer TF. The transformer TF has two windings T ₁ and T ₂ , the output of each winding is rectified by diodes D ₁₀ and D ₁₁ , and then connected to capacitor C ₃
and C ₄ and output as a DC positive voltage signal from terminals c ₁ and c ₂ .

In this way, if any one of terminals a, b, and e is not input, no DC signal is output from terminals c ₁ and c ₂ , so output c ₁ or c ₂ is the positive and negative input of inputs a, b, and e, respectively. It becomes a logical product (AND).
Moreover, even if any of the components fails, the DC output is likely to disappear, so the circuit shown in FIG. 2 is, after all, an asymmetric error logic circuit.

On the other hand, the asymmetric error logic circuit in FIG. 3 sets the negative voltage input terminal e in FIG. 2 to a positive polarity voltage,
Moreover, it was obtained by making the transistor Q ₂ an NPN type transistor and connecting it to the positive input terminal b. In this way, the output c in the case of FIG. 3 is the logical product of only the positive inputs of inputs a and b. In addition, the third
The figure omits what corresponds to the resistor R ₄ in FIG. 2.

Although the asymmetric error logic circuit described above has a novel configuration disclosed for the first time in this specification, these are merely examples of those that can be used in the present invention. Other examples of asymmetric error logic circuits are
These are disclosed in Japanese Patent Publication No. 45-29054 and Japanese Patent Publication No. 48-30777, and these can also be used in the present invention.

In the configuration of the counting device as described above, each terminal c of the memory circuits LS ₁ to LS ₄ constituting the memory circuit MY
The outputs CV ₁ to _{CV 4} are fed back to the positive input terminal a to form a self-holding circuit, and at the same time, the counting input signal CP is input to the positive input terminal b of the first stage storage circuit LS ₁ , and the second stage Signals ST 1 to ST 3 from the steering gate circuit STG are input to the positive input terminals b of the subsequent memory circuits LS ₂ to _{LS 4} , and signals ST ₁ to _{ST 3} from the steering gate circuit STG are input to each positive input terminal a via diodes D ₄ to _{D 7} . Signal RS is now input.

Therefore, when a positive voltage signal is input to each terminal a while a positive voltage is applied to each terminal b, the oscillation circuit 1 of each memory circuit LS ₁ to _{LS 4} oscillates, and the amplifier and rectifier DC positive voltage signals CV ₁ to _{CV 4} are output from terminal c through the terminal c, and this is fed back to terminal a, so from now on, the diode of terminal a
Even if the positive voltage input signals from D ₄ to _{D 7} disappear, the memory circuits LS ₁ to LS ₄ continue to oscillate, and the outputs CV ₁ to _{CV 4} also maintain positive voltage. In other words, even if the preset signal RS becomes 0V after the outputs CV ₁ to _{CV 4} of the storage device MY have once become a positive voltage, the outputs CV ₁ to _{CV 4} maintain the positive voltage.

On the other hand, the gate circuits G ₁ to _{G 3} of the steering gate circuit STG receive the counting input signal CP (negative voltage)
Each time input, the corresponding memory circuit LS ₁ ~ _{LS 4}
It is determined whether or not it should be set based on the output condition of the previous stage storage circuit, and when it should be set, it outputs 0V signals _ST1 to _ST4 .

Next, based on the configuration and function of each of the circuits described above, the operation of the counting device will be explained using the time chart shown in FIG. 1A.

As shown in the figure, the count input signal
When a positive preset signal RS is input while CP is at a positive voltage (see b in the same figure), the memory circuit LS ₁
the second input terminal b of the memory circuits LS ₂ to LS ₄
Since the positive polarity voltage of the counting input signal CP is also applied to the input terminal b of the memory circuits LS 1 to LS 4 via the diodes D ₁ to _{D 3} , from the output terminal c of the memory circuits LS ₁ to _{LS 4} ,
As shown in charts C, H, G, and R of FIG. 1A, positive polarity voltage outputs CV ₁ to CV ₄ are generated in one cycle. Since the positive polarity voltage is fed back from the output terminal c to the input terminal a, even if the positive polarity preset pulse signal RS disappears, the output voltage CV ₁
~CV ₄ does not disappear and is self-maintained.

Furthermore, the asymmetric error AND circuits AL ₁ to AL ₃ of the gate circuits G ₁ to _{G 3} respectively output the negative polarity voltage signal of the count input signal CP and the output voltage signals CV ₁ to CV of the previous stage storage circuits LS ₁ to LS ₄ . ₃ , and the positive polarity voltage is applied to the input terminals a and b from the outputs _c2 of the asymmetric error AND circuits _AL1 to _AL3 .
While the counting input signal CP is a negative polarity voltage, even if the output voltages CV ₁ to _{CV 3} of the memory circuit change from positive polarity voltage to 0 voltage, the outputs c ₁ and c ₂ are self-maintained and do not disappear.

Now, with the memory device MY preset as described above and the memory circuits LS ₁ to _{LS 4} outputting positive voltage outputs, the first counting input signal CP ₁ is output as shown in the chart of FIG. 1A. (negative voltage), the AND condition of the input terminals a and b of the first stage memory circuit LS ₁ will not be satisfied, so the output CV ₁ will be
The voltage becomes 0V (see figure C), and the output side of the memory circuit includes a rectifier circuit, so the fall is slow as shown in the figure. ), and at the same time the counting input signal CP
The negative voltages are also input to the negative input terminals e of the asymmetric error AND circuits AL ₁ to _{AL 3} of the respective gate circuits G ₁ to _{G 3} .

In the gate circuit G ₁ , the previous stage memory circuit LS ₁
The output CV ₁ from the output terminal is 0V, but the output terminal
It is self-maintained by the output of _c2 , and also has a gate circuit.
G ₂ and G ₃ are positive polarity voltages CV ₂ ,
Since CV ₃ is occurring, the asymmetric error AND circuit
Positive voltage is generated at the outputs ST ₂ and ST ₃ of AL ₂ and LA ₃ . Then, when the counting input signal CP returns to a positive voltage, it is applied to the terminals b of the memory circuits LS ₁ -LS ₄ via the diodes D ₁ -D ₃ , so that the outputs of the memory device MY CV ₂ -CV ₄ is maintained at a positive voltage. However, in the memory circuit LS ₁ , even if a positive voltage is applied to terminal b, no positive voltage is applied to terminal a, so
The output CV ₁ remains at zero voltage. Since the input of the input terminal e of the asymmetric error AND circuit AL ₁ of the gate circuit G ₁ becomes a positive voltage, its outputs c ₁ and c ₂ disappear as shown in FIG. 1A.

In this state, the second count input signal CP ₂
(negative voltage) is input, since at this time no positive voltage is input to terminals a and b of the asymmetric error AND circuit AL ₁ , the positive polarity voltage signal ST ₁ from the circuit AL ₁ disappears. As a result, the output CV ₂ of the storage device MY becomes 0V (chat), but the output
In the same way as when CV ₁ becomes 0V, the outputs CV ₃ and CV ₄
maintains a positive voltage. In this way, by inputting the second count input signal CP ₂ (negative voltage), the memory circuit
The output CV ₂ of MY becomes 0, and the output CV 3 becomes 0 due to the third counting input signal CP ₃ , and the output CV becomes ₀ due to the fourth counting input signal CP ₄ . ₄ becomes 0.

In this way, according to the input of the counting input signal CP (negative voltage), the asymmetric error AND circuit of the memory circuit MY
LS ₁ to LS ₄ are reset in sequence, and the signals CV ₁ , CV ₂ ,
CV ₃ and CV ₄ change from positive voltage to 0V and are sequentially output. Then, the next positive polarity voltage is generated at the outputs CV ₁ , CV ₂ , CV ₃ , and CV ₄ under the preset conditions, that is, when the count input signal CP becomes a positive voltage and,
Only when the preset pulse signal RS (positive voltage) is input.

Note that here, the gate circuits G ₁ to _{G 3} are connected to the storage device before the negative voltage count input signal CP is input.
As mentioned above, the signals ST ₁ to ST ₃ do not disappear until after the signals CV ₁ to _{CV 3} in the previous stage of MY change to 0V, and the sequential specification operation of the bits to be stored is ensured. This is a steering gate circuit.

As mentioned above, the storage circuit LS ₁ of the storage device MY
~LS ₄ is a circuit as shown in Figure 3, so even if a failure occurs in each circuit, its output CV ₁ ~ _{CV 4}
is not a positive voltage. Furthermore, if the feedback line between terminals c and a is disconnected, it will no longer be able to self-hold, and its outputs CV ₁ to _{CV 4} will not maintain a positive voltage, and the set signal and preset signal will not be maintained.
When each line of RS is disconnected, the memory circuits LS ₁ to _{LS 4}
does not operate in oscillation, so its outputs CV ₁ to _{CV 4} cannot be positive voltages.

On the other hand, since the asymmetric error AND circuits AL ₁ to _{AL 6} constituting the steering gate circuit STG are circuits as shown in FIG. 2, even if a failure occurs in each circuit, the outputs ST ₁ to _{ST 3} is never a positive voltage, and the steering gate circuit STG
Even if a disconnection fault occurs in the input/output line of the input/output line, the signals ST ₁ to _{ST 3} will never become a positive voltage. The same applies when an open circuit failure or a short circuit failure occurs in the diodes D ₁ to D ₇ , and the output signals CV ₁ to D 7 are
CV ₄ will never be a positive voltage.

In addition, in the above embodiment, the diodes D ₁ to
For example, D ₇ can be configured by an AND circuit as shown in FIG. 4, and there are various specific gate circuit configurations. Also, the transistors in FIGS. 2 and 3 are changed from PNP type to NPN type, or vice versa, and the diodes D ₁₀ and D ₁₁ are reversed.
Input terminals a, b of positive input voltage are connected to negative input terminals n, m
and input terminal e is set as positive voltage input terminal l, then
As shown in FIGS. 5 and 6, an asymmetric error AND circuit that outputs a negative voltage can be used. Using such an asymmetric error AND circuit, the diodes D ₁ to D ₇ in Figure 1 are reversed, and the input signals CP,
Even if the polarity of RS is reversed, a counting device with the same function can be obtained. FIG. 7 shows the circuit in this case.

As described above, in the counting device according to the present invention, even if a failure or disconnection occurs in any of the component circuits, feedback lines, set signal lines, and preset signal lines, the output voltage of each memory circuit disappears. Indicates an asymmetric failure mode. Then, the count value advances only when the output voltages of the memory circuits in each stage disappear one after another. Therefore, it is possible to provide a fail-safe counting device that has a characteristic that the count value advances due to a circuit failure, that is, a fail-safe counting device that fails on the safe side.

When such a counting device is used, for example, to count the axles of an approaching train, fail-safe performance of train detection is guaranteed. However, the application of the invention is not limited to the above examples.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 1A is a time chart showing waveforms of the main parts of FIG. 1, and FIGS. 2 and 3 are asymmetric error logic used in the present invention, respectively. A circuit diagram showing an example of the circuit, FIG. 4 is a diagram showing an equivalent circuit of a diode. Figures 5 and 6 are circuit diagrams showing examples of asymmetric error logic circuits when the polarity is reversed in Figures 2 and 3, respectively, and Figure 7 is a counting device when the polarity is similarly reversed. FIG. STG...Steering gate circuit, MY...Storage device, _G1 to _G3 ...Gate circuit, _AL1 to _AL6 ...Asymmetric error AND circuit, _LS1 to _LS4 ...Storage circuit.

Claims (1)

[Scope of Claims] 1 (a) Outputs the preset signal inputted to the first input terminal via the backflow prevention circuit and the set signal inputted to the second input terminal, and outputs the output from the first input terminal. A storage device comprising n-stage storage circuits configured in parallel with an asymmetric error AND circuit that is fed back to a terminal and self-maintained; and the storage circuit i (i=2, 3,...,n) in the storage device, respectively.
an asymmetric error AND circuit that stores and outputs the output voltage of the previous stage storage circuit by ANDing it with the output voltage of the previous stage, i.e., the i-1st stage storage circuit; (c) a steering gate circuit comprising n-1 stages of gate circuits in parallel, each having a logic gate that bypasses a voltage signal having a polarity of (c) a second input terminal of the first stage storage circuit of the storage device; The voltage of the polarity when counting is not to be performed among the counting input signals is inputted as the set signal, and the asymmetric voltage of the gate circuit corresponding to the memory circuit is inputted to the second input terminal of the memory circuit of the second stage and below. A fail-safe counting device configured by connecting an output signal of an error AND circuit and a bypass signal of the logic gate so that they are respectively input as the set signal.