JPH01136423A - Unipolar/bipolar conversion circuit - Google Patents

Abstract

PURPOSE:To prevent completely a circuit fault such as secondary component defect due to clock interference by providing a NAND means obtaining NAND of outputs of an input interruption detection circuit to a clock input section of a unipolar/bipolar main conversion circuit. CONSTITUTION:A NAND circuit using a clock as one clock is inserted between the clock input of a NOR circuit and an output of a terminal Q of a one-shot multivibrator 6. If the clock is interrupted, the B input terminal of the one-shot multivibrator 6 is interrupted, the output of the Q terminal being so far at '0' goes to '1' after the interruption detection time t1 and an alarm of input interruption is sent externally via an inverter 7. Simultaneously, outputs of NOR circuits 1, 2 go to '0' without fail, transistors 3, 4 are turned off. As a result, the damage to the transistors is completely prevented.

Description

[Detailed Description of the Invention] [1 Already Required] Regarding a unipolar/bipolar conversion circuit (hereinafter referred to as a U/B conversion circuit) for main transmission signals used in a digital terminal device, a clock disconnection failure occurs in the above circuit. Our goal is to provide a U/B conversion circuit that completely prevents secondary circuit failures (part damage, etc.) caused by NRZ encoding with a simple circuit configuration. The υ/B main conversion circuit inputs ``1#'' data alternately to two input terminals every clock and outputs RZ-encoded bipolar data, and the input data is input from the branch output of one of the input terminals. and an input disconnection detection circuit that detects disconnection.
In the /B conversion circuit, the clock input section of the U/B main conversion circuit is provided with a NAND means for calculating the NAND of the clock and the output of the input disconnection detection circuit, and the output of the NAND means is used as the clock to perform the above U/B conversion circuit. /B It is configured to be input to the main conversion circuit.

[Industrial application field]

The present invention relates to an improvement of an II/B conversion circuit for main transmission signals used in digital terminal equipment.

In the above circuit, there is a need for a U/B conversion circuit that can completely prevent secondary circuit failures (damage of parts, etc.) due to clock disconnection failures with a simple circuit configuration.

[Conventional technology]

FIG. 4 is a block diagram of a conventional U/B conversion circuit.

FIG. 5 is a time chart illustrating a conventional example.

In FIG. 4, NRZ encoded data "1" is alternately applied to one input terminal of NOR circuits 1 and 2 every clock. (■PPCM and ■NPCM shown in FIG. 5 are inverted because of negative logic). The clock input section of NOR circuits 1 and 2 is connected to the clock (CLK) shown in Figure 5.
Add. Due to the characteristics of the NOR circuit that outputs "1" only when the two inputs are both 0", the outputs of NOR circuits 1 and 2 are obtained as shown in Figure 5 (■) and (■). This "1"
The output of is applied to the bases of transistors (hereinafter referred to as Tr) 3 and 4, turning on Tr 3 and 4 alternately. Then, current flows from the power supply (+5 V) through the midpoint of the transformer 5 to the Tr 3 and 4.

As a result, a current flows in the reverse direction on the secondary side of the transformer 5, and a bipolar output as shown in FIG. 5 is obtained.

Now, the branch output of the input terminal of the NOR circuit 1 is connected to the input terminal B of the 1-shot multi-by-break 6 in the input disconnection detection circuit 9.
In addition, when there is no logic change in the input data to B within an arbitrarily set time (for example, t1 seconds), it is determined that the input is disconnected, and then "1" is output and "θ" is output via the inverter 7.
An alarm is generated by outputting .

[Problem that the invention seeks to solve]

However, in the above-mentioned U/B conversion circuit, when the clock is cut off due to a circuit failure or the like, an excessive current flows through the transistor as shown in FIG. 5, resulting in damage to the transistor.

Therefore, it is an object of the present invention to provide a U/B conversion circuit that completely prevents secondary circuit failures (damage of parts, etc.) due to clock disconnection failures with a simple circuit configuration.

[Means for solving problems]

The above problem is solved by the circuit configuration shown in FIG.

In other words, in FIG. 1, the unipolar signal inputs NRZ-encoded unipolar "1#" data consisting of 1" and 60" alternately to two input terminals every clock, and outputs RZ-encoded bipolar data. /In a unipolar/bipolar converter circuit having a bipolar main converter circuit 80 and an input disconnection detection circuit 90 that detects an input data disconnection from a branch output of one of the input terminals, 15 is a clock input of the unipolar/bipolar main converter circuit 80. established in the department,
This is NAND means for calculating the NAND of the clock and the output of the input disconnection detection circuit.

The output of the NAND means 15 is then inputted to the unipolar/bipolar main conversion circuit 80 as a clock.

[For production]

In FIG. 1, an input disconnection detection circuit 90 when the clock is disconnected
The input data to is also disconnected, and the input data has a constant logical value (O'') at a predetermined time. By inputting this output to the NAND means 15 together with the clock (O''), The output of the NAND means 15 is “1”
” becomes.

On the other hand, NO in the unipolar/bipolar main conversion circuit 80
By inputting the above output “1” to the R circuit, the NOR
The output of the circuit becomes 0'', which turns off the transistor connected to the NOR circuit, thereby preventing damage to the transistor.

〔Example〕

FIG. 2 is a block diagram of a U/B conversion circuit according to an embodiment of the present invention.

FIG. 3 is a time chart explaining the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the present invention differs from the conventional example in that an NA circuit with a clock as one input is connected between the clock input of the NOR circuit and the output of the Q terminal of the one-shot multivibrator 6.
This is because an ND circuit was inserted.

This will be explained in detail below.

Assume that the clock applied to one input terminal of the NAND circuit 10 is, for example, "1". On the other hand, as explained in the conventional example, if there is a logic change during the arbitrary time t1 seconds of the one-shot multi-bye break 6 and the input to the B terminal is not interrupted, the third
As shown in the figure (■), the Q terminal outputs "1". This output is applied to one input terminal of the NAND circuit IO. A clock (CLK) is applied to the other input terminal a. CLK
For example, when the input is "1", the NAND circuit outputs "O" only when all inputs are "1", so in this case it outputs "θ".

This is shown in Figure 3 (■).

The "0" output of this NAND circuit 10 is connected to the NOR circuit 1.
Add to the clock input section of 2. The other input terminal has PP
CM and NPCM are added, but as shown in Figure 3 ■ and ■, "1" is output when "Yes" and "100" are respectively "0", and "0" is output when "100" is "1".As a result, As in the conventional example, a bipolar output is obtained on the secondary side of the transformer 5, as shown in FIG.

Now, when the clock is cut off, the PPCM and NPCM are also cut off, as shown in FIG. At this time,
Lower PCM (■) and NAND circuit output (■) are both “O”
Considering the case of n, the output of the NOR circuit 1 is "1", the Tr 3 is always on, and an excessive current flows through the Tr 3.

However, since the B input terminal of the 1-shot multipipe rake 6 is also disconnected, after the disconnection detection time t1 seconds,
The output of the Q terminal, which was ``, becomes ``1,'' and an input disconnection alarm is sent to the outside via the inverter 7.At the same time, the Q
The output of the terminal changes from "1" to "0" as shown in Figure 3 (■), and the output of the NAND circuit 10 always becomes "1'" as shown in Figure 3 (■). Therefore, the outputs of NOR circuits 1 and 2 Also, regardless of the input group and the logic value of Akira, it is always “On”.
becomes. That is, Tr 3 and Tr 4 are turned off.

As a result, damage to the Tr can be completely prevented.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to completely prevent secondary circuit failures (damage of parts, etc.) due to clock disconnection failures in the above-mentioned U/B conversion circuit with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a configuration diagram of a U/B conversion circuit according to an embodiment of the present invention, Fig. 3 is a time chart explaining the embodiment, and Fig. 4 is a U/B conversion circuit of a conventional example. A block diagram of the B conversion circuit, and FIG. 5 is a time chart illustrating a conventional example. In the figure, 15 is a NAND means, 80 is a unipolar/bipolar main conversion circuit, and 90 is an input disconnection detection circuit.

Claims (1)

[Claims] Unipolar/bipolar main conversion that inputs NRZ-encoded unipolar "1" data consisting of "1" and "0" alternately to two input terminals every clock, and outputs RZ-encoded bipolar data. In the unipolar/bipolar conversion circuit comprising a circuit (80) and an input disconnection detection circuit (90) that detects disconnection of input data from one branch output of the input terminal, the unipolar/bipolar main conversion circuit (80) The clock input section is provided with a NAND means (15) for calculating the NAND of the clock and the output of the input disconnection detection circuit, and the unipolar/bipolar main conversion is performed using the output of the NAND means (15) as a clock. A unipolar/bipolar conversion circuit characterized in that an input is input to a circuit (80).