JPS58207755A - Detecting circuit of polarity inversion - Google Patents

Detecting circuit of polarity inversion

Info

Publication number
JPS58207755A
JPS58207755A JP1816582A JP1816582A JPS58207755A JP S58207755 A JPS58207755 A JP S58207755A JP 1816582 A JP1816582 A JP 1816582A JP 1816582 A JP1816582 A JP 1816582A JP S58207755 A JPS58207755 A JP S58207755A
Authority
JP
Japan
Prior art keywords
circuit
polarity
bistable circuit
line
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1816582A
Other languages
Japanese (ja)
Inventor
Akihiro Kobayashi
小林 暁洋
Yutaka Nishino
豊 西野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iwatsu Electric Co Ltd
Nippon Telegraph and Telephone Corp
Iwasaki Tsushinki KK
Original Assignee
Iwatsu Electric Co Ltd
Nippon Telegraph and Telephone Corp
Iwasaki Tsushinki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iwatsu Electric Co Ltd, Nippon Telegraph and Telephone Corp, Iwasaki Tsushinki KK filed Critical Iwatsu Electric Co Ltd
Priority to JP1816582A priority Critical patent/JPS58207755A/en
Publication of JPS58207755A publication Critical patent/JPS58207755A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M1/00Substation equipment, e.g. for use by subscribers
    • H04M1/82Line monitoring circuits for call progress or status discrimination

Abstract

PURPOSE:To detect accurately the polarity inversion only, by providing an FF storing the polarity of a communication line so as to prevent malfunction due to the transmission of a dial pulse intermitting a DC loop or hit of DC supply on the way of exchange. CONSTITUTION:A hook switch 2 is connected to a connecting terminal L1 of a telephone set, a series circuit comprising a telephone set circuit 1 and a power supply circuit 7 is connected between the other connecting terminal L2 and the switch 2 via a diode bridge DB for polarity coincidence, and a power supply tV is applied to each section from the circuit 7 in closing the switch 2. FF1, FF2 as bistable circuits are connected to the output side of the bridge DB respectively via diodes D1, D2 and transistors TRQ11, Q12 respectively. The FF1, FF2 are reset after the supply of a power supply +B with an output of a power- on reset circuit 6. When a pair of terminals L1, L2 has a prescribed polarity, the FF1 or FF2 is set, the outputs of the FF1, FF2 are ANDed at an AND circuit AND, allowing to detect accurately the polarity inversion.

Description

【発明の詳細な説明】 本発明は通信回線の極性反転を検出する回路に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for detecting polarity reversal of a communication line.

通話回線に接続された電話機から発呼操作を行ったとき
被呼者が応答すると、交換機の動作により回線の極性が
反転する。この反転状態は通話中継続し、終話のため回
線を復旧すると極性は再度反転される。
When a call is made from a telephone connected to a telephone line and the called party answers, the polarity of the line is reversed by the action of the exchange. This reversed state continues during the call, and when the line is restored to end the call, the polarity is reversed again.

第1図はこのような極性反転を検出するだめの従来の回
路の1例であり、Ll、L2は電話機と線路との接続端
子、1は電話機回路、2はフックスイッチ、3はダイオ
ードブリッジ、4はダイオード、5はリレー、6はコン
デンサである。第1図の回路において、Llの極性がプ
ラスでり、の極性がマイナスの状態の場合に電圧が印加
された時には、ダイオード4は順方向となり、リレー5
を短絡するだめリレー5は動作しないが、Ll + t
、2に印加さね%JLt圧が前記の状態から反転される
と、リレー5は動作し、リレー5の接点(図示していな
い)により極性が反転したことを検出することができる
Figure 1 shows an example of a conventional circuit for detecting such polarity reversal, in which Ll and L2 are connection terminals between the telephone and the line, 1 is the telephone circuit, 2 is a hook switch, 3 is a diode bridge, 4 is a diode, 5 is a relay, and 6 is a capacitor. In the circuit shown in Fig. 1, when voltage is applied when the polarity of Ll is positive and the polarity of Ll is negative, diode 4 becomes forward direction, and relay 5
Relay 5 will not work unless short-circuited, but Ll + t
, 2 is reversed from the above state, the relay 5 is activated and the reversal of polarity can be detected by the contacts (not shown) of the relay 5.

しかし、この方式の第1の欠点は、LIIL2の4枳性
が指定されるため、電話機設置時に線路の極性を確認す
る必要がちり、設置作業がわずられしいことである。
However, the first drawback of this method is that because the LIIL2 4-wire characteristic is specified, it is necessary to check the polarity of the line when installing the telephone, making the installation work cumbersome.

第2の欠点をま、リレーが動作している状態で11流ル
ープを断続するダイヤルインパルス信号の送出・を行な
うと、ダイヤルインパルスに同101 してリレー5が
オフ・オンを繰り返すため、この間(d転、面信号とは
みなさないための特別な回路が必要であり、実用化には
回路構成が複雑になることである0 第3の欠点は、リレー5の巻線抵抗外だけ電話機の直流
抵抗が増加し、電話機への直流供給電流が減少し、通話
性能が1氏トすることである。
Regarding the second drawback, if you send out a dial impulse signal that intermittents the 11 flow loop while the relay is operating, the relay 5 will repeatedly turn off and on at the same time as the dial impulse. A special circuit is required to prevent D-turn and surface signals from being treated as signals, and the circuit configuration becomes complicated for practical use.The third drawback is that the direct current of the telephone only exceeds the winding resistance of the relay 5. The resistance increases, the DC supply current to the telephone decreases, and the call performance deteriorates by 1 degree.

第4の欠点は、リレー5の挿入による交流(1+失増加
をおさえるためリレー5と並列に人容に1のコンデ/す
6を必要とし、装置の小形化が、困難であることである
The fourth drawback is that in order to suppress the increase in alternating current (+1) loss caused by the insertion of the relay 5, a 1-unit AC/DC 6 is required in parallel with the relay 5, making it difficult to downsize the device.

本発明は、これらの欠点を除去し、設置時に回線の極性
を指定することなく、安定した極性反転検出出力が得ら
れる極性反転検知回路を提供するものである。
The present invention eliminates these drawbacks and provides a polarity reversal detection circuit that can provide a stable polarity reversal detection output without specifying the polarity of the line at the time of installation.

以下本発明の詳細な説明する。The present invention will be explained in detail below.

第2図は本発明の一実施例であって、IJI + Ll
は電話機の接続端子、DBは極性−飲用のダイオードブ
リッジ、lは電話機回路、7は電源回路、6はパワーオ
ンリセット回路、ANDはアンド回路、FF、、FF2
は二安定回路としての7リツプ・フロップ、Qlt +
 Q12はトランジスタ、R1+ R2+ R3+ R
4は抵抗、DI + D2はダイオード、自はコンデン
サ、OUTは転極検出出力端子である。
FIG. 2 shows an embodiment of the present invention, in which IJI + Ll
is the telephone connection terminal, DB is the polarity-potable diode bridge, l is the telephone circuit, 7 is the power supply circuit, 6 is the power-on reset circuit, AND is the AND circuit, FF, FF2
is a 7-lip-flop as a bistable circuit, Qlt +
Q12 is a transistor, R1+ R2+ R3+ R
4 is a resistor, DI + D2 is a diode, self is a capacitor, and OUT is a polarity reversal detection output terminal.

この実施例において、フックスイッチ2が閉じると、L
l又はLlから〔ダイオードブリッジDB→電話機回路
1→電源回路7〕の経路を通してLl又はLlへの直流
ループが閉結され、電源回路7により各部にV+の′電
源が供給される。パワーオンリセット回路6は電源が供
給された時一定時間のり七ノド出力を発生する回路であ
り、リセット出力によりフリップ・フロップFF、及び
FF2はリセットされる。
In this embodiment, when the hook switch 2 is closed, L
A DC loop from Ll or Ll to Ll or Ll is closed through the path [diode bridge DB→telephone circuit 1→power supply circuit 7], and the power supply circuit 7 supplies V+' power to each part. The power-on reset circuit 6 is a circuit that generates an output for a certain period of time when power is supplied, and the flip-flops FF and FF2 are reset by the reset output.

トランジスタQllのベースはダイオードDIと抵抗R
8を通してり、端子側に接続され、トランジスタQ1□
のベースはダイオードD2+抵抗R2を通してL2端r
・側へ接続されている。
The base of transistor Qll is connected to diode DI and resistor R.
8, connected to the terminal side, and transistor Q1□
The base of is connected to L2 terminal r through diode D2 + resistor R2.
・Connected to the side.

従って、′電話機端子Ll e Llの極性がLl側プ
ラス、L2側マイナスであれば、トランジスタQnはオ
ンであり、フリップ・フロップFF、はセットされず、
トランジスタQ12はオフであり、クリップ・フロップ
FF2のセット入力端子S2はハイレベルとなり、クリ
ップ・フロップFF2はセントされ、出力Q2は・・イ
レベルとなる。
Therefore, if the polarity of the telephone terminal Ll e Ll is positive on the Ll side and negative on the L2 side, the transistor Qn is on and the flip-flop FF is not set.
The transistor Q12 is off, the set input terminal S2 of the clip-flop FF2 becomes high level, the clip-flop FF2 is set, and the output Q2 becomes low level.

次に回線の極性が反転し、Ll側マイナス+L2側プラ
スとなると、前述の状態とは逆にトランジスタQoがオ
フとなり、フリップ・フロップFF1がヒツトされ、Q
Hの出力は/・イレベルとなる。極性反転により、フリ
ップ・フロップFF、 、 FF2の各出力Q+ 、 
Q2が共に7・イレベルとなり、AND回路を通して転
滲検出出力を得ることができる。
Next, when the polarity of the line is reversed and becomes negative on the Ll side and positive on the L2 side, the transistor Qo turns off, contrary to the above state, flip-flop FF1 is hit, and the Q
The output of H becomes /.level. By reversing the polarity, each output Q+ of the flip-flops FF, , FF2,
Q2 are both at the 7-level level, and a leakage detection output can be obtained through the AND circuit.

コ/テンサ自は交換+1 fillで極性を反転したり
、あるいはトランク接続替え時に生ずる直流電流の瞬断
に対してV+電源を一定値以下に低下させないためのコ
ンデンサである。
The capacitor is a capacitor that prevents the V+ power supply from dropping below a certain value when the polarity is reversed when replacing +1 fill or when there is a momentary interruption of DC current that occurs when switching trunk connections.

第3図は本発明の他の実施例で、MMはモノマルチバイ
ブレータ、ORはOR回路である。第3図は、第2図の
回路構成に、さらにAND回路の出力が・・イレベルに
なると一定時間・・イレベルの出力を発生するモノマル
チバイブレータMMを接続し、その出力を極性反転検出
出力パルスとすると共にOR回路を通してフリップ・フ
τffツブFFl l FF2 ラリセットするように
構成されている。
FIG. 3 shows another embodiment of the present invention, in which MM is a monomultivibrator and OR is an OR circuit. In Figure 3, a mono multivibrator MM is connected to the circuit configuration shown in Figure 2, which generates an output at E level for a certain period of time when the output of the AND circuit becomes E level, and its output is used as a polarity reversal detection output pulse. At the same time, the flip-flop τff knob FFl l FF2 is reset through an OR circuit.

従って、2回目以降の転極があっても、前述の説明と同
様の動作で転極検出出力パルスを得ることができる。
Therefore, even if there is a second or subsequent polarity reversal, a polarity reversal detection output pulse can be obtained by the same operation as described above.

h”r 4図は本発明の他の実施例であり、EはMi:
 幹、pct 、 PO2はホトカプラR5は抵抗であ
る。第2図。
h”r Figure 4 shows another embodiment of the present invention, where E is Mi:
Stem, pct, PO2 is photocoupler R5 is a resistor. Figure 2.

第3図が電話機の直流ループ内に電源回路を設は回路を
動作させる局電源動作型であるのに対して、第4図の実
施例は、外部電源を使用するものであり、電話機側の電
源との分離をフォトカブラl)C,。
While the embodiment shown in Fig. 3 is a station power operated type in which a power supply circuit is installed in the telephone's DC loop to operate the circuit, the embodiment shown in Fig. 4 uses an external power supply, and the power supply circuit is operated on the telephone side. Photocoupler for separation from the power supply l)C.

PO2により行なうように構成されている。It is configured to be carried out by PO2.

第5図は本発明のさらに他の実施例であり、二安定回路
にサイリスタを「重用したものである。絹5図において
、SCR,、5CR2はサイリスタ、QIIIQ12は
゛トランジスタ、R11+R12* RI3 + RI
4は抵抗、INVはインバータであり、その他の記号は
第1図から第4図までの実施例における記号と同一であ
る。この実施例では、二安定回路としてサイリスタSC
R,、5CIt2を使用したため、サイリスタをリヒノ
ト(オフ状状態)する手段として、トランジスタQ11
1QI2をサイリスタ5CR4、5CR2と並列に接続
した構成としている。
Figure 5 shows still another embodiment of the present invention, in which a thyristor is heavily used in a bistable circuit. In Figure 5, SCR, 5CR2 are thyristors, QIIIQ12 is a transistor, R11 + R12 * RI3 + RI
4 is a resistor, INV is an inverter, and other symbols are the same as those in the embodiments shown in FIGS. 1 to 4. In this example, a thyristor SC is used as a bistable circuit.
Since R,,5CIt2 is used, the transistor Q11 is used as a means to turn off the thyristor.
1QI2 is connected in parallel with thyristors 5CR4 and 5CR2.

以上詳細に説明したように1本発明は電話機の直流抵抗
を増加することなく、線路の極性を記1、・するフリッ
プ・フロップを有する構成であるため、直流ループを断
続するダイヤルインパルス(i 号の送出を行っても、
あるいは、交換接続途中での直流供給の瞬断等があって
も、誤動作することなく、極性反転があった時のみ正確
な転極検出出力をmることができるので、通話時間の割
数装置、自動メツセージ送出装置等幅広い分野での応用
が11丁能・である。
As explained in detail above, the present invention has a configuration having a flip-flop that marks the polarity of the line without increasing the DC resistance of the telephone. Even if you send
Alternatively, even if there is a momentary interruption of the DC supply during the exchange connection, there will be no malfunction, and an accurate polarity reversal detection output can be made only when there is a polarity reversal. It has 11 applications in a wide range of fields such as automatic message sending devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の転極検出回路の回路構成例を示すブロッ
クを含む回路図、第2図、第3図、第4図及び第5図は
本発明の一実施例を示すブロックを含む回路図である。 特許出願人  岩崎通信機株式会社 同    日本電信電話公社 代理人 大塚 学 同      昌  水  常  雄 ′f73  幻 第 4  図 手続補正書(方式) 昭和58年7月7 日 特許庁長官 若 杉 和 夫 殿 1 事件の表示 特願昭57−18165号 2 発明の名称 極性反転検知回路 3 補正をする者 事件との関係 出願人 (01B)岩崎通信機株式会社 東京都新宿区西新宿1=23−1 「発明の詳細な説明」の欄 明細書を次のように訂正す゛る。 (1、発明の名称を「極性反転検知回路」に訂+T゛す
る0 (2、特許請求の範囲の欄を別紙のように訂正、する。 (3)第2頁第8行「検出」を「検知」に訂正する。 特許請求の範囲 (1)一対の線路の一方の片線の極性が予め定V)だプ
ラス又はマイナスの極性の時にセットされる第1の二安
定回路と、前記一対の線路の他力の片線の極性が予め定
めたプラス又はマイナスの極性の時にセントされる第2
の二安定回路と、前記第1の二安定回路と前記第2の二
安定回路の出力の論理積をとって前記一対の線路の極性
反転の検出出力とする論理積回路とを“備えた極性反転
検知回路。 (2)一対の線路の一方の片線の極性が予め定めだプラ
ス又はマイナスの極性の時にセットされる第1の二安定
[C11路と、前記一対の線路の他)jの片線の極性が
予め定めたプラス又はマイナスの極性の時にセットされ
る第2の二安定[【11路と、前記第1の二安定回路と
前記第2の二〇安定回路の出力の論理積をとって前記一
対の線路の極f1反転の検出出力とする論理積回路と、
前記検出出力によシ前記第1の二安定回路と前記第2の
二安定回路とをリセットするためのリセット手段とを備
えだ極性反転St<+回路。
FIG. 1 is a circuit diagram including blocks showing an example of the circuit configuration of a conventional polarity reversal detection circuit, and FIGS. 2, 3, 4, and 5 are circuit diagrams including blocks showing an embodiment of the present invention. It is a diagram. Patent Applicant: Iwasaki Tsushinki Co., Ltd., Agent: Nippon Telegraph and Telephone Public Corporation, Manabu Otsuka, Tsuneo Masamizu'f73, Phantom No. 4, Draft Procedure Amendment (Method), July 7, 1980, Commissioner of the Patent Office, Kazuo Wakasugi, Mr. 1 Indication of the case Japanese Patent Application No. 18165/1986 2 Name of the invention Polarity reversal detection circuit 3 Person making the amendment Relationship to the case Applicant (01B) Iwasaki Tsushinki Co., Ltd. 1=23-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo "Invention The description in the column "Detailed explanation of" has been amended as follows. (1. Correct the name of the invention to "Polarity Reversal Detection Circuit." 0. (2. Correct the scope of claims as shown in the attached sheet.) (3) Modify "Detection" in line 8 of page 2. Corrected to "detection." Claims (1) A first bistable circuit that is set when the polarity of one line of the pair of lines is a predetermined positive or negative polarity (V); The second line is sent when the polarity of one line of the other line is a predetermined positive or negative polarity.
a bistable circuit, and an AND circuit that takes the AND of the outputs of the first bistable circuit and the second bistable circuit to provide a detection output of polarity reversal of the pair of lines. Reversal detection circuit. (2) A first bistable circuit (other than C11 and the pair of lines) that is set when the polarity of one line of the pair of lines is a predetermined plus or minus polarity. A second bistable circuit that is set when the polarity of one line is a predetermined plus or minus polarity [[logical product of the 11 path and the outputs of the first bistable circuit and the second bistable circuit] an AND circuit that outputs the detection output of pole f1 inversion of the pair of lines;
A polarity inversion St<+ circuit comprising a reset means for resetting the first bistable circuit and the second bistable circuit according to the detection output.

Claims (2)

【特許請求の範囲】[Claims] (1)一対の線路の一方の片線の極性が予め定めたプラ
ス又はマイナスの極性の時にセットされる第1の二安定
回路と、前記一対の線路の他方の片線の極性が予め定め
たプラス又はマイナスの極性の時にセットされる第2の
二安定回路と、前記第1の二安定回路と前記第2の二安
定回路の出力の論理積をとって前記一対の線路の極性反
転の検出出力とする論理積回路とを備えた極性反転検出
回路。
(1) A first bistable circuit that is set when the polarity of one line of the pair of lines is a predetermined positive or negative polarity, and a first bistable circuit that is set when the polarity of one line of the pair of lines is a predetermined polarity. A second bistable circuit that is set when the polarity is positive or negative, and the outputs of the first bistable circuit and the second bistable circuit are logically ANDed to detect polarity reversal of the pair of lines. A polarity reversal detection circuit equipped with an AND circuit as an output.
(2)一対の線路の一方の片線の極性が予め定めたプラ
ス又はマイナスの極性の時にセットされる第1の二安定
回路と、前記一対の線路の他方の片線の極性が予め定め
たプラス又はマイナスの極性の時にセットされる第2の
二安定回路と、前記第1の二安定回路と前記第2の二安
定回路の出力の論理積をとって前記一対の線路の4夕性
反転の検出出力とする論理積回路と、前記検出出力によ
り前記第1の二安定回路と前記第2の二安定回路とをリ
セットするためのり七ノド手段とを備えた極性反転検出
回路。
(2) A first bistable circuit that is set when the polarity of one line of the pair of lines is a predetermined positive or negative polarity, and a first bistable circuit that is set when the polarity of one line of the pair of lines is a predetermined polarity. A second bistable circuit that is set when the polarity is positive or negative, and the outputs of the first bistable circuit and the second bistable circuit are ANDed to perform quaternary inversion of the pair of lines. A polarity reversal detection circuit comprising: an AND circuit that outputs a detection output; and a gate means for resetting the first bistable circuit and the second bistable circuit using the detection output.
JP1816582A 1982-02-09 1982-02-09 Detecting circuit of polarity inversion Pending JPS58207755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1816582A JPS58207755A (en) 1982-02-09 1982-02-09 Detecting circuit of polarity inversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1816582A JPS58207755A (en) 1982-02-09 1982-02-09 Detecting circuit of polarity inversion

Publications (1)

Publication Number Publication Date
JPS58207755A true JPS58207755A (en) 1983-12-03

Family

ID=11963991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1816582A Pending JPS58207755A (en) 1982-02-09 1982-02-09 Detecting circuit of polarity inversion

Country Status (1)

Country Link
JP (1) JPS58207755A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146560A (en) * 1984-01-11 1985-08-02 Masao Uchiumi Detecting circuit for response of the other party
JPS61161059A (en) * 1985-01-08 1986-07-21 Hashimoto Corp On-hook and off-hook detecting system
JPS63187460U (en) * 1987-05-23 1988-11-30
JPH01227554A (en) * 1988-03-07 1989-09-11 Rohm Co Ltd Polarity inversion detector for telephone circuit
JPH0386649U (en) * 1989-12-22 1991-09-02
WO1998049566A1 (en) * 1997-04-25 1998-11-05 Siemens Aktiengesellschaft Polarity identification circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50156304A (en) * 1974-06-05 1975-12-17
JPS5643859A (en) * 1979-09-18 1981-04-22 Tamura Electric Works Ltd Polarity-inversion-signal detecting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50156304A (en) * 1974-06-05 1975-12-17
JPS5643859A (en) * 1979-09-18 1981-04-22 Tamura Electric Works Ltd Polarity-inversion-signal detecting circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146560A (en) * 1984-01-11 1985-08-02 Masao Uchiumi Detecting circuit for response of the other party
JPS61161059A (en) * 1985-01-08 1986-07-21 Hashimoto Corp On-hook and off-hook detecting system
JPS63187460U (en) * 1987-05-23 1988-11-30
JPH042519Y2 (en) * 1987-05-23 1992-01-28
JPH01227554A (en) * 1988-03-07 1989-09-11 Rohm Co Ltd Polarity inversion detector for telephone circuit
JPH0386649U (en) * 1989-12-22 1991-09-02
WO1998049566A1 (en) * 1997-04-25 1998-11-05 Siemens Aktiengesellschaft Polarity identification circuit

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