JPH0255981B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a subscriber circuit of a telephone exchange, and more particularly to a paging signal sending circuit that sends a paging signal to a subscriber terminal via a subscriber line.

(Prior Art) FIG. 1 is a circuit diagram showing an example of a conventional calling signal sending circuit. DC current is supplied to the subscriber terminal 1 from a current supply circuit 3 via a subscriber line 2. Signals such as voice information are sent to and received from the subscriber terminal 1 via the subscriber line 2 and the current supply circuit 3 with the exchange main body (not shown).

On the other hand, in order to send out a paging signal prior to transmitting and receiving the voice information signal to the subscriber terminal 1, a resistor R ₁ ,
A ringing signal source 5 is connected to one line 6 via a switch 4, and a negative power supply 7 is connected to the other line 8 via a resistor _R2 . The switch 4 has transfer contacts operative to switch between the paging signal source 5 and the ground air.

FIG. 2 is a waveform diagram showing the state of transmission of a paging signal to the subscriber terminal 1, which consists of a period 9 for transmitting earth air and a period 10 for transmitting an alternating current signal, that is, a paging signal, and a combination of both periods. Various call signals are realized by appropriately selecting .

(Problem to be Solved by the Invention) In such a conventional calling signal sending circuit, when the switch 4 switches from the calling signal source 5 to the earth side, the line 6 transmits the calling signal via the resistor _R1 for a certain period of time. A situation arises in which neither the power source 5 nor the earth is connected. At that time, the voltage of the paging signal source 5 at the time the switch 4 was opened remains in the part of the subscriber line 2 or the subscriber terminal 1 that was electrically connected to the paging signal source 5 until just before. Become. This residual voltage gradually starts discharging due to a leak resistance including a ring trip circuit (not shown) in the subscriber line 2, etc., and therefore has a frequency component extremely close to direct current. For this reason, it is connected across the resistor R ₁ ,
Moreover, it has the disadvantage that a ring trip circuit (not shown), which is activated and stops the ringing signal when the voltage at both ends thereof exceeds a certain value, may be erroneously activated.

In this way, the contact of the switch 4 is connected to the calling signal source 5.
In order to eliminate the situation where the device is not connected to the earth and the earth, and to achieve miniaturization, semiconductor switches with a self-current holding function were sometimes used. However, when a semiconductor switch with such a current self-holding function is used to alternately open and close two signals to switch between them, a situation occurs in which both signals are simultaneously applied for a certain period of time. arise.

That is, in the case of a calling signal sending circuit, the calling signal and the earth signal collide with each other in a short-circuited state with low impedance, resulting in destruction of the semiconductor switch.

Further, in the conventional circuit, when an electromagnetic component having a mechanical contact is used as the switch 4 for sending out a calling signal, the power required for driving is large, and furthermore, it is difficult to integrate the switch 4 with other components.

An object of the present invention is to prevent the parts that were electrically connected to the calling signal source until just before from being charged to a potential other than the earth's potential, even if the calling signal is stopped at any timing. It is an object of the present invention to provide a calling signal sending circuit which avoids collision with earth signals and has a configuration suitable for integration.

(Means for Solving the Problem) In order to achieve the above object, the present invention uses a pair of semiconductor elements having a current self-holding function such as pnpn transistors connected in antiparallel as a switch, and a detection circuit for detecting the open/closed state of the semiconductor switch; a delay circuit for delaying a signal from the detection circuit by a time longer than the turn-off time of the semiconductor switch; An exclusive operation circuit is provided which closes the other during a period when one of the two is in an open state.

(Example) Hereinafter, the present invention will be described in detail based on drawings of examples.

FIG. 3 is a circuit diagram showing one embodiment of the present invention. In the following drawings, the same parts as shown in FIG. 1 are denoted by the same reference numerals, and the explanation thereof will be omitted.

Reference numerals 11 and 12 each designate a semiconductor switch having a current self-holding function, which corresponds to the switch 4 shown in FIG. 1 as a pair. In this embodiment, the semiconductor switches 11 and 12 are
pnpn transistors 11a, 11b and 12a,
12b are connected in antiparallel. 13 is an exclusive operation circuit, which includes a first gate drive circuit 13a that drives the semiconductor switch 11, a second gate drive circuit 13b that drives the semiconductor switch 12, and a detection circuit 1.
5, the first delay gate circuit 21, the second delay gate circuit 38, and the control circuit 14.

The detection circuit 15 detects the open and closed states of the semiconductor switches 11 and 12, and transmits the states to the control circuit 1.
4. The control signal from the control circuit 14 is sent to the first gate drive circuit 13a via the first delay gate circuit 21 together with the control signal from the control terminal 20.
and are transmitted to the second gate drive circuit 13b via the second delay gate circuit 38, respectively.

FIG. 4 is a waveform diagram for explaining the operation of this embodiment. The operation of this embodiment will be explained below based on FIGS. 3 and 4.

When sending a paging signal to the subscriber terminal 1, a control signal Tcont having the timing shown in FIG. 4A is applied from the control terminal 20 to the exclusive operation circuit 13.

The low level input voltage of this control signal Tcont turns the semiconductor switch 11 ON and 12 OFF, and the high level input voltage turns the semiconductor switch 11 OFF and 12.
The control circuit output information corresponding to the control terminal input corresponding to ON (T11 in FIG. 4B) and the detection circuit 15 corresponding to the semiconductor switch 11 from the detection circuit
The output information [T12 in FIG. 4C] is inputted to the first delay gate circuit 21 to obtain the first delay gate output information [T13 in FIG. Waveform shaping is performed by the following, and first gate drive output information [T14 in FIG. 4E and T15 in F] is obtained.

At this time, T11 or T13 is the output information change point [fourth
The operation time is delayed compared to the turn-off time of the semiconductor switch 12 shown in FIG.
The waveform-shaped output of the gate drive circuit output information [FIG. 4 E, F] is input to the gate of the semiconductor switch 11 to cause it to operate. Furthermore, by this operation, ON information of the semiconductor switch 11 is transmitted to the detection circuit 15, and output information T22 (FIG. 4H) corresponding to the semiconductor switch 12 is outputted from the detection circuit 15.

Then, the control circuit output information corresponding to the control terminal input [T21 in FIG. 4G] and the output information corresponding to the semiconductor switch 12 from the detection circuit 15 [the fourth
T22 in FIG. H] is input to the second delay gate circuit 38, and the second delay gate output information [T2 in FIG.
3] is waveform-shaped by the second drive gate circuit 13b to obtain second drive circuit output information [T24 in FIG. 4J].

At this time, T21 or T23 is a change point of the output information corresponding to the semiconductor switch 12 from the detection circuit by setting the integration time of CR etc. [the turn-off time of the semiconductor switch 11 shown in FIG. 4H]
The operation time is further delayed [Fig. 4 I].

The waveform-shaped output of the second gate drive circuit output information [FIG. 4J] is input to the gate of the semiconductor switch 12, and the semiconductor switch 12 is operated.

Further, due to this operation, ON information of the semiconductor switch 12 is transmitted to the detection circuit 15, and the T
12 is output from the detection circuit 15, an exclusive operation can be performed corresponding to the control terminal input voltage [FIG. 4 A Tcont], and the output terminal 28
Then, the output voltage [Tout in Figure 4 L] is obtained.

In other words, while the first gate drive circuit output is ON, the semiconductor switch 11 is ON, the semiconductor switch 12 is OFF, and the second gate drive circuit output is ON.
While ON, the semiconductor switch 11 is OFF and the semiconductor switch 12 is ON.

Therefore, when the semiconductor switch 11 is ON, a calling signal is sent from the calling signal source 5 to the semiconductor switch 11 → resistor R ₁ → line 6 → subscriber line 2.
→ Subscriber terminal 1 → Subscriber line 2 → Line 8 → Resistor
The subscriber terminal 1 is called through a loop of R ₂ → negative power supply 7 → earth air.

Next, during the paging signal suspension period, that is, the period when the transmission of the signal from the paging signal source 5 is suspended and the earth signal is transmitted to the subscriber terminal 1, the first gate drive circuit outputs T14 and T15 are OFF, 2 gate drive circuit output T24 turns ON. Therefore, semiconductor switch 11 is opened and semiconductor switch 12 is closed. In this way, when the first gate drive circuit outputs T14 and T15 are ON, the semiconductor switch 11 is turned ON when the second gate drive circuit output T24 is ON.
At times, each of the semiconductor switches 12 becomes conductive, and a calling signal and a ground signal as shown in FIG. 4L are sent to the subscriber terminal 1. At this time, since the semiconductor switches 11 and 12 are composed of semiconductor elements having a current self-holding function such as pnpn transistors, the first gate drive circuit outputs T14 and T1 are shown as dots in FIG. 4L.
5 goes from ON to OFF, the second gate drive circuit output T
Even when the switch 24 is switched from OFF to ON, the current flowing through the semiconductor switch 11 may not immediately become zero due to the current self-holding function.

In this case, the detection circuit 15 detects that the semiconductor switch 11 is still in the closed state,
Driving the semiconductor switch 12 until it reaches the open state after the turn-off time shown in FIG. 4H [FIG. 4J
T24] is not performed.

Therefore, conventionally, semiconductor elements having a current self-holding function are used to repeatedly close and open the current.
Collision between the two signals, which occurs when two signals are sent, does not occur.

FIG. 5 is a circuit diagram showing the embodiment shown in FIG. 3 in more detail.

As described in the explanation of FIG. 3, the circuit configuration is that the semiconductor switches 11 and 12 are constructed by connecting pnpn transistors 11a and 11b and 12a and 12b in antiparallel, respectively. Exclusive operation circuit 13
A control circuit 14 having a control terminal 20 and a pair of first and second semiconductor switches 11 and 12 corresponding to a pair of semiconductor switches 11 and 12 that operate in response to an output from the control circuit 14.
It is comprised of delay gate circuits 21 and 38, and a pair of first and second gate drive circuits 13a and 13b that operate in response to their respective outputs. Furthermore, the exclusive operation circuit 13 controls the semiconductor switches 11 and 12.
NPN transistors 33, 37 and 43, 45 and PNP connected to each gate of the pnpn transistor
transistors 29, 34 and a current mirror input circuit for receiving the outputs of these transistors;
The current mirror output circuit also includes a detection circuit 15 connected to the control circuit 14.

Next, the operation of the embodiment shown in FIG. 5 will be explained.
A control signal Tcont having a timing as shown in FIG. 4A is applied from the terminal 20 to the exclusive operation circuit 13.

Control circuit output information for control terminal inputs where the low level input voltage of the control signal turns semiconductor switch 11 ON and 12 OFF, and the high level input voltage corresponds to semiconductor switch 11 OFF and 12 ON [Figure 4B T11] and the output information from the detection circuit 15 corresponding to the semiconductor switch 11 from the detection circuit [T12 in FIG. 4C] are input to the first delay gate circuit 21, and the first delay gate output information 4
T13 in Figure D] is waveform-shaped by the first gate drive circuit 13a, and the first gate drive output information [T14 in Figure 4 E and T15 in F] is obtained.
and diodes 26, 27 or 23, 24
drive the gate of the semiconductor switch 11 through the
The semiconductor switch 11 is made conductive.

At this time, T11 or T13 is the output information change point corresponding to the semiconductor switch 11 from the detection circuit 15 depending on the setting of the CR integration time [Fig. 4C
The operation time is delayed than the turn-off time of the semiconductor switch 12 shown in FIG. and make them perform the action. Further, by this operation, ON information of the semiconductor switch 11 is transmitted to the detection circuit 15, and output information T22 (FIG. 4H) corresponding to the semiconductor switch 12 is outputted from the detection circuit 15.

Then, the control circuit output information corresponding to the control terminal input [T21 in FIG. 4G] and the output information corresponding to the semiconductor switch 12 from the detection circuit 15 [the fourth
T22 in FIG. H] is input to the second delay gate circuit 38, and the second delay gate output information [T2 in FIG.
3] is waveform-shaped by the second drive gate circuit 13b to obtain second drive circuit output information [T24 in FIG. 4J].

At this time, T21 or T23 delays the operation time from the output information change point corresponding to the semiconductor switch 12 from the detection circuit [the turn-off time of the semiconductor switch 11 shown in FIG. 4H] by setting the CR integration time. Figure 4 I].

The waveform-shaped output of the second gate drive circuit output information [FIG. 4J] is input to the gate of the semiconductor switch 12, and the semiconductor switch 12 is operated.

Further, due to this operation, ON information of the semiconductor switch 12 is transmitted to the detection circuit 15, and the T1
2 is output from the detection circuit, an exclusive operation can be performed corresponding to the control terminal input voltage [A Tcont in FIG. 4], and the output voltage [Tout in FIG. 4 L] is output to the output terminal 28. obtain.

In other words, while the first gate drive circuit output is ON, the semiconductor switch 11 is ON, the semiconductor switch 12 is OFF, and the second gate drive circuit output is ON.
During this period, the semiconductor switch 11 is turned off and the semiconductor switch 12 is turned on.

Next, the exclusive operation will be explained in detail.
When the pnpn transistor 11a or the pnpn transistor 11b is conductive, the gates of the pnpn transistors 11a and 11b and the transistors connected thereto form a current mirror circuit, so the pnpn transistor 11a is conductive. In this case, the current flows from the collector of the PNP transistor 29 → the diode 30 → the first current mirror input point 52 in the detection circuit or the second current mirror input point 53 in the detection circuit → the diode 32 → the collector of the NPN transistor 33.

Furthermore, even when the pnpn transistor 11b is conductive, the current flows from the collector of the PNP transistor 34 → the diode 35 → the first current mirror input point 52 in the detection circuit or the second current mirror input point 53 in the detection circuit → the diode 36 → The flow flows to the collector of the NPN transistor 37, and the detection circuit 15 outputs the output information [T22 in FIG. 4H] indicating that the semiconductor switch 11 is conducting, and stops the operation of the second delay gate circuit 38CR integration circuit. Therefore, this becomes operation prohibition information for the second gate drive circuit 13b.

Also, pnpn transistor 12b or pnpn
When the transistor 12a is conductive, the gates of the pnpn transistors 12a and 12b and the transistors 43 and 45 form a current mirror circuit, so when the pnpn transistor 12b is conductive, the current flows to the detection circuit. The current flows from the third mirror input point 54 to the diode 42 to the collector of the NPN transistor 43 to the emitter. Also,
When the pnpn transistor 12a is conductive, the current flows from the third mirror input point 54 in the detection circuit to the diode 44 to the collector of the NPN transistor 45 to the emitter, and the detection circuit output T12 causes the current to flow to the first delay gate circuit 21. In order to stop the CR integration circuit in the first gate drive circuit 13a, exclusive operation of the semiconductor switches 11 and 12 becomes possible by providing operation inhibiting input information for the first gate drive circuit 13a.

Now, let us consider a case where the semiconductor switch 11 is to be changed from a conductive state to a non-conductive state, and the semiconductor switch 12 is to be changed from a non-conductive state to a conductive state. The control terminal 20 is supplied with the control signal as described above [see Fig. 4A].
When the input voltage Tcont changes from a low level input voltage to a high level input voltage], each current mirror 29, 33, 24, 37 connected to the gate of the semiconductor switch 11 via the detection circuit 15
The second delay gate circuit 38 together with the OFF information T22 in FIG. H and the control circuit output information T21 in FIG.
Therefore, a delay time [FIG. 4 I] larger than the turn-off time of the semiconductor switch 11 is secured by the CR integration circuit, and a drive current [T24 in FIG. 4 J] is output to the second gate drive circuit 13b, and the drive terminal 39 is
The semiconductor switch 12 is driven through.

Conversely, a case will be considered in which the semiconductor switch 11 is to be changed from a non-conducting state to a conducting state, and the semiconductor switch 12 is to be changed from a conducting state to a non-conducting state. When the control signal as described above is applied to the control terminal 20 [when changing from the high level input voltage of Tcont in FIG. 4A to the low level input voltage], the transistor 43 of the semiconductor switch 12 via the diode 42 or , 45, the OFF information T12 of FIG. 4C,
Along with the control circuit output information T11 in FIG. 4B, the first
By the delay gate circuit 21, the semiconductor switch 12
A delay time [FIG. 4D] larger than the turn-off time of 1 is ensured by the CR integration circuit, and the drive current [T1 in FIGS. 4E and F] is supplied to the first gate drive circuit 13a.
4, T15], and drives the semiconductor switch 11 via the drive terminal 22 and the drive terminal 25.

Furthermore, when the semiconductor switch 12 is brought into a non-conductive state, the output from the drive terminal 46 [Fig.
T25] by driving the base of the NPN transistor 48 through the diode 47.
Clamp between the gate and cathode of the pnpn transistor 12b or through the diode 49.
By driving the base of NPN Darlington transistor 50, pnpn transistor 12a
The anode current is actively cut off by clamping the gate of the pnpn transistor 12a and the cathode of the diode 51 and forcibly drawing current from the P gate of the pnpn transistor 12a.

As described above, according to this embodiment, the turn-off time of the semiconductor switch is determined by means for detecting conduction or non-conduction of the pnpn transistor constituting the semiconductor switch, and by transmitting the detection stage as one of the control information to the control input section. By using the exclusive operation circuit 13 including the delay circuits 21 and 38 that generate a larger delay time, the two semiconductor switches 11 and 12 are not operated simultaneously, so that collision between the calling signal source 5 and the ground air is prevented. There is an advantage that a stable paging signal sending circuit can be obtained.

(Effects of the Invention) As explained in detail above, according to the present invention, a semiconductor switch having a current self-holding function is used and a circuit is provided to control the signals to be sent so that they do not collide with each other. Therefore, it is possible to realize a stable calling signal sending circuit without destroying the switch and also preventing malfunctions due to residual charge in the circuit that would occur when a mechanical switch with transfer contacts is used.

Furthermore, since the switch is entirely made of semiconductors, it has the advantage of being easy to integrate, including peripheral circuits.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a conventional paging signal sending circuit, Fig. 2 is a waveform diagram showing a state of sending a paging signal to a subscriber terminal, and Fig. 3 is a circuit diagram showing an example of a conventional paging signal sending circuit. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIGS. 3 and 5, and FIG. 5 is a detailed circuit diagram of the embodiment shown in FIG. 3. . DESCRIPTION OF SYMBOLS 1...Subscriber terminal, 2...Subscriber line, 3...Current supply circuit, 4...Switch, 5...Paging signal source, 6,
8...Line, 7...Negative power supply, 9...Earth air sending period, 1
0...Call signal sending period, 11, 12...Semiconductor switch, 13...Exclusive operation circuit, 13a, 13b...
Gate drive circuit, 14... Control circuit, 15... Detection circuit, 21, 38... Delay gate circuit, 28... Output terminal, 22, 25, 39, 46... Gate drive circuit output terminal, 23, 24, 26, 27, 30 ,33,
35, 36, 40, 41, 42, 44, 47, 4
9, 51...diode, 29, 33, 34, 3
7, 43, 45, 48, 50...transistor, 5
2, 53, 54... Current mirror input points in the detection circuit.

Claims (1)

[Scope of Claims] 1. In a paging signal sending circuit that sends a paging signal and a ground signal to a subscriber terminal via a subscriber line, a paging signal source and a ground signal are connected to the subscriber line so as to be openable and closable. a pair of first and second current self-holding type bidirectional semiconductor switches, and an exclusive circuit that closes the other while one of the pairs is in an open state, and this circuit is configured to receive a control signal as input. an NPN transistor whose base is connected to the P gate of the semiconductor switch and whose emitter is connected to the cathode of the semiconductor switch via a resistor;
or a current mirror circuit comprising the semiconductor switch and a PNP transistor whose base is connected to the N gate of the semiconductor switch and whose emitter is connected to the anode of the semiconductor switch via a resistor; a detection circuit that detects the open/closed state of the switch; and a control circuit that receives a signal output from the detection circuit and a control signal and outputs two sets of first and second signal groups corresponding to these signals. , a first and a second delay signal group respectively inputting the first or second signal group and outputting the first and second delayed signals having a delay equal to or longer than the turn-off time of the first or second semiconductor switch, respectively. A calling signal sending circuit comprising: a delay gate circuit; and first and second gate drive circuits that respectively input the first or second delay signal to operate the first or second semiconductor switch.