JPH01198281A - Inverter - Google Patents

Abstract

PURPOSE:To prevent erroneous operation and to improve reliability, by arranging a snubber circuit in parallel with a series circuit of a switching element and an impedance. CONSTITUTION:An inverter alternately turns ON and OFF switching elements S1-S2 connected is series with a DC power source E and feeds high frequency power to a load circuit 5. The elements S1-S2 are driven respectively through a control section 1 comprising drive circuits 3, 4. A snubber circuit i.e., a capacitor C4, is connected in parallel with a series circuit of the switching element S2 and an impedance Z. The control circuit 2 comprises a timer IC9 for producing a rectangular signal, a TFF10 and AND gates 11, 12 and produces a control signal having simultaneous OFF interval and turning ON, OFF alternately. A transistor Q2 and a buffer 13 form an overcurrent detector for blocking the AND gates 11, 12 when the voltage V6 across the impedance Z is higher than a predetermined level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to an inverter device that converts DC power into AC power.

[Conventional technology 1 FIG. 9 shows a conventional inverter device of this type.

In this inverter device, switching elements S, S2 connected in series to a DC power source E are turned on and off alternately.
This is a so-called [11 inverter] which supplies frequency power to the load circuit 5. The switching element S,
, S, are turned on and off by the outputs v1 and V2 of the control section 1, respectively. The control unit 1 includes each switching element S
,, a control signal V 31 that turns on and off S 2 alternately.
A control circuit 2 that outputs V 4 and switching elements S, , S according to a control signal V 3 t V 4 of the control circuit 2
2 and drive circuits 3 and 4, respectively. Note that the control signals ■3 and ■ of the control circuit 2 are used to prevent excessive short-circuit current from flowing when the respective switching elements S, S2 are turned on at the same time! - In order to do this, a so-called dead time is provided in which both switching elements S1, S2 are turned off simultaneously. Further, an impedance Z is connected in series to the switching element S2, and the voltage across the impedance Z is detected to detect an overcurrent flowing through the switching element S2. In other words, the impedance Z changes due to variations in the load 6 and the coil L.
When the impedance of the load circuit 5 consisting of the switching element S I and the capacitor C4 changes significantly, the switching element S I
This is provided to prevent excessive current from flowing through -82 and possibly destroying the switching elements S, , S2, and improves reliability by stopping the switching operation of the switching elements S, , S2. That's what I'm trying to do.

Further, the capacitor C4 connected in parallel to the switching element S2 is a snubber circuit that prevents the Sarno voltage from being applied to the switching element S2 due to the load circuit 5 including the resonant circuit consisting of the coil LI and the capacitor C1.

By the way, such switching elements S , , S 2
In an inverter device in which the control circuit 5 and the switching element S1 are connected in series, it is necessary to level shift the drive signal V in order to drive the switching element S1 on the side where the potential is different from that of the control circuit 5. Therefore, P
A level switch 7 consisting of an NP current mirror circuit 7 and an NPN current mirror circuit 8 constituted by two NPN transistors is provided.

Note that a diode D connected in parallel to the PNP current mirror circuit 7 protects the PNP current mirror circuit 7 from a reverse voltage, and a resistor R1 is an output resistance of the PNP current mirror circuit 7. The power source of the control unit 1 corresponding to each of the switching elements S, S2 is a resistor R.
2, obtained from capacitor C2, resistor R1, and capacitor C3.

Now, if the control signal V3 becomes high level at time t0, the drive output v2 also becomes high level, the switching element S2 is turned on, and current 2 flows through the load circuit 5.

At this time, the direction shown by the arrow in the figure (in the following explanation, the direction of the current shown by the arrow in the figure is called the positive direction,
The opposite direction will be called the negative direction. ) current ■2 flows through. Time t.

When the control signal (3) becomes low level, the switching element S2 is turned off, but the current flowing through the coil tries to continue flowing and flows in the opposite direction to the switching element S. When the control signal ■ becomes high level at time t2, N
A current I5 flows through the PN current mirror circuit 8, and P
The output (2) of the NP current mirror circuit 7 becomes a high level, the drive output (2) of the drive circuit 3 becomes a high level, and the switching element S1 is turned on. And time t
, when the control signal ■4 of the control circuit 2 becomes low level,
The drive output ■ also becomes low level, and the switching element S
1 is turned off, and the switching element S2 is turned on again at time t. High frequency power is supplied to the load 6 by repeating the above operations.

By the way, capacitor C1 has t11t during switching.
3, in order to absorb the Sarno voltage due to the load circuit 5, the potential V? at the connection point of the switching elements S, , S, is increased. (
At the time of the change shown in FIG. 10(k)), an inrush current I3 shown in FIG. 10(i) flows. What is the sum of this rush current I3 and current I2? , (Fig. 10 (j)) flows through the impedance Z for overcurrent detection, and the voltage across the impedance Z becomes
is as shown in FIG. 10 (Q,). However, time t
As shown in , the impedance Z changes due to the fluctuation of the load 6.
When the voltage across the terminal ■6 becomes equal to or higher than the overcurrent detection voltage vth of the control circuit 2 (■×), the control circuit 2 output V 2 t V
4 become low level, and the oscillation operation of the inverter device stops.

In other words, the end of the book is that the switching element S
There was a problem in that the overcurrent detection impedance Z, which was supposed to protect the +-82, caused malfunctions.

Furthermore, the dynamic range of overcurrent detection is also reduced due to the inrush current I flowing through the capacitor C4.

Note that the above description is for the case where the operating frequency of the switching elements S 1 , S 2 is higher than the natural oscillation frequency of the load circuit 5 .

The switching element S is lower than the natural vibration frequency of the load circuit 5.
, , FIG. 11 shows the operation when the operating frequency of S2 is low. At time 〇, the drive output ■2 becomes high level and the switching element S2 is turned on, and the coil L of the load circuit 5
, , the current flowing in the opposite direction of the switching element Sl flows in the positive direction of the switching element S2, and the potential ■
7 becomes zero. When a reverse current flows through the switching element S1, if a forward voltage is forcibly applied to eliminate the reverse current, a recovery current generally flows, so the current I flowing through the switching element S has a steep current component. Therefore, the steep current also flows through the switching element S2. Further, in this case, the discharge current of the capacitor C2 flows only to the switching element S2, and does not flow to the impedance Z. Therefore, the voltage (6) across the impedance Z is not affected either. Time t.

Then, the drive output (2) becomes a low level, and the switching element S2 is turned off in the positive direction. However, current I2 is in the negative direction and is not affected. Time t
At 2, the drive output V becomes a high level, the potential V7 also becomes a high level, and the coverage current of the switching element S2 and the charging current of the capacitor C4 flow to the switching element S. At time t3, drive output ■1 becomes low level, and at time t, drive output v2 becomes high level again. If the operating frequency of the switching elements S, , S2 is lower than the characteristic signal frequency of the load circuit 5, a steep component is included due to the recovery current during switching, so that the impedance Z will change regardless of the presence or absence of the capacitor C6. The dynamic range for overcurrent detection becomes small, the overcurrent detection effect is low, and the influence of capacitor C4 is reduced at rK+ to *L. In addition, the switching element S,
, S2, this mode is inappropriate and is not normally used.

Therefore, when the operating frequency of the switching elements S , , S 2 is higher than the natural oscillation frequency of the load circuit 5,
Malfunction caused by capacitor C1 becomes a problem, and in this case, reliability decreases.

[Problem to be Solved by the Invention 1] The present invention has been made in view of the above points, and its purpose is to solve the problem even when the operating frequency of the switching element is higher than the natural oscillation frequency of the load circuit. Another object of the present invention is to provide an inverter device that does not cause malfunctions due to charging and discharging of a snubber circuit.

Means for Solving the Problems 1 In order to achieve the above object, the present invention connects a snubber circuit that absorbs surges caused by a load circuit in parallel to a series circuit of one switching element and an impedance.

(Function) As described above, the present invention prevents the charging/discharging current of the snubber circuit from flowing through the impedance by connecting a snubber circuit that absorbs surges caused by the load circuit in parallel to the series circuit of one switching element and the impedance. In this way, the voltage caused by charging and discharging the snubber circuit is prevented from appearing in the voltage across the impedance.

(Example) An embodiment of the present invention is shown in FIGS. 1 and 2.

The configuration of this embodiment is substantially the same as that of the conventional example described above, except that in this embodiment, a capacitor C4 serving as a snubber circuit is connected in parallel with a series circuit of switching element S2 and impedance Z. Switching element S,,S
2 is a transistor Q and a diode D2 connected in parallel as shown in FIG. 7(a), or an N-channel MO3.
) that can be energized at any time in the vertical direction are used. Further, as the control circuit 2, one as shown in FIG. 8 is used. In other words, this control circuit 2 includes a timer IC 9 that generates a rectangular signal and a T 7 lip 7F that alternately generates inverted outputs on both outputs by the output of the timer IC 9.
11
．． 12 to obtain a control signal that has a simultaneous off period and is turned on and off alternately. The transistor Q2 and the buffer 13 constitute an overcurrent detection circuit that shuts off AND (11.12) when the voltage across the impedance Z is equal to or higher than a predetermined voltage. That is, when the voltage across the impedance Z exceeds a predetermined voltage, the transistor Q is turned on, the buffer 13 is latched at a low level, and the AND/D11.12 output is set at a low level.

Now, at time t0, the drive output ■2 becomes high level, the switching element S2 is turned on, and the resonant current of the load circuit 5 flows, and when the switching element S2 is turned off at time t, the current I2 tries to continue flowing, and the switching element S2 is turned on. Flows in the opposite direction to element S1. At this time, the voltage of the capacitor C1 reaches a high level together with the potential 7 at the connection point of the switching element S + =82, but the charging current I3 of the capacitor C4 does not flow to the impedance Z. Drive output at time t2■
becomes high level, the switching element S1 is turned on in the positive direction, and turned off at the time. At this time, the load current flows through the switching element S2 in the opposite direction, and the discharge current of the capacitor C1 does not flow through the impedance Z.

At time t, the drive output V2 becomes high level again, and the above-described operation is repeated. In other words, since the current ■ of the snubber circuit that reduces the surge voltage during switching does not flow to the impedance Z for overcurrent detection, the detection voltage V is affected by this current I3 as shown in #S2 diagram (0,). No output is generated, and a wide dynamic range up to the overcurrent detection voltage Vth can be achieved. Therefore, it is possible to accurately detect only when an overcurrent flows due to a change in the resonant frequency due to a change in the load circuit 5. By the way, as the snubber circuit, a capacitor C shown in FIG. 3(a) is used.
CR series type in which 1 and resistor R1 are connected in series, or capacitor C41 resistor R4, coil L2 shown in the same figure (b)
An LCR series type in which two are connected in series may also be used. The overcurrent detection impedance Z includes a resistor R7 shown in FIG. 4(a), a parallel circuit of resistor R5 and a capacitor C1 shown in FIG. 4(b), and a resistor R3 and a coil shown in FIG. A parallel circuit with L is used. Moreover, the connection position of the snubber circuit may be parallel to the switching element S1, and in this case as well, the voltage of the overcurrent detection impedance Z is not affected.

[Effects of the Invention] As described above, in the present invention, two switching elements that have simultaneous off periods and are turned on and off alternately are connected in series to a DC power supply, and have a natural vibration frequency lower than the operating frequency of the switching elements. In an inverter device in which a load circuit that resonates at is connected to both ends of one switching element, an impedance is inserted in series with the one switching element, and a voltage across the impedance is detected to control the operation of the switching element. Since a snubber circuit that absorbs surges caused by the load circuit is connected in parallel to the series circuit of one switching element and the impedance, it is possible to prevent the charging/discharging current of the snubber circuit from flowing to the impedance. There is an advantage that the voltage due to the discharge current does not appear in the voltage across the impedance, and therefore there is no possibility of malfunction in the operation of controlling the switching element based on the voltage across the impedance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the same operation as above, FIGS. 3(a) and (b) are specific circuit diagrams of the same snubber circuit as above, and FIG. ) to (e) are specific circuit diagrams of the same impedance as above, FIG. 5 is a partial circuit diagram when the snubber circuit is connected to the other switching element, and FIG.
The figure is a specific circuit diagram of the same drive circuit as above, and FIGS. 7(a) and (b).
) are specific circuit diagrams of the same switching elements as above, FIG. 8 is a specific circuit diagram of the control circuit as above, FIG. 9 is a circuit diagram of a conventional example, and FIGS. 10 and 11 are operation explanatory diagrams as above, respectively. be. 5 is a load circuit, S + , S 2 is a switching element,
E is a DC power supply, C1 is a capacitor, and Z is an impedance. Agent Patent Attorney Ishi 1) Ai Figure 7 Figure 3 (0) (b) Figure 5 Figure 62 Figure 7 Figure 8

Claims (1)

[Claims] (1) Two switching elements that have simultaneous off periods and turn on and off alternately are connected in series to a DC power supply, and one switching element connects a load circuit that resonates at a natural frequency lower than the operating frequency of the switching element. In an inverter device, an impedance is inserted in series with one of the switching elements, and the voltage across the impedance is detected to control the operation of the switching element. An inverter device comprising: a snubber circuit connected in parallel to the snubber circuit for absorbing surges caused by a load circuit.