JPS6342301B2 - - Google Patents

Info

Publication number
JPS6342301B2
JPS6342301B2 JP58118779A JP11877983A JPS6342301B2 JP S6342301 B2 JPS6342301 B2 JP S6342301B2 JP 58118779 A JP58118779 A JP 58118779A JP 11877983 A JP11877983 A JP 11877983A JP S6342301 B2 JPS6342301 B2 JP S6342301B2
Authority
JP
Japan
Prior art keywords
replacement
block
bits
blocks
log
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58118779A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6010370A (ja
Inventor
Nobuhiko Kuribayashi
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58118779A priority Critical patent/JPS6010370A/ja
Publication of JPS6010370A publication Critical patent/JPS6010370A/ja
Publication of JPS6342301B2 publication Critical patent/JPS6342301B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58118779A 1983-06-30 1983-06-30 バツフア記憶装置における置き換え制御方式 Granted JPS6010370A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58118779A JPS6010370A (ja) 1983-06-30 1983-06-30 バツフア記憶装置における置き換え制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58118779A JPS6010370A (ja) 1983-06-30 1983-06-30 バツフア記憶装置における置き換え制御方式

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP61313524A Division JPS62162153A (ja) 1986-12-27 1986-12-27 バツフア記憶装置における置き換え制御方式

Publications (2)

Publication Number Publication Date
JPS6010370A JPS6010370A (ja) 1985-01-19
JPS6342301B2 true JPS6342301B2 (enrdf_load_stackoverflow) 1988-08-23

Family

ID=14744866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58118779A Granted JPS6010370A (ja) 1983-06-30 1983-06-30 バツフア記憶装置における置き換え制御方式

Country Status (1)

Country Link
JP (1) JPS6010370A (enrdf_load_stackoverflow)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693167A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Memory replacement control system
JPS5696337A (en) * 1979-12-28 1981-08-04 Fujitsu Ltd Resource control system

Also Published As

Publication number Publication date
JPS6010370A (ja) 1985-01-19

Similar Documents

Publication Publication Date Title
US5274790A (en) Cache memory apparatus having a plurality of accessibility ports
US4905141A (en) Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
EP0084114B1 (en) Instruction prefetching data processing apparatus including a conditional branch instruction predictor
EP0036110B1 (en) Cache addressing mechanism
US6496902B1 (en) Vector and scalar data cache for a vector multiprocessor
US4831520A (en) Bus interface circuit for digital data processor
US5091851A (en) Fast multiple-word accesses from a multi-way set-associative cache memory
US6006311A (en) Dynamic updating of repair mask used for cache defect avoidance
CN101470670B (zh) 具有扇区功能的高速缓冲存储器
EP0303661B1 (en) Central processor unit for digital data processing system including write buffer management mechanism
US6023746A (en) Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction
JPH1074166A (ja) 多重レベル・ダイナミック・セット予測方法および装置
CN101918925B (zh) 用于处理器的高关联性高速缓存的第二次机会取代机制
US6745291B1 (en) High speed LRU line replacement system for cache memories
US6085288A (en) Dual cache directories with respective queue independently executing its content and allowing staggered write operations
JPH07311711A (ja) データ処理装置とその動作方法及びメモリ・キャッシュ動作方法
US5636354A (en) Data processor with serially accessed set associative memory cache interface and method
Liptay Design of the IBM Enterprise System/9000 high-end processor
EP0284751B1 (en) Cache memory
US4658356A (en) Control system for updating a change bit
US5295253A (en) Cache memory utilizing a two-phase synchronization signal for controlling saturation conditions of the cache
JPS6342301B2 (enrdf_load_stackoverflow)
JPH0551933B2 (enrdf_load_stackoverflow)
JPS6194159A (ja) メモリ装置
JP2845762B2 (ja) 階層バッファメモリ装置