JPS6342301B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a control method for a buffer storage device of a computer, and in particular to a control method for LRU of a block in a buffer storage device such as a set associative method.
(Least Recently Used) Management Replacement Control Method. [Technical background] Many of the latest large-scale computers have set-associative caches installed in the CPU in order to shorten the main memory access time from the CPU. In a system in which VUs (vector units) are connected, the VUs directly access the main memory, so consistent control is required between the CPU's cache and the main memory. Figure 1 shows an example of this. 1 is the main storage unit MSU, 2 is the main storage control unit MCU, 3 is the central processing unit CPU, 4 is the vector processing unit VU, and 5 is the main storage unit MCU.
The cache is composed of TAG1 and a data buffer, 6 is TAG2, and 7 is a TAG2 control circuit. When the CPU performs a BLOCK FETCH from main memory, the address and data are registered in TAG1 and data buffer of the cache, and at the same time,
Register BLOCK FETCH address to TAG2.
When VU stores to main memory, the store address is
The address is sent to TAG2 and checked to see if it matches the address of the CPU's cache. If there is a match, the CPU sends the matching address to TAG1 of the cache and performs buffer invalidation (BI). If they do not match, buffer invalidation is not performed. TAG2 is
It consists of two BLOCKs, BLK0 and BLK1, and performs data replacement control so that it is always occupied by the most recently used block. The replacement algorithm is LRU. BLK0 of TAG2,
If you have already registered on both BLK1, you will receive additional
To register a BLOCK FETCH address,
It determines the address that is not the latest based on the contents of the replacement bit, transfers that address to the CPU, performs buffer invalidation on the cache, and registers the BLOCK FETCH address for the replaced BLOCK of TAG2. [Object and Structure of the Invention] An object of the present invention is to
The purpose is to realize a control circuit for LRU management easily and with a small amount of hardware, and the configuration for this purpose includes a buffer consisting of N blocks, where N is a power of 2 greater than 4;
In a set associative buffer storage device equipped with a replacement control circuit that controls data replacement of each block based on the replace bits, the replacement control circuit has log ₂ N replace bits for each block. ,
Furthermore, it is provided with a usage order determination logic circuit that assembles a log ₂ N stage tournament style logic in which two of each block are combined using one of each of the log ₂ N replacement bits of each of the blocks. This method is characterized in that a replacement block is determined by the following. [Examples of the Invention] The details of the present invention will be described below with reference to Examples. When the buffer is divided into N blocks and used, each block needs to have [log ₂ N] replacement bits. First, the cases where the number of blocks is 2 and 4 will be explained, and finally the case where the number of blocks is generalized to N will be explained. In addition, among the new blocks, the one with the most recent usage history
The older one is expressed as HOT and the older one as COLD. (1) When the number of blocks is 2 As shown in Figure 2, each block BLK0,
Add one replacement bit each to BLK1 R ₀ and R ₁
will be established. The replacement algorithm is as follows. If the values of R ₀ and R ₁ are 0, 0 or 1, 1, BLK1 is HOT and replaces BLK0. If the values of R ₀ and R ₁ are 0, 1 or 1, 0, BLK0 is HOT and replaces BLK1. When replacing, new data is registered in that block, but at that time, the previous replacement bit is inverted and registered. As a result, the replaced block becomes HOT. FIG. 3 shows an example of a circuit for determining a replacement block. In the figure, 8 is an exclusive OR EOR gate, 9 is an inverter, and 10 is a buffer. When a block is referenced, set the replace bit so that the referenced block becomes HOT. However, there are cases where it is not necessary to invert, such as when it is referenced continuously. Here, set the new replacement bit.
Assuming NewR0 and NewR1, the logic is as follows. NewR0 = (Replacement of BLK0) R0 NewR1 = (Replacement of BLK1) R1 Further arrangement can be expressed as NewR0 = (01) R0 = 1 NewR1 = (R0R1) R1 = R0. Note that the symbol in the formula indicates exclusive OR EOR. This is realized by a simple circuit of an inverter 11 and an AND gate 12 shown in FIG. FIG. 5 shows an example of the operation of replacement control executed using the circuits of FIGS. 3 and 4. In the order of operation order numbers P ₁ , P ₂ , ..., P ₁₀ ,
It shows the values of R0 and R1, HOT block, and replacement block when the registration or reference operation shown in the operation content line is performed. In addition, in the INITIAL state of P ₀ , BLK0 and
BLK1 is cleared. Therefore, no substitution occurs in the registration of P ₁ and P ₃ , and the next P ₆ ,
Replacement occurs when P ₇ and P ₉ are registered. (2) When the number of blocks is 4 As shown in Figure 6, each block BLK0 to
BLK3 has two replacement bits (R00,
R10), (R01, R11), (R02, R12), (R03,
R13). Role of each replacement bit and HOT and COLD
The judgment conditions are as follows. HOT or COLD determination between BLK0 and BLK1 is made using the R00 and R01 bits. The judgment conditions are the same as in the previous section (1). That is, in the case of (0, 0) or (1, 1),
BLK0 is determined to be COLD. In the case of (1, 0) or (0, 1), BLK1 is determined to be COLD. The determination of HOT and COLD between BLK2 and BLK3 is performed in the same way. HOT between BLK0, 1 and BLK2, 3,
For determination of COLD, R10, R11, R12,
If all EORs of R13 bits are 0,
BLK0 and 1 are determined to be COLD. Based on the above three judgment results, the oldest block is replaced. When registering new data to the replaced block, use the replace bit (R0X, R1X)
The contents of the previous replacement bit are reversed and registered. As a result, the replaced block becomes
It will always be a HOT block. Even if a block is referenced, set it to be HOT even if it has a block. NewR00,
NewR01, NewR02, and NewR03 are updated as follows in the same way as when the number of blocks is two. NewR00=01 NewR01=R00 NewR02=03 NewR03=R02 Similarly for NewR10, NewR11, NewR12, and NewR13, NewR10=R10 (replacement of BLK0, 1) NewR11=R11 (replacement of BLK0, 1) NewR12=R12 (replacement of BLK2, 3 replacement) NewR13=R13 (BLK2, 3 replacement). Logically, it can be made even simpler, but
In the actual design, (replacement of BLK0 and 1),
(Replacement of BLK2 and 3) is created when creating the replacement block, so it will not be simplified any further. FIG. 7 shows an example of a determination circuit for determining the above-mentioned replacement block. In the figure, 13
17 to 17 are EOR gates, 18 to 20 are inverters, and 21 to 24 are AND gates. FIG. 8 shows an example of the above-mentioned new replacement bit creation circuit. In the figure, 25 to 28
is an EOR gate. FIG. 9 is an operation example of replacement control executed using the circuits of FIGS. 7 and 8, and corresponds to FIG. 5. Operation sequence number P ₀
In the INITIAL state, all blocks are cleared. Therefore, no replacement occurs in the registration operations from P ₁ to P ₄ . (3) When the number of bits is N: N is a positive integer and a power of 2, such as 1, 2, 4, 8, 16, 32, etc. At this time, the number of replacement bits is [log ₂ N]. As a result, the total number of reference bits is [N×
log ₂ N]. FIG. 10 is an explanatory diagram of a replacement bit judgment processing algorithm used to determine a replacement block for such N blocks, and the ranking is judged in [log ₂ N] stages with 2 as a unit. It has a tournament structure (or tree structure). For example, BLK0 has a replacement bit.
R00, R10,...R ((logN)-1, 0) are given, and the last BLK (N-1) is given R0 (N-1),
R1(N-1),...R((logN)-1·N-1) are given. 1st reference bit of each block
R00, R01, . . . , R0·N-1 are used to determine HOT and COLD between each two blocks when all blocks are divided into groups of two. These groups are (R00,
R01), (R02, R03), ..., (R0・N−2, R0・
N-1). Second reference bit for each block
R10, R11,..., R1・N-1 are HOT between two groups of two blocks in sequence,
Used to determine COLD. In this way, the last reference bits R((logN)-1.0), R
((logN)-1・1), ..., R((logN)-1・N
-1) is used to determine HOT and COLD between groups of N/2 blocks. Based on the judgment results at each judgment stage above,
The AND logic of each determination is taken, and the block that is the coldest is determined to be the replacement block. For example, if block X is replaced, its replacement bits R0X, R1X,..., R((logN)-
1.Reverse all of X) and register. This makes the block a HOT block. Also, when referenced, the referenced block will always be HOT.
R0X, R1X, ..., R according to the following conditions
Set ((logN)-1,X). NewROX=0・+1 (X=0, 2, 4, 6, 8,...) NewR0・X+1=R0X NewR1X=R1X (replacement of BLKX, X+1) NewR1・X+1=R1・X+1 (replacement of BLKX, X+1) NewR2X=R2X (BLKX, X+1, X+2, X+3
) NewR2・X+1=R2・X+1 (BLKX, X+1,
Replacement of X+2, X+3) NewR2・X+2=R2・X+2 (BLKX, X+1,
Replacement of X+2, X+3) NewR2・X+3=R2・X+3 (BLKX, X+1,
(Replacement of X+2, X+3) The same applies hereafter. Next, a device according to an embodiment of the present invention will be described. FIG. 11 shows the configuration of an embodiment in which the method of the present invention is applied to a circuit centered on TAG2 in the storage control device in the computer system shown in FIG. In FIG. 11, 6 is TAG2, in which an address copy of a cache consisting of two blocks BLK0 and BLK1 is stored. 7 is TAG2 control circuit, 29 is TAG2IN register, 30 is BFA register, 31 is selector SEL, 32 is
TAG2OUT register, 33 and 34 are matching circuits, and 35 is a ULPR control circuit. The TAG2(6) block consists of 512 lines.
Block size is 128 bytes. On the other hand,
The CPU cache block size is 64 bytes. TAG2 also includes auxiliary control bits such as U, L, P, and R. U and L bits are TAG2
These bits indicate the upper (U) 64 bytes and lower (L) 64 bytes of the block size of 128 bytes. Further, P is a parity bit, and R is a replacement bit. Note that the parity bit P is the parity bit for the U, L, and R bits. TAG2IN register 29 and BFA register 3
The input address data is added to 0 at the same time, but the TAG2IN register holds this for 1T (T is a clock cycle), and the BFA register 30 holds it for a certain period of time. Thereby, VU
At a timing when a STORE address is not input, the selector 31 is opened and address data can be written to TAG2 through the TAG IN register 29. Next, we will discuss the operation when registering TAG2. In this case, the registration data input to the TAG2IN register 29 is the block fetch address of the CPU. Also, the VALID of block BLK0 of TAG2(6)
The V bit indicating (validity) is V ₀ , similarly
The V bit that displays the VALID of BLK1 is _V1 ,
Each is input to the TAG2 control circuit 7 (not shown) and V=V ₀ ·V ₁ is calculated. Further, the matching circuit 33 sets the match signal as a result of comparing the contents of BLK0 of TAG2 and the input registration data as _M0 , and the match signal of BLK1 from the matching circuit 34 as _M1 , and inputs them to the TAG2 control circuit 7. , calculate M=M ₀ +M ₁ . The TAG2 control circuit 7 further performs the following control operation according to the above values of V and M.

〔Effect of the invention〕

According to the present invention, the number of replacement bits required for N blocks is [N×log ₂ N]
It is individual. However, in the conventional method, as the number of blocks increases, the rate of increase in the number of replaced bits increases compared to the method of the present invention.For example, when the number of blocks is 16, a conventional method requires 120 bits, but the method of the present invention requires 64 bits. You can get away with bits. In addition, fewer peripheral circuits are required and control is simplified.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a buffer storage device, Figure 2 is an explanatory diagram of reference bits, Figure 3 is an example diagram of a replacement block determination circuit when the number of blocks is 2, and Figure 4 is a replacement bit creation circuit. FIG. 5 is an explanatory diagram of its operation example, FIG. 6 is an explanatory diagram of the replacement bit when the number of blocks is four, FIG. 7 is an embodiment diagram of the replacement block determination circuit, and FIG. The figure also shows an example of the replace bit creation circuit, and FIG. 9 is an explanatory diagram of an example of its operation.
FIG. 10 is an explanatory diagram of the replacement bit when the number of blocks is N, FIG. 11 is a diagram of the main part of one embodiment of the storage control device, and FIG. 12 is an explanatory diagram of the parity bit. In the figure, 1 is the main storage unit MSU, 2 is the storage control unit MCU, 3 is the central processing unit CPU, 4 is the vector processing unit VU, 5 is the cache memory, and 6 is the
TAG2 and 7 indicate TAG2 control circuits.

Claims (1)

[Scope of Claims] A set associate comprising a buffer consisting of N blocks, where N is a power of 2 greater than 4, and a replacement control circuit that controls data replacement of each block based on a replace bit. In the buffer storage device using the buffer storage system, the above-mentioned replacement control circuit performs log ₂ N for each block.
Each block has two replacement bits, and one of each of the log ₂ N replacement bits of each of the above blocks is used to combine two of each block.
A replacement control method is characterized in that a replacement block is determined by providing a usage ranking determination logic circuit that has a log ₂ N-stage tournament style logic. 2. A set associative type buffer storage device comprising a buffer consisting of N blocks, where N is a power of 2 greater than 4, and a replacement control circuit that controls data replacement of each block based on replace bits. In this case, the above replacement control circuit calculates log ₂ N for each block.
Each block has two replacement bits, and one of each of the log ₂ N replacement bits of each of the above blocks is used to combine two of each block.
It is configured to determine the replacement block by providing a usage order determination logic circuit that has a log ₂ N-stage tournament style logic, and furthermore, the replacement bit for each block is as follows:
A replacement control method characterized in that parity is checked together with other control bits of the block.