JPS6341220B2 - - Google Patents
Info
- Publication number
- JPS6341220B2 JPS6341220B2 JP56041345A JP4134581A JPS6341220B2 JP S6341220 B2 JPS6341220 B2 JP S6341220B2 JP 56041345 A JP56041345 A JP 56041345A JP 4134581 A JP4134581 A JP 4134581A JP S6341220 B2 JPS6341220 B2 JP S6341220B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- inspection
- bonding wire
- wiring
- illuminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 238000007689 inspection Methods 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 6
- 238000003384 imaging method Methods 0.000 claims description 8
- 238000005286 illumination Methods 0.000 claims description 7
- 230000007547 defect Effects 0.000 claims description 2
- 239000000284 extract Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- 238000011179 visual inspection Methods 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置のボンデングワイヤ配線形
状を検べる検査装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection device that can inspect the shape of bonding wires in semiconductor devices.
通常、半導体装置は半導体チツプをパツケージ
にダイス付けし、チツプ表面の配線パツドとパツ
ケージ上のリード端子との間を、アルミニウム又
は金の細線（直径25〜30μｍ程度）で接続してお
り配線パツドとリード端子との双方にボンデング
されるので、ワイヤはボンデングワイヤと呼ばれ
ている。第１図にその部分断面図を示しており、
１は半導体チツプ、２はその配線パツド、３はパ
ツケージ、４はリード端子、５はボンデングワイ
ヤであるが、集積回路（IC）では多数のワイヤ
が配線されるため、配線が少しずれると隣接する
ワイヤと接触しやすくなり、又タルミが多いと半
導体装置を使用しているうちに、徐々に変形して
ワイヤ相互間で接触したりあるいはチツプ表面上
の半導体素子と接触する事故を発生する。 Normally, semiconductor devices are made by dicing a semiconductor chip onto a package, and connecting the wiring pads on the surface of the chip and the lead terminals on the package with thin aluminum or gold wires (about 25 to 30 μm in diameter). The wire is called a bonding wire because it is bonded to both the lead terminal and the lead terminal. Fig. 1 shows a partial sectional view of it.
1 is a semiconductor chip, 2 is its wiring pad, 3 is a package, 4 is a lead terminal, and 5 is a bonding wire.In an integrated circuit (IC), a large number of wires are wired, so if the wires are slightly misaligned, adjacent wires may If the semiconductor device has a large amount of sag, it will gradually deform as the semiconductor device is used, causing accidents such as contact between wires or contact with semiconductor elements on the surface of the chip.
従つて、従来よりワイヤをボンデングした組立
工程後に、目視によつてすべてのボンデングワイ
ヤを検査しているが、検査工数が多くかゝつて、
且つ入手による目視検査では、誤差も多くて見落
しもあり漏れのない検査は困難である。 Therefore, conventionally, all bonded wires are visually inspected after the assembly process in which the wires are bonded, but this requires a large number of inspection steps.
In addition, visual inspection upon acquisition has many errors and oversights, making it difficult to perform a complete inspection.
本発明はこのような欠点を除去することを目的
としており、その特徴は半導体チツプ表面の配線
パツドと該チツプを内在する半導体パツケージ上
のリード端子との間が、ボンデイングワイヤによ
る多数のワイヤで互に隣接するように配線接続さ
れている半導体ボンデイングワイヤの検査装置に
おいて、前記半導体パツケージの全周囲側方向か
ら該ワイヤ全体を照明する照明装置を具備し、更
に該半導体パツケージの上方に位置して、前記照
明装置により照明された全ボンデイングワイヤの
ワイヤ全体の配線形状を映像信号で把える撮像装
置と、撮像装置からの映像信号を２値化させる２
値化変換回路と、２値化信号を記憶させるメモリ
装置と、メモリ装置より所要領域の２値化信号を
抽出して、ボンデイングワイヤ配線の欠陥形状を
検出する検出回路とを設けた半導体ボンデイング
ワイヤの検査装置であり、以下詳細に説明する。 The present invention aims to eliminate such drawbacks, and its feature is that the wiring pads on the surface of the semiconductor chip and the lead terminals on the semiconductor package containing the chip are interconnected by a large number of bonding wires. The inspection apparatus for semiconductor bonding wires connected adjacent to the semiconductor package includes an illumination device that illuminates the entire wire from the entire periphery of the semiconductor package, and further includes an illumination device located above the semiconductor package, an imaging device that captures the overall wiring shape of all the bonding wires illuminated by the lighting device using video signals; and 2. Binarizing the video signal from the imaging device.
A semiconductor bonding wire that is provided with a digitization conversion circuit, a memory device that stores the binary signal, and a detection circuit that extracts the binary signal in a required area from the memory device and detects the shape of a defect in the bonding wire wiring. This is an inspection device, and will be explained in detail below.
本発明ではボンデングワイヤの配線形状を検査
するため、ワイヤの照明装置が特に大切で、一般
的な照明系のように垂直に上方から照射すれば、
半導体チツプ表面の配線パターンと混同するなど
の誤りが生じ易い。そのため、半導体容器の周囲
側方向から照明する方法を採り、その実施例を第
２図ａ，ｂに示す。同図ａはサークル螢光灯６。
ｂは４ケの線状フイラメント電球７で、出来るだ
け小型のものを用いる。又、周囲に多数の豆電球
を配列してもよくて、その照度は1000ルツクス程
度とする。通常のボンデングワイヤは30μｍφ前
後であつて、上記のように全周囲方向から照射す
ると、ワイヤに光が当たり、それが全方向に反射
して、上方に円弧を画いているボンデングワイヤ
の配線形状のみクローズアツプする状態となる。
第１図から判るように半導体チツプ１の周囲は凹
んでいるので暗く、又チツプ表面も側方からの光
照射では反射光が撮像系にほとんど入らないため
不鮮明となるから、上記照明ワイヤを最も認識し
やすい。 In the present invention, the wiring shape of the bonding wire is inspected, so the lighting device for the wire is particularly important.
Errors such as confusion with the wiring pattern on the surface of the semiconductor chip are likely to occur. Therefore, a method of illuminating the semiconductor container from the periphery side is adopted, and an example thereof is shown in FIGS. 2a and 2b. Figure a shows circle fluorescent lamp 6.
b indicates four linear filament light bulbs 7, which are as small as possible. Also, a large number of miniature light bulbs may be arranged around the area, and the illumination intensity should be about 1000 lux. Normal bonding wire has a diameter of around 30 μm, and when irradiated from all directions as shown above, the light hits the wire and is reflected in all directions, creating an upward arc. Bonding wire wiring Only the shape will be close-up.
As can be seen from FIG. 1, the area around the semiconductor chip 1 is dark because it is recessed, and when the chip surface is illuminated from the side, the reflected light hardly enters the imaging system, making it unclear. Easy to recognize.
このような照明装置を用いて、照し出されたボ
ンデングワイヤの配線形状を顕微鏡で拡大し撮像
装置で把えるが、ボンデングワイヤからの反射光
を映像装置として認識することが可能な例えば
CCDカメラやビジコンを撮像装置として使用す
る。これらの認識および検出系は第３図のブロツ
ク図に示しており、１０は顕微鏡、１１はCCD
カメラ、１２は２値化変換回路、１３はメモリ装
置、１４は検出回路で、CCDカメラで把握され
た映像信号は２値化変換回路で適切なしきい値に
よつて信号（０、１）に変換され、その２値化信
号はシフトレジスタなどからなるメモリ装置にマ
トリツクス状に順次蓄えれる。次いでメモリ装置
１３内の２値化信号を検出回路１４で検出する
が、その際に第４図に示す検出領域１５に限定す
る方式を用いると好都合である。検出領域１５は
半導体チツプ１の周囲外線からパツケージ３のリ
ード端子４がある内線までの方形環状領域とす
る。即ち検出回路では走査して識別するとき、例
えば上記方形環状領域以外はすべて信号０におき
かえ識別する。それにはメモリ装置１３にたくわ
えられた２値化信号のマトリツクスと組立工程で
記憶させたチツプ及びパツケージの位置を組み合
わせて、演算すればよい。そして、例えばＸ方
向、Ｙ方向に走査して、配線信号を１とし、信号
１の相互間隔が規定値以下となれば不良とする。
検出走査にはその他の簡便な方式もあるが、この
様に検出領域を限定すれば誤認しやすい位置を除
去することになるので、誤りは皆無となり、且つ
ボンデンワイヤ配線形状はすべて検出される。
又、本発明のような上面から得た撮像信号では、
たとえワイヤ相互に上下間の間隙が充分であつて
も、接触として判定するのが、上下間のみの間隙
は使用中にダレを起して事故発生の恐れがあるの
で、不良とする考え方である。 Using such an illumination device, the wiring shape of the illuminated bonding wire is magnified with a microscope and grasped with an imaging device.
A CCD camera or vidicon is used as an imaging device. These recognition and detection systems are shown in the block diagram in Figure 3, where 10 is a microscope and 11 is a CCD.
A camera, 12 is a binarization conversion circuit, 13 is a memory device, and 14 is a detection circuit.The video signal captured by the CCD camera is converted into a signal (0, 1) by the binarization conversion circuit using an appropriate threshold. The converted signals are sequentially stored in a matrix in a memory device such as a shift register. Next, the binary signal in the memory device 13 is detected by the detection circuit 14, but it is convenient to use a method of limiting the detection area 15 shown in FIG. 4 at this time. The detection area 15 is a rectangular annular area from the outer line of the semiconductor chip 1 to the inner line where the lead terminals 4 of the package 3 are located. That is, when the detection circuit scans and identifies, for example, all areas other than the above-mentioned rectangular annular area are replaced with a signal of 0 for identification. This can be done by combining the binary signal matrix stored in the memory device 13 with the chip and package positions stored in the assembly process. Then, by scanning in, for example, the X direction and the Y direction, the wiring signal is set to 1, and if the mutual interval between the signals 1 becomes less than a specified value, it is determined to be defective.
There are other simple methods for detection scanning, but by limiting the detection area in this way, positions that are likely to be misidentified are removed, so there are no errors, and all bonded wire wiring shapes are detected.
In addition, in the imaging signal obtained from the top surface as in the present invention,
Even if the gap between the top and bottom wires is sufficient, it is judged as contact, but if there is only a gap between the top and bottom, there is a risk of sagging during use and an accident, so it is considered defective. .
以上は一実施例であるが、本発明は認識しやす
い照明方式を特色とする自動検査装置で、従来の
目視検査と較べて認識や見落しがなく、検査の信
頼性が向上すると共に、自動組立工程内において
最も時間と人員とを要している検査工程の時間短
縮に著しく役立つ検査装置となる。 Although the above is just one example, the present invention is an automatic inspection device featuring an easy-to-recognize lighting system, which eliminates recognition and oversight compared to conventional visual inspection, improves inspection reliability, and automatically This is an inspection device that is extremely useful in reducing the time required for the inspection process, which requires the most time and manpower in the assembly process.
第１図は半導体装置の断面図、第２図ａ，ｂは
本発明の照明装置とパツケージとの位置を示す斜
視図、第３図は本発明の検出系ブロツク図、第４
図は検出領域を示す平面図である。
図中、１は半導体チツプ、３はパツケージ、５
はボンデングワイヤ、６はサークル灯、７は線状
電球、１０は顕微鏡、１１はCCDカメラ、１２
は２値化変換回路、１３はメモリ装置、１４は検
出回路、１５は方形環状検出領域を示す。
FIG. 1 is a sectional view of the semiconductor device, FIGS. 2a and 2b are perspective views showing the positions of the illumination device and the package of the present invention, FIG. 3 is a block diagram of the detection system of the present invention, and FIG.
The figure is a plan view showing the detection area. In the figure, 1 is a semiconductor chip, 3 is a package, and 5 is a semiconductor chip.
is a bonding wire, 6 is a circle lamp, 7 is a linear light bulb, 10 is a microscope, 11 is a CCD camera, 12
13 is a memory device, 14 is a detection circuit, and 15 is a rectangular annular detection area.
Claims (1)
内在する半導体パツケージ上のリード端子との間
が、ボンデイングワイヤによる多数のワイヤで互
に隣接するように配線接続されている半導体ボン
デイングワイヤの検査装置において、前記半導体
パツケージの全周囲側方向から該ワイヤ全体を照
明する照明装置を具備し、更に該半導体パツケー
ジの上方に位置して、前記照明装置により照明さ
れた全ボンデイングワイヤのワイヤ全体の配線形
状を映像信号で把える撮像装置と、撮像装置から
の映像信号を２値化させる２値化変換回路と、２
値化信号を記憶させるメモリ装置と、メモリ装置
より所要領域の２値化信号を抽出して、ボンデイ
ングワイヤ配線の欠陥形状を検出する検出回路と
を設けたことを特徴とする半導体ボンデイングワ
イヤの検査装置。1. A semiconductor bonding wire inspection device in which wiring pads on the surface of a semiconductor chip and lead terminals on a semiconductor package containing the chip are interconnected by a large number of bonding wires so as to be adjacent to each other, An illumination device is provided that illuminates the entire wire from the entire periphery of the semiconductor package, and is further positioned above the semiconductor package to image the wiring shape of the entire bonding wire illuminated by the illumination device. An imaging device that recognizes signals, a binarization conversion circuit that binarizes the video signal from the imaging device, and two
Inspection of semiconductor bonding wire, characterized in that it is provided with a memory device that stores a digitized signal, and a detection circuit that extracts the digitized signal of a required area from the memory device and detects the shape of a defect in the bonding wire wiring. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56041345A JPS57155743A (en) | 1981-03-20 | 1981-03-20 | Inspection device for semiconductor bonding wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56041345A JPS57155743A (en) | 1981-03-20 | 1981-03-20 | Inspection device for semiconductor bonding wire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155743A JPS57155743A (en) | 1982-09-25 |
| JPS6341220B2 true JPS6341220B2 (en) | 1988-08-16 |
Family
ID=12605923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56041345A Granted JPS57155743A (en) | 1981-03-20 | 1981-03-20 | Inspection device for semiconductor bonding wire |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155743A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5989538U (en) * | 1982-12-08 | 1984-06-18 | 日本電気ホームエレクトロニクス株式会社 | pellet pick up device |
| JPS59119843A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Automatic wire inspecting device |
| JPS59171129A (en) * | 1983-03-17 | 1984-09-27 | Fujitsu Ltd | Automatic wiring inspection device |
| JPH0781848B2 (en) * | 1985-05-20 | 1995-09-06 | 富士通株式会社 | Linear object inspection device |
| JPH0732188B2 (en) * | 1986-12-03 | 1995-04-10 | ビュー・エンジニアリング・インコーポレーテッド | Semiconductor device inspection equipment |
| JPH07111998B2 (en) * | 1989-08-18 | 1995-11-29 | 株式会社東芝 | Wire bonding inspection device |
| US5298989A (en) * | 1990-03-12 | 1994-03-29 | Fujitsu Limited | Method of and apparatus for multi-image inspection of bonding wire |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54130880A (en) * | 1978-04-03 | 1979-10-11 | Hitachi Ltd | Detector for chip position on semiconductor wafer |
| JPS55165647A (en) * | 1979-06-11 | 1980-12-24 | Mitsubishi Electric Corp | Device for automatically detecting whether wire bonding position is right or wrong |
-
1981
- 1981-03-20 JP JP56041345A patent/JPS57155743A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54130880A (en) * | 1978-04-03 | 1979-10-11 | Hitachi Ltd | Detector for chip position on semiconductor wafer |
| JPS55165647A (en) * | 1979-06-11 | 1980-12-24 | Mitsubishi Electric Corp | Device for automatically detecting whether wire bonding position is right or wrong |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155743A (en) | 1982-09-25 |
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