JPH0732188B2 - Semiconductor device inspection equipment - Google Patents
Semiconductor device inspection equipmentInfo
- Publication number
- JPH0732188B2 JPH0732188B2 JP28688386A JP28688386A JPH0732188B2 JP H0732188 B2 JPH0732188 B2 JP H0732188B2 JP 28688386 A JP28688386 A JP 28688386A JP 28688386 A JP28688386 A JP 28688386A JP H0732188 B2 JPH0732188 B2 JP H0732188B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- image pickup
- inspection
- magnification
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7865—Means for transporting the components to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ボールボンディング或いはウェッジボンディ
ングなどによるワイヤボンド工程を終了した半導体装置
のワイヤボンディング状態の外観検査を行う半導体装置
の検査装置に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device inspection apparatus that performs a visual inspection of a wire bonding state of a semiconductor device that has completed a wire bonding process such as ball bonding or wedge bonding. is there.
ワイヤボンディング状態の検査は、従来は、手動で作業
者による目視作業により行われていた。検査項目として
は、例えばボールボンディングの場合、ワイヤなし、ワ
イヤ切れ、ミスボンド(誤った場所にボンディングす
る)、ワイヤ高さ、ワイヤカール(余分な曲がり)、リ
フトボンド(ボンド部分の浮上がり)、パッド、リード
に対するボンド位置、ボール又はステッチの寸法、形状
などが挙げられる。Conventionally, the inspection of the wire bonding state has been manually performed by visual inspection by an operator. Items to be inspected include, in the case of ball bonding, no wire, wire break, misbond (bond at wrong place), wire height, wire curl (excessive bend), lift bond (lift of bond part), pad , The bond position with respect to the lead, the size or shape of the ball or stitch, and the like.
また、特開昭61−148828号公報にみられる如く、焦点深
度の浅いレンズを備えたカメラを用い、カメラを上下さ
せてワイヤの高さ方向の変形量を検査する試みもなされ
ていた。Further, as disclosed in JP-A-61-148828, an attempt has been made to inspect the amount of deformation of the wire in the height direction by using a camera equipped with a lens having a shallow depth of focus and moving the camera up and down.
しかしながら、従来の目視による検査では、検査結果に
ばらつきを伴い精度が悪く、手間もかかるので検査効率
が低いものであった。However, in the conventional visual inspection, the inspection efficiency is low because the inspection results vary and the accuracy is low and it takes time.
また、カメラを用いた検査では上下方向のカメラ移動に
時間がかかるばかりでなく、レンズが高倍率であって視
野が狭く、半導体装置のICチップ周辺の広い範囲をカバ
ーするためにはパッド,リード毎にカメラを水平移動す
ることが必要となり、時間を要し、検査効率が低かっ
た。In addition, in the inspection using a camera, it takes time to move the camera in the vertical direction, and the lens has a high magnification and a narrow field of view. Therefore, in order to cover a wide area around the IC chip of the semiconductor device, pads and leads are required. It was necessary to move the camera horizontally every time, which took time and the inspection efficiency was low.
本発明は、前記従来の問題点を解決し、外観検査の自動
化が容易に行え、検査精度及び検査効率が向上する半導
体装置の検査装置を提供することを目的とするものであ
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device inspection apparatus which solves the above conventional problems, facilitates automation of appearance inspection, and improves inspection accuracy and inspection efficiency.
本発明は上記の課題を解決する手段として、ワイヤボン
ドを行った後の半導体装置の外観検査を検査ステージに
て行う半導体装置の検査装置において、ワイヤボンドを
行った後の半導体装置を収納、供給するローディング装
置と、該ローディング装置により供給された半導体装置
を移送し、前記検査ステージを経て排出する移送装置
と、該移送装置により排出された半導体装置を受けてこ
れを収容するアンローディング装置と、前記検査ステー
ジにおいて半導体装置のICチップ及びその周辺全体を含
む視野を有し、撮像中心軸が検査点に一致する複数の低
倍率撮像装置と一つのパッド或いはリード及びその周辺
を含む視野を有する高倍率撮像装置とを備えた半導体装
置の撮像装置と、該撮像装置により得られた撮像信号を
デジタル処理して、予めメモリ回路に記憶されている標
準データと比較してボンディング状態の良否を判定する
画像処理装置と、該画像処理装置の判定信号に基づき半
導体装置に良否を区別する判定目印を付すマーキング装
置と、を備えたことを特徴とする半導体装置の検査装置
を提供せんとするものである。As a means for solving the above problems, the present invention stores and supplies a semiconductor device after wire bonding in a semiconductor device inspection device that performs an appearance inspection of a semiconductor device after wire bonding at an inspection stage. A loading device, a transfer device that transfers the semiconductor device supplied by the loading device and discharges the semiconductor device through the inspection stage, and an unloading device that receives the semiconductor device discharged by the transfer device and accommodates the semiconductor device. The inspection stage has a field of view including the IC chip of the semiconductor device and the entire periphery thereof, and a plurality of low-magnification image pickup devices whose image pickup central axes coincide with the inspection point and one pad or lead and a field of view including the periphery thereof. An image pickup device of a semiconductor device including a magnification image pickup device, and digitally processing an image pickup signal obtained by the image pickup device, An image processing device that determines the quality of the bonding state by comparing with standard data stored in the memory circuit, and a marking device that attaches a determination mark for distinguishing the quality of the semiconductor device based on the determination signal of the image processing device, It is intended to provide an inspection device for a semiconductor device, which is characterized by including:
本発明では、各低倍率撮像装置の視野は、半導体装置の
ICチップとその周辺のボンディング状態全体が一度に見
える程度であり、撮像装置を上下、水平方向に移動する
ことなく、主としてICチップの位置ズレ及びワイヤルー
プの形状,寸法を立体的に検査し、既に記憶されている
標準データと比較して不良の有無を検査する。In the present invention, the field of view of each low-magnification imaging device is
The entire bonding state of the IC chip and its surroundings can be seen at a time, and the positional deviation of the IC chip and the shape and dimensions of the wire loop are three-dimensionally inspected without moving the image pickup device vertically or horizontally. Inspect for defects by comparing with standard data already stored.
また、高倍率撮像装置の視野は、半導体装置の一つのパ
ッド或いはリードとその周辺のボンディング状態が見え
る程度であり、主としてボールやステッチ位置、形状、
寸法を検査する。この視野は各パッド及びリードごとに
移動するが、既に低倍率撮像装置で得られたICチップの
ズレ量に基づいて各パッドの位置が算出されメモリ回路
に記憶されているので、視野の移動に際しても高倍率撮
像時に改めてパッド位置を検出する必要がなく、その算
出位置を目標に迅速に移動を行うことができる。Further, the field of view of the high-magnification image pickup device is such that one pad or lead of the semiconductor device and the bonding state around it can be seen, and mainly the ball, stitch position, shape,
Inspect the dimensions. This field of view moves for each pad and lead, but since the position of each pad is calculated and stored in the memory circuit based on the amount of displacement of the IC chip already obtained with the low-magnification imaging device, Also, it is not necessary to detect the pad position again at the time of high-magnification imaging, and the calculated position can be quickly moved to the target.
本発明の実施例につき図面を用いて説明する。 Embodiments of the present invention will be described with reference to the drawings.
第1図において、検査装置の本体のベースフレーム1の
上にワイヤボンディング工程を終了したリードフレーム
などの半導体装置を収容した供給用マガジン2、該供給
用マガジン2を昇降せしめる供給用エレベータ3、外観
検査を行う検査ステージ4、供給用マガジン2の中の半
導体装置を一つづつ検査ステージ4に押し出して供給す
る押し出し装置5、検査ステージ4に供給された半導体
装置6を低倍率検査点7、高倍率検査点8、マーキング
点9を経て間欠的に移送せしめる移送装置10、検査及び
マーキングを終了した半導体装置を収容する収納用マガ
ジン11、該収納用マガジン11を昇降せしめる収納用エレ
ベータ12が備えられている。移送装置10は1組で複数個
の半導体装置を同時に移動せしめてもよく、複数組用い
て同時又は単独に動かしてもよい。In FIG. 1, a supply magazine 2 for accommodating a semiconductor device such as a lead frame which has completed a wire bonding process on a base frame 1 of a main body of an inspection apparatus, a supply elevator 3 for elevating and lowering the supply magazine 2, an external view The inspection stage 4 for inspecting, the extrusion device 5 for extruding and supplying the semiconductor devices in the supply magazine 2 one by one to the inspection stage 4, the semiconductor device 6 supplied to the inspection stage 4 for the low magnification inspection point 7, There are provided a transfer device 10 for intermittently transferring through a magnification inspection point 8, a marking point 9, a storage magazine 11 for storing a semiconductor device which has been inspected and marked, and a storage elevator 12 for moving the storage magazine 11 up and down. ing. The transfer device 10 may move a plurality of semiconductor devices at the same time in one set, or may use a plurality of sets to move simultaneously or independently.
半導体装置を撮像する撮像装置は、XYテーブル13に設け
られた複数の低倍率撮像装置14と、XYテーブル15に設け
られた高倍率撮像装置16とより成り、それぞれ低倍率検
査点7及び高倍率検査点8において半導体装置6の所定
部分の撮像を行うようになっている。17は撮像された画
像を表示するモニターである。An image pickup device for picking up an image of a semiconductor device includes a plurality of low-magnification image pickup devices 14 provided on an XY table 13 and a high-magnification image pickup device 16 provided on an XY table 15. An image of a predetermined portion of the semiconductor device 6 is picked up at the inspection point 8. Reference numeral 17 denotes a monitor that displays the captured image.
18は検査結果が不良である半導体装置の部分に不良なる
ことを表示するマークを付すマーキング装置であり、マ
ーキング点9において検査結果に応じてマークを付すよ
うになっている。Reference numeral 18 denotes a marking device for marking a defective portion of the semiconductor device, which has a defective inspection result, at the marking point 9 according to the inspection result.
各低倍率撮像装置14の視野は第2図に19にて示す如く、
一つのICチップ20とその周辺のボンディング状態全体が
一度に見える程度の視野であり、主としてICチップ20の
位置ズレ及びワイヤループの形状、寸法を検査する。The field of view of each low-magnification imager 14 is as shown at 19 in FIG.
The field of view is such that the entire bonding state of one IC chip 20 and its periphery can be seen at once, and mainly the positional deviation of the IC chip 20 and the shape and size of the wire loop are inspected.
ICチップ20が超LSIの如く特に大型の場合には、複数個
の視野に分け、XYテーブル13により移動して全体の検査
を行う。When the IC chip 20 is particularly large like a VLSI, it is divided into a plurality of fields of view and moved by the XY table 13 to inspect the whole.
高倍率撮像装置16の視野は第3図に21にて示す如く一つ
のパッド22(或いはリード)とその周辺のボンディング
状態が見える程度の視野であり主としてボールやステッ
チ位置、形状、寸法を検査する。この視野21は各パッド
及びリードごとに移動するが、既に低倍率撮像装置14で
得られたICチップ20のズレ量に基づいて各パッドの位置
が算出されメモリ回路に記憶されているので、視野の移
動に際しても高倍率撮像時に改めてパッド位置を検出す
る必要がなく、その算出位置を目標に迅速に移動を行う
ことができる。The field of view of the high-magnification image pickup device 16 is such that one pad 22 (or lead) and the bonding state around it can be seen as shown by 21 in FIG. 3, and mainly the ball, stitch position, shape and size are inspected. . The field of view 21 moves for each pad and lead, but since the position of each pad is calculated based on the displacement amount of the IC chip 20 already obtained by the low-magnification imaging device 14 and stored in the memory circuit, the field of view 21 It is not necessary to detect the pad position again at the time of high-magnification imaging even when the movement is performed, and the movement can be performed quickly with the calculated position as a target.
低倍率撮像装置14の一例を第4図,第5図,第6図に示
す。An example of the low-magnification imaging device 14 is shown in FIGS. 4, 5, and 6.
低倍率撮像装置14は、レンズ系23A,23B,23C、受光面24
A,24B,24C、光・電気変換器25A,25B,25C、鏡筒26A,26B,
26C、絞り45A,45B,45Cより成る撮像ユニット27A,27B,27
Cを備え、それぞれの受光面中心とレンズの中心を結ぶ
撮像中心軸28A,28B,28CはICチップ20上の低倍率検査点
7に一致し、平面図においては第6図に示す如く撮像中
心軸28Aと28Cとは逆向き(180°方向)に、撮像中心軸2
8Bは撮像中心軸28A,28Cと直角方向になっている。各レ
ンズ系23A,23B,23Cのレンズの面(レンズの主軸に対し
直角な面)及び受光面24A,24B,24Cは全てICチップ20の
表面と平行になるよう保持されている。即ち、平面42,4
3,44は平行となっている。The low-magnification image pickup device 14 includes lens systems 23A, 23B, 23C and a light-receiving surface 24.
A, 24B, 24C, optical / electrical converter 25A, 25B, 25C, lens barrel 26A, 26B,
Imaging unit 27A, 27B, 27 consisting of 26C, diaphragms 45A, 45B, 45C
The imaging center axes 28A, 28B, 28C, which are provided with C and connect the center of each light receiving surface and the center of the lens, coincide with the low-magnification inspection point 7 on the IC chip 20, and as shown in FIG. Imaging center axis 2 in the opposite direction (180 ° direction) to axes 28A and 28C
8B is perpendicular to the imaging center axes 28A and 28C. The lens surface of each lens system 23A, 23B, 23C (the surface perpendicular to the principal axis of the lens) and the light-receiving surfaces 24A, 24B, 24C are all held parallel to the surface of the IC chip 20. That is, the plane 42,4
3,44 are parallel.
各撮像ユニット27A,27B,27Cを上記の如く配備して撮像
すると撮像中心軸28A,28B,28CがICチップ20の面に対し
て傾いているにも拘らず、受光面24A,24B,24Cに結ばれ
る像は第2図の視野全体にピントが合い、しかもあたか
も直上から撮像した如く、例えばICチップ20は歪まずに
正方形のままの形で結像する。When the image pickup units 27A, 27B, and 27C are arranged and imaged as described above, the image pickup central axes 28A, 28B, and 28C are tilted with respect to the surface of the IC chip 20, but the light receiving surfaces 24A, 24B, and 24C are formed. The image formed is in focus over the entire field of view of FIG. 2 and, moreover, as if the image was taken from directly above, for example, the IC chip 20 is imaged in a square shape without distortion.
しかし、斜から撮像しているのであるから高さの差のあ
るものは、各撮像ユニット27A,27B,27Cごとに異なる形
状、寸法で撮像され、そのうちの少なくとも二つの撮像
ユニットの撮像信号をデジタル化して合成することによ
り各部の立体的な寸法、形状を算出することができる。However, since the images are taken from an oblique direction, images with different heights are imaged with different shapes and dimensions for each imaging unit 27A, 27B, 27C, and the imaging signals of at least two of these imaging units are digital. It is possible to calculate the three-dimensional size and shape of each part by synthesizing and composing.
三つの撮像ユニット27A,27B,27Cにて第2図の如きICチ
ップ20の撮像を行ったとき、例えばボンディング部29の
部分は、正常状態ならば、各撮像ユニットでそれぞれ第
7図(a),(b),(c)の如く撮像され、このうち
の二つの撮像より得られた各部の位置のデジタル量を用
いて演算することにより、ワイヤ30の任意の点P,Qなど
の立体的な位置を求めることができる。31はリード、32
はボール、33はステッチである。When the image pickup of the IC chip 20 as shown in FIG. 2 is performed by the three image pickup units 27A, 27B, and 27C, for example, if the bonding portion 29 is in a normal state, the image pickup units in FIG. , (B), (c) are imaged, and by calculating using the digital amount of the position of each part obtained from two of these images, the three-dimensional shape of an arbitrary point P, Q etc. of the wire 30 can be obtained. It is possible to find the desired position. 31 is the lead, 32
Is a ball and 33 is a stitch.
また例えば、ボンディング部29′は正常状態ならば、撮
像ユニット27Aにおいては第8図(a)の如く撮像さ
れ、撮像ユニット27Bにおいては第8図(b)の如く撮
像され、両者の像のワイヤ30の各位置をデジタル処理し
て合成演算することによりワイヤ30の任意の点の立体的
位置を求めることができる。Further, for example, when the bonding portion 29 'is in a normal state, the image pickup unit 27A takes an image as shown in FIG. 8A, and the image pickup unit 27B takes an image as shown in FIG. The three-dimensional position of an arbitrary point of the wire 30 can be obtained by digitally processing each position of 30 and performing a composite operation.
このようにして求められた実物に関するデータを、既に
記憶されている標準データと比較して、低倍率撮像装置
14により、ICチップ20の位置のズレ、各部のワイヤの欠
如、ワイヤ切れ、ミスボンド(他の場所にボンド)、ワ
イヤ高さの不適寸法、ワイヤカール(横ずれ、隣のワイ
ヤとの接触)、リフトボンド(ボール32又はステッチ33
がパッド22又はリード31から浮き上がり接触していない
こと)などの不良の有無を検査することができる。The low-magnification image pickup device is compared with the standard data that has already been stored by comparing the thus obtained data relating to the actual object.
Due to 14, the position of the IC chip 20 is misaligned, the wires in each part are missing, the wire is broken, the misbond (bonds to other locations), the wire height is inappropriate, the wire curl (lateral displacement, contact with the next wire), lift Bond (ball 32 or stitch 33
It is possible to inspect whether or not there is a defect such as that the pad floats up from the pad 22 or the lead 31 and is not in contact therewith.
この際、各ワイヤ1本ごとに検査する必要はなく、数本
づつまとめて全体を数ブロックごとに数度に分けるか、
或いは全体をまとめて一度にディジタル処理により検査
することができる。従って検査時間が極めて短くなり、
また許容限度が数値化されることにより検査にばらつき
がなく精度が向上する。At this time, it is not necessary to inspect each wire, and several wires may be put together into several blocks or divided into several blocks.
Alternatively, the whole can be inspected by digital processing all at once. Therefore, the inspection time becomes extremely short,
In addition, since the allowable limit is digitized, there is no variation in inspection and accuracy is improved.
撮像ユニットは2組のみでもよい。2組、或いは3組の
撮像ユニットの撮像中心軸の方向は任意に選ぶことがで
きる。例えば第4〜6図において撮像ユニット27Aのみ
を垂直としてもよい。The number of imaging units may be only two. The directions of the imaging center axes of the two or three sets of imaging units can be arbitrarily selected. For example, in FIGS. 4 to 6, only the image pickup unit 27A may be vertical.
第4〜6図の撮像ユニットのほかに、さらに別の認識用
ユニットを中央に垂直に設けてもよい。In addition to the image pickup unit shown in FIGS. 4 to 6, another recognition unit may be provided vertically in the center.
高倍率撮像装置16においては、第3図の如き狭い視野に
おいて拡大された画像により、パターン認識を行い、デ
ジタル処理によって得られたボール32(又はステッチ3
3)がパッド22(又はリード31)に対する位置ズレ、ボ
ール32(又はステッチ33)の形状、寸法を、予め記憶さ
れた標準データと比較して、不良の有無を検査すること
ができる。In the high-magnification image pickup device 16, pattern recognition is performed using an image enlarged in a narrow field of view as shown in FIG. 3, and a ball 32 (or stitch 3) obtained by digital processing is obtained.
3) The position deviation with respect to the pad 22 (or the lead 31), the shape and the size of the ball 32 (or the stitch 33) can be compared with standard data stored in advance to inspect for the presence or absence of a defect.
この場合、全てのボンディング部分を検査する必要はな
く、或る程度の数の抜き取り検査を行えばよく、また、
パッドの位置を改めて検査する必要がないので、その時
間を省略することができ、低倍率撮像による検査に見合
った短時間で高倍率撮像による検査ができ、全体の検査
効率が向上する。また、許容限度が数値化されるので検
査にばらつきがなく精度が向上する。In this case, it is not necessary to inspect all the bonding portions, and a certain number of sampling inspections may be performed.
Since it is not necessary to inspect the position of the pad again, the time can be omitted, the inspection by the high-magnification imaging can be performed in a short time commensurate with the inspection by the low-magnification imaging, and the overall inspection efficiency is improved. Further, since the allowable limit is digitized, there is no variation in the inspection and the accuracy is improved.
高倍率撮像装置16のレンズ系は高倍率なるがために焦点
深度が浅く、パッド22の面と、リード31の面との間の僅
かな高さの差に対してもそれぞれピント合わせをせねば
ならない。このピント合わせ操作は、装置内のレンズ系
の調節や、装置全体の上下などにより行うほか、薄いガ
ラスなどの透光体34をレンズ系の下に出し入れして両平
面のピント合わせの調節を行うようにしてもよい。Since the lens system of the high-magnification image pickup device 16 has a high magnification, the depth of focus is shallow, and it is necessary to focus on each of the slight height differences between the surface of the pad 22 and the surface of the lead 31. I won't. This focusing operation is performed by adjusting the lens system in the device, by moving the device up and down, and by adjusting the focus of both planes by inserting and removing the light-transmitting body 34 such as thin glass under the lens system. You may do it.
マーキング装置18は低倍率撮像装置14又は高倍率撮像装
置16からの検査信号に応じて不良のICチップの付近に不
良マークを付し、後工程における不良品排除の目印とす
る。The marking device 18 attaches a defect mark in the vicinity of the defective IC chip in accordance with an inspection signal from the low-magnification image pickup device 14 or the high-magnification image pickup device 16 to serve as a mark for rejecting defective products in a subsequent process.
第9図は信号系路の説明図であり、35はカメラコントロ
ールユニット、36は画像処理装置としてのパターン認識
ユニット、37はインターフェース制御系、38はCPU、39
はメモリ回路、40はステージドライバ、41は他のドライ
バである。FIG. 9 is an explanatory diagram of a signal system path, 35 is a camera control unit, 36 is a pattern recognition unit as an image processing device, 37 is an interface control system, 38 is a CPU, 39
Is a memory circuit, 40 is a stage driver, and 41 is another driver.
メモリ回路39には、検査各項目に関する標準データ、或
いは、二つの撮像ユニットからの平面位置データを合成
して立体位置を演算して求める演算プログラムなどが記
憶されている。The memory circuit 39 stores standard data regarding each inspection item, or a calculation program for calculating the three-dimensional position by combining plane position data from two image pickup units.
カメラコントロールユニット35においては、視野全体
を、或いは視野を複数個のブロックに分けて、1回又は
数回のフレームの走査を行いデジタル撮像信号を出力
し、パターン認識ユニット36においては、その入力信号
とメモリ回路39からの標準データに基づく標準データ信
号とを比較して、入力データ信号の正常、非正常を判定
し、不良の場合はマーキング装置18に信号を送り、該当
するICの付近にマークを付す。In the camera control unit 35, the entire field of view or the field of view is divided into a plurality of blocks to scan a frame once or several times to output a digital image pickup signal, and in the pattern recognition unit 36, the input signal And a standard data signal based on standard data from the memory circuit 39 are compared to determine whether the input data signal is normal or abnormal.If the input data signal is defective, a signal is sent to the marking device 18 to mark near the corresponding IC. Attach.
モニタ17には検査情報として撮像画面のほかに、検査数
値、不良個所、不良分析などをリアルタイムで表示でき
るようになっているので、状況により直ちにボンディン
グマシンにフィードバックしてボンディング条件の設定
などのアクションを速やかに行うことができる。In addition to the imaging screen as the inspection information, the monitor 17 can display the inspection numerical value, defect location, defect analysis, etc. in real time, so that the situation can be immediately fed back to the bonding machine and actions such as setting of bonding conditions performed. Can be done promptly.
また、検査データを集計することにより前工程での不良
発生箇所への敏速な対応が可能となり生産の歩留向上が
はかれる。In addition, by collecting inspection data, it is possible to promptly deal with a defect occurrence point in the previous process, and improve the production yield.
第10図、第11図は低倍率検査点7における照明具の例を
示す。低倍率検査点7におけるICチップ20を取囲むよう
に、かつ検査面に接近して低い位置に、環状の光源を持
つ照明灯46が設けられる。周囲から、かつ低い位置から
照明されることにより、ボンディングワイヤ30の立体的
な形状を誤りなく、明瞭に撮像することができる。FIG. 10 and FIG. 11 show an example of the illuminator at the low magnification inspection point 7. An illumination lamp 46 having an annular light source is provided so as to surround the IC chip 20 at the low-magnification inspection point 7 and at a low position close to the inspection surface. By being illuminated from the surroundings and from a low position, the three-dimensional shape of the bonding wire 30 can be clearly imaged without error.
本発明によれば、低倍率撮像装置によって視野が広く、
深い焦点深度によって広い視野で立体的にピントが合い
易く、撮像装置を上下,水平方向に移動する必要がなく
迅速に検査することができ、また高倍率撮像装置は低倍
率撮像装置による検査により走査の一部が省略され、時
間も短縮され、全体の検査効率、検査精度が向上し、し
かも半導体装置のバンディング部の外観検査が容易に自
動化され、許容範囲が数値化されて検査のばらつきがな
い等の実用上極めて大なる効果を奏する。According to the present invention, the low-magnification imaging device provides a wide field of view,
Due to the deep depth of focus, it is easy to focus three-dimensionally in a wide field of view, and it is possible to quickly inspect without the need to move the image pickup device vertically or horizontally. Also, the high-magnification image pickup device scans by the low-magnification image pickup device Part is omitted, the time is shortened, the overall inspection efficiency and inspection accuracy are improved, and the appearance inspection of the banding part of the semiconductor device is easily automated, and the allowable range is quantified and there is no variation in inspection. It has an extremely great effect in practical use.
図面は本発明の実施例に関するもので、第1図は全体の
斜視図、第2図は低倍率撮像装置の視野、第3図は高倍
率撮像装置の視野、第4図は低倍率撮像装置の低倍率検
査点7を通り半導体装置6の移送方向に平行な垂直面に
よる断面正面図、第5図はそのI−I線断面側面図、第
6図はその平面的配置図、第7図(a),(b),
(c)は一つのボンディング部を異なる撮像ユニットで
撮像した場合の像の見え方の説明図、第8図(a),
(b)は他の一つのボンディング部を異なる撮像ユニッ
トで撮像した場合の像の見え方の説明図、第9図は信号
系路の説明図、第10図は照明具の実施例の平面図、第11
図はそのII−II線断面正面図である。 1…ベースフレーム、2…供給用マガジン、3…供給用
エレベータ、4…検査ステージ、5…押し出し装置、6
…半導体装置、7…低倍率検査点、8…高倍率検査点、
9…マーキング点、10…移送装置、11…収納用マガジ
ン、12…収納用エレベータ、13…XYテーブル、14…低倍
率撮像装置、15…XYテーブル、16…高倍率撮像装置、17
…モニター、18…マーキング装置、19…視野、20…ICチ
ップ、21…視野、22…パッド、23A,23B,23C…レンズ
系、24A,24B,24C…受光面、25A,25B,25C…光・電気変換
器、26A,26B,26C…鏡筒、27A,27B,27C…撮像ユニット、
28A,28B,28C…撮像中心軸、29,29′…ボンディング部、
30…ワイヤ、31…リード、32…ボール、33…ステッチ、
34…透光体、35…カメラコントロールユニット、36…パ
ターン認識ユニット、37…インターフェース制御系、38
…CPU、39…メモリ回路、40…ステージドライバ、41…
他のドライバ、42,43,44…平面、45A,45B,45C…絞り、4
6…照明灯。The drawings relate to an embodiment of the present invention. FIG. 1 is an overall perspective view, FIG. 2 is a field of view of a low-magnification imager, FIG. 3 is a field of view of a high-magnification imager, and FIG. 4 is a low-magnification imager. 5 is a cross-sectional front view of a vertical plane parallel to the transfer direction of the semiconductor device 6 passing through the low-magnification inspection point 7 of FIG. 5, FIG. 5 is a cross-sectional side view of the II line, FIG. (A), (b),
FIG. 8 (a) is an explanatory view of how an image looks when one bonding portion is imaged by different imaging units, FIG. 8 (a),
(B) is an explanatory view of how an image looks when another one of the bonding parts is picked up by a different imaging unit, FIG. 9 is an explanatory view of a signal system path, and FIG. 10 is a plan view of an embodiment of a lighting fixture. , 11th
The figure is a front view taken along the line II-II. DESCRIPTION OF SYMBOLS 1 ... Base frame, 2 ... Supply magazine, 3 ... Supply elevator, 4 ... Inspection stage, 5 ... Extrusion device, 6
... Semiconductor device, 7 ... Low magnification inspection point, 8 ... High magnification inspection point,
9 ... Marking point, 10 ... Transfer device, 11 ... Storage magazine, 12 ... Storage elevator, 13 ... XY table, 14 ... Low magnification image pickup device, 15 ... XY table, 16 ... High magnification image pickup device, 17
… Monitor, 18… Marking device, 19… View, 20… IC chip, 21… View, 22… Pad, 23A, 23B, 23C… Lens system, 24A, 24B, 24C… Light receiving surface, 25A, 25B, 25C… Light・ Electrical converter, 26A, 26B, 26C ... Lens barrel, 27A, 27B, 27C ... Imaging unit,
28A, 28B, 28C ... Imaging center axis, 29, 29 '... Bonding part,
30 ... wire, 31 ... lead, 32 ... ball, 33 ... stitch,
34 ... Translucent body, 35 ... Camera control unit, 36 ... Pattern recognition unit, 37 ... Interface control system, 38
… CPU, 39… Memory circuit, 40… Stage driver, 41…
Other drivers, 42, 43, 44 ... Plane, 45A, 45B, 45C ... Aperture, 4
6… Lighting.
フロントページの続き (72)発明者 ツシャー・コトハリ アメリカ合衆国カリフォルニア州93063 シミ・バレー,ノース・ボヤジャー・アベ ニュー1650 ビュー・エンジニアリング・ インコーポレーテッド内 (72)発明者 バレリー・リウドジウス アメリカ合衆国カリフォルニア州93063 シミ・バレー,ノース・ボヤジャー・アベ ニュー1650 ビュー・エンジニアリング・ インコーポレーテッド内 (72)発明者 上原子 隆 東京都西多摩郡羽村町栄町3丁目1番地の 5 海上電機株式会社内 (56)参考文献 特開 昭57−155743(JP,A) 特開 昭61−148828(JP,A)Front Page Continued (72) Inventor Tushar Kotohari, California, USA 93063 North Voyageur Avenue, 1650 View Engineering Incorporated (72) Inventor Valerie Riudusius, California, USA 93063 Simi Valley, North Voyager Avenue 1650 View Engineering Incorporated (72) Inventor Taka Ueato 3-5-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Kaiji Electric Co., Ltd. (56) Reference JP-A-57- 155743 (JP, A) JP 61-148828 (JP, A)
Claims (1)
観検査を検査ステージにて行う半導体装置の検査装置に
おいて、ワイヤボンドを行った後の半導体装置を収納、
供給するローディング装置と、該ローディング装置によ
り供給された半導体装置を移送し、前記検査ステージを
経て排出する移送装置と、該移送装置により排出された
半導体装置を受けてこれを収容するアンローディング装
置と、前記検査ステージに設けられた半導体装置のICチ
ップ及びその周辺全体を含む視野を有し、撮像中心軸が
検査点に一致する複数の低倍率撮像装置と一つのパッド
或いはリード及びその周辺を含む視野を有する高倍率撮
像装置とを備えた半導体装置の撮像装置と、該撮像装置
により得られた撮像信号をデジタル処理して、予めメモ
リ回路に記憶されている標準データと比較してボンディ
ング状態の良否を判定する画像処理装置と、該画像処理
装置の判定信号に基づき半導体装置に良否を区別する判
定目印を付すマーキング装置と、を備えたことを特徴と
する半導体装置の検査装置。1. A semiconductor device inspecting apparatus for performing visual inspection of a semiconductor device after wire bonding at an inspection stage, wherein the semiconductor device after wire bonding is stored.
A loading device for supplying, a transfer device for transferring the semiconductor device supplied by the loading device and discharging the semiconductor device through the inspection stage, and an unloading device for receiving the semiconductor device discharged by the transfer device and accommodating the semiconductor device. A plurality of low-magnification image pickup devices having a field of view including the IC chip of the semiconductor device provided on the inspection stage and the entire periphery thereof, and a plurality of low-magnification image pickup devices whose image pickup central axes coincide with the inspection point and one pad or lead and its periphery An image pickup device of a semiconductor device including a high-magnification image pickup device having a field of view, and an image pickup signal obtained by the image pickup device are digitally processed, and compared with standard data stored in a memory circuit in advance to determine a bonding state. An image processing apparatus that determines pass / fail, and a mark that marks a semiconductor device based on a determination signal of the image processing apparatus. Inspection apparatus for a semiconductor device characterized by comprising: a ring device.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28688386A JPH0732188B2 (en) | 1986-12-03 | 1986-12-03 | Semiconductor device inspection equipment |
US07/128,329 US4872052A (en) | 1986-12-03 | 1987-12-03 | Semiconductor device inspection system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28688386A JPH0732188B2 (en) | 1986-12-03 | 1986-12-03 | Semiconductor device inspection equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63144532A JPS63144532A (en) | 1988-06-16 |
JPH0732188B2 true JPH0732188B2 (en) | 1995-04-10 |
Family
ID=17710233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28688386A Expired - Lifetime JPH0732188B2 (en) | 1986-12-03 | 1986-12-03 | Semiconductor device inspection equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0732188B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239449A (en) * | 1988-07-28 | 1990-02-08 | Matsushita Electric Ind Co Ltd | Inspection of wire bonding |
JPH04116844A (en) * | 1990-09-06 | 1992-04-17 | Nec Corp | Device for discriminating assembling property of ic |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57155743A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Inspection device for semiconductor bonding wire |
JPS61148828A (en) * | 1984-12-24 | 1986-07-07 | Toshiba Corp | Inspection of wire bonding |
-
1986
- 1986-12-03 JP JP28688386A patent/JPH0732188B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63144532A (en) | 1988-06-16 |
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