JPH0569304B2 - - Google Patents

Info

Publication number
JPH0569304B2
JPH0569304B2 JP28688286A JP28688286A JPH0569304B2 JP H0569304 B2 JPH0569304 B2 JP H0569304B2 JP 28688286 A JP28688286 A JP 28688286A JP 28688286 A JP28688286 A JP 28688286A JP H0569304 B2 JPH0569304 B2 JP H0569304B2
Authority
JP
Japan
Prior art keywords
inspection
imaging
electrical signal
lens
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP28688286A
Other languages
Japanese (ja)
Other versions
JPS63144531A (en
Inventor
Waisunaa Rarufu
Hansen Peetaa
Takashi Kamiharashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaijo Corp
Original Assignee
Kaijo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaijo Corp filed Critical Kaijo Corp
Priority to JP61286882A priority Critical patent/JPS63144531A/en
Priority to US07/128,329 priority patent/US4872052A/en
Publication of JPS63144531A publication Critical patent/JPS63144531A/en
Publication of JPH0569304B2 publication Critical patent/JPH0569304B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10162Shape being a cuboid with a square active surface

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ボールボンデイング或いはウエツジ
ボンデイングなどによるワイヤボンド工程を終了
した半導体装置のワイヤボンデイング状態の外観
検査を撮像により行う半導体装置の撮像検査装置
に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an imaging inspection of a semiconductor device in which the appearance of the wire bonding state of a semiconductor device that has completed a wire bonding process such as ball bonding or wedge bonding is inspected by imaging. It is related to the device.

〔従来技術〕[Prior art]

ワイヤボンデイング状態の検査は、従来は、手
動で作業者による目視作業により行われている。
検査項目としては、例えばボールボンデイングの
場合、ワイヤなし、ワイヤ切れ、ミスボンド(誤
つた場所にはボンデイングする)、ワイヤ高さ、
ワイヤカール(余分な曲がり)、リフトボンド
(ボンド部分の浮上がり)、パツド、リードに対す
るボンド位置、ボール又はステツチの寸法、形状
などが挙げられる。
Inspection of the wire bonding state has conventionally been performed manually and visually by an operator.
Inspection items include, for example, in the case of ball bonding, no wire, wire breakage, misbond (bond in the wrong place), wire height,
These include wire curl (excessive bending), lift bond (lifting of the bond), pad, bond position relative to the lead, ball or stitch size and shape, etc.

このうち「ワイヤなし」から「リフトボンド」
までの項目の検査は、ICチツプとその周辺のボ
ンデイング部を全部含む広い視野を有する低倍率
の顕微鏡を用いて、目視により検査が行われてい
た。
Among these, from “no wire” to “lift bond”
Inspections for the previous items were performed visually using a low-magnification microscope with a wide field of view that included the entire IC chip and its surrounding bonding parts.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、従来におけるこのような手段に
よる検査では、両眼顕微鏡を用いてワイヤの立体
的な形状を把握することはできるものの、目視で
あるので、多数のボンデイング部位について多数
の項目の検査を行うことに多くの時間を要して検
査効率が低く、しかも、ボンデイング状態の良、
不良を判定するのに検査員の勘に頼つている状態
であるので検査結果にばらつきが多く、しかも顕
微鏡で手前の上方から斜め下方に向けて目視する
ため、手前側と向こう側とで、遠近による像の歪
のためワイヤのたわみ量などの判断に誤りを生じ
易く、検査精度が低いものであつた。
However, in conventional inspections using such means, although it is possible to grasp the three-dimensional shape of the wire using a binocular microscope, since it is a visual inspection, it is difficult to inspect a large number of items on a large number of bonding parts. Inspection efficiency is low because it takes a lot of time, and the bonding condition is good.
Because the inspector relies on his or her intuition to judge defects, there are many variations in the inspection results.Furthermore, since the inspection is performed using a microscope from above the front to diagonally downward, there is a difference in distance between the front and back sides. Due to the distortion of the image caused by this, it was easy to make errors in determining the amount of deflection of the wire, resulting in low inspection accuracy.

また、焦点深度の極めて浅いレンズを用い、カ
メラを上下せしめてワイヤの高さ方向の各点にピ
ントを合わせるようにしてワイヤの高さ方向の変
形量を検査する試みもなされているが、上下方向
のカメラ移動に時間がかかるほかに、レンズが高
倍率であり視野が狭く、ICチツプ周辺の広い範
囲をカバーするためには、パツド、リードごとに
カメラを水平面内に移動するこのが必要となり時
間を要し、検査効率が低かつた。
In addition, attempts have been made to inspect the amount of deformation in the height direction of the wire by using a lens with an extremely shallow depth of focus and moving the camera up and down to focus on each point in the height direction of the wire. In addition to taking time to move the camera in different directions, the lens has a high magnification and has a narrow field of view, and in order to cover a wide area around the IC chip, it is necessary to move the camera in a horizontal plane for each pad and lead. It was time consuming and the inspection efficiency was low.

本発明は従来のものの上記の問題点を解決し、
広い視野内における画像からの多数の入力データ
信号を極めて短時間に判定して検査効率が向上す
るとともに、良、不良の判断基準が定量化され、
しかも検査面全体に遠近による歪も生ぜず、誤差
が少なくなり、検査精度が向上する半導体装置の
撮像検査装置を提供することを目的とするもので
ある。
The present invention solves the above problems of the conventional ones,
Inspection efficiency is improved by determining a large number of input data signals from images within a wide field of view in an extremely short time, and the criteria for determining good and bad are quantified.
Moreover, it is an object of the present invention to provide an imaging inspection apparatus for a semiconductor device that does not cause distortion due to distance on the entire inspection surface, reduces errors, and improves inspection accuracy.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記の問題点を解決するための手段
として、ワイヤボンドを行つた後の半導体装置の
外観検査を行う半導体装置の撮像検査装置におい
て、単数または複数のレンズより成るレンズ系
と、該レンズ系による像を結像せしめる受光面と
を有する複数組の撮像ユニツトと、該撮像ユニツ
トの前記受光面における画像信号を電気信号に変
える光・電気信号変換器と、該電気信号をデジタ
ル化し、各撮像ユニツトのうち少なくとも二つの
撮像ユニツトからのデジタル信号を合成演算して
対象物の立体位置のデータを得る演算回路と、検
査項目に関するデジタル化された標準データを記
憶するメモリ回路と、前記光・電気信号から変換
した電気信号に基づきデジタル化された入力デー
タ信号と前記標準データに基づく標準データ信号
とを比較して該入力データの正常、非正常を判定
する画像処理装置とを備え、前記撮像ユニツト
は、それぞれの受光面が、検査されるべき半導体
装置の検査面に対し平行に配備され、かつ、それ
ぞれの撮像ユニツトの受光面中心とレンズ系中心
とを結ぶ中心軸が、前記検査面にて交差するよう
配備されていることを特徴とする半導体装置の検
査用撮像装置を提供せんとするものである。
As a means for solving the above-mentioned problems, the present invention provides an imaging inspection apparatus for a semiconductor device that performs an external appearance inspection of a semiconductor device after wire bonding. a plurality of imaging units each having a light-receiving surface for forming an image by a lens system; an optical/electrical signal converter that converts an image signal on the light-receiving surface of the imaging unit into an electrical signal; and digitizing the electrical signal. an arithmetic circuit that synthesizes digital signals from at least two of the imaging units to obtain data on the three-dimensional position of the object; a memory circuit that stores digitized standard data regarding inspection items; - an image processing device that compares an input data signal digitized based on an electrical signal converted from an electrical signal with a standard data signal based on the standard data to determine whether the input data is normal or abnormal; Each of the imaging units has a light-receiving surface parallel to the inspection surface of the semiconductor device to be inspected, and a central axis connecting the center of the light-receiving surface of each imaging unit and the center of the lens system is parallel to the inspection surface. It is an object of the present invention to provide an imaging device for inspecting a semiconductor device, which is characterized in that it is arranged so as to intersect with each other.

〔作用〕[Effect]

本発明は上記の如く構成されているので、低倍
率のレンズを用いることができ、ICチツプまわ
りのボンデイングの全領域を一つの広い視野に入
れた状態で撮像検査ができ、撮像装置を水平面内
にパツド、リードごとに移動させる必要もなく、
対象物の立体的な形状を把握するのに低倍率レン
ズを用いることができるので焦点深度が深く、撮
像装置を上下に移動することも必要なく、これら
移動に関する時間を必要とせず、また、広い視野
の全領域の多くの部位の、多くの種類の信号を、
1フレーム又は数フレームの短時間の走査にて標
準データ信号と比較し判定することができるの
で、検査時間が短縮されて検査効率が向上する。
Since the present invention is configured as described above, it is possible to use a lens with low magnification, to perform imaging inspection with the entire bonding area around the IC chip in one wide field of view, and to move the imaging device in a horizontal plane. There is no need to move each lead,
Since a low magnification lens can be used to grasp the three-dimensional shape of the object, the depth of focus is deep, there is no need to move the imaging device up and down, and there is no need for the time associated with these movements. Many types of signals from many parts of the entire visual field,
Since it is possible to make a determination by comparing with a standard data signal by scanning one frame or several frames in a short time, the inspection time is shortened and the inspection efficiency is improved.

また、入力データの正常、非正常の判断が定量
化されて、検査員の個人差によるばらつきが少な
く、広い視野全体に遠近の歪がないことにより誤
差が少なくなり、また低倍率レンズを用いること
ができるため焦点深度が深く、視野全体にピント
が合い易く、検査精度の向上をはかることができ
る。
In addition, the judgment of normal or abnormal input data is quantified, there is less variation due to individual differences among inspectors, there is no distortion of perspective over a wide field of view, which reduces errors, and it is possible to use low-magnification lenses. This allows for a deep depth of focus, making it easy to focus on the entire field of view, and improving inspection accuracy.

〔実施例〕〔Example〕

本発明の実施例につき図面を用いて説明する。 Embodiments of the present invention will be described with reference to the drawings.

第1図において、検査装置の本体のベースフレ
ーム1の上にワイヤボンデイング工程を終了した
リードフレームなどの半導体装置を収容した供給
用マガジン2、該供給用マガジン2を昇降せしめ
る供給用エレベータ3(例えば実開昭61−116632
号公報、実開昭61−119532号公報、実開昭62−
20017号公報参照)、外観検査を行う検査ステージ
4、供給用マガジン2の中の半導体装置を一つづ
つ検査ステージ4に押し出して供給する押し出し
装置5(例えば実開昭61−185741号公報、実開昭
62−2543号公報参照)によつて検査ステージ4に
供給された半導体装置6を低倍率検査点7、高倍
率検査点8、マーキング点9を経て間欠的に移送
せしめる移送装置10(例えば特開昭63−9946号
公報参照)、検査及びマーキングを終了した半導
体装置を収容する収納用マガジン11、該収納用
マガジン11を昇降せしめる収納用エレベータ1
2が備えられている。移送装置10は1組で複数
個の半導体装置を同時に移動せしめてもよく、複
数組用いて同時又は単独に動かしてもよい。
In FIG. 1, a supply magazine 2 containing semiconductor devices such as lead frames that have undergone a wire bonding process is placed on a base frame 1 of the main body of the inspection device, and a supply elevator 3 (e.g. Jitsukai Showa 61-116632
Publication No. 119532, Publication No. 119532, Publication No. 119532, Utility Model Application No. 62-
20017 Publication), an inspection stage 4 that performs a visual inspection, and an extrusion device 5 that pushes out and supplies the semiconductor devices in the supply magazine 2 one by one to the inspection stage 4 (for example, Utility Model Application Laid-Open No. 61-185741, Kaisho
62-2543)), the semiconductor device 6 supplied to the inspection stage 4 is intermittently transferred through a low magnification inspection point 7, a high magnification inspection point 8, and a marking point 9. (See Publication No. 63-9946), a storage magazine 11 that accommodates semiconductor devices that have been inspected and marked, and a storage elevator 1 that raises and lowers the storage magazine 11.
2 are provided. One set of the transfer device 10 may move a plurality of semiconductor devices at the same time, or a plurality of sets may be used to move the semiconductor devices simultaneously or individually.

半導体装置を撮像する撮像装置は、XYテーブ
ル13に設けられた低倍率撮像装置14と、XY
テーブル15に設けられた高倍率撮像装置16と
より成り、それぞれ低倍率検査点7及び高倍率検
査点8において半導体装置6の所定部分の撮像を
行うようになつている。17は撮像された画像を
表示するモニターである。
An imaging device for imaging a semiconductor device includes a low magnification imaging device 14 provided on an XY table 13 and an XY
It consists of a high-magnification imaging device 16 provided on a table 15, and is configured to image a predetermined portion of the semiconductor device 6 at a low-magnification inspection point 7 and a high-magnification inspection point 8, respectively. 17 is a monitor that displays the captured image.

18は検査結果が不良である半導体装置の部分
に不良なることを表示するマークを付すマーキン
グ装置であり、マーキング点9において検査結果
に応じてマークを付すようになつている。
A marking device 18 attaches a mark indicating that the semiconductor device is defective to a portion of the semiconductor device that has a defective inspection result, and is adapted to attach a mark at a marking point 9 according to the inspection result.

低倍率撮像装置14の視野は第2図に19にて
示す如く、一つのICチツプ20の周辺のボンデ
イング状態全体が一度に見える程度の視野であ
り、主としてICチツプ20の位置ズレ及びワイ
ヤループの形状、寸法を検査する。
The field of view of the low-magnification imaging device 14, as shown at 19 in FIG. Inspect shape and dimensions.

ICチツプ20が超LSIの如く特に大型の場合に
は複数個の視野に分け、XYテーブル13により
移動して全体の検査を行う。
If the IC chip 20 is particularly large, such as a super LSI, it is divided into a plurality of fields of view and moved by the XY table 13 to inspect the whole.

高倍率撮像装置16の視野は第3図に21に示
す如く一つのパツド22(或いはリード)付近の
ボンデイング状態が見える程度の視野であり主と
してボールやステツチ位置、形状、寸法を検査す
る。この視野21は各パツド及びリードごとに移
動するが、既に低倍率撮像装置14で得られた
ICチツプ20のズレ量に基づいて各パツドの位
置が算出されメモリ回路に記憶されているので、
視野の移動に際しても高倍率撮像時に改めてパツ
ド位置を検出する必要がなく、その算出位置を目
標に迅速に移動を行うことができる。
The field of view of the high magnification imaging device 16 is such that the bonding condition near one pad 22 (or lead) can be seen, as shown at 21 in FIG. 3, and the position, shape, and size of the ball and stitches are mainly inspected. This field of view 21 moves for each pad and lead, but it has already been obtained with the low magnification imaging device 14.
Since the position of each pad is calculated based on the amount of deviation of the IC chip 20 and stored in the memory circuit,
When moving the field of view, there is no need to detect the pad position again during high-magnification imaging, and the pad position can be quickly moved using the calculated position as the target.

低倍率撮像装置14の一例を第4図,第5図,
第6図に示す。
Examples of the low magnification imaging device 14 are shown in FIGS.
It is shown in FIG.

低倍率撮像装置14は、単数又は複数のレンズ
により構成されるレンズ系23A,23B,23
C、ビジコン又は固体撮像素子などを備えた受光
面24A,24B,24C、光・電気変換器25
A,25B,25C、鏡筒26A,26B,26
C、絞り45A,45B,45Cより成る撮像ユ
ニツト27A,27B,27Cを備え、それぞれ
の受光面中心とレンズの中心を結ぶ中心軸28
A,28B,28Cは検査されるべきICチツプ
20の検査面上の低倍率検査点7に一致して交差
し、平面図においては第6図に示す如く中心軸2
8Aと28Cとは逆向き(180°方向)に、中心軸
28Bは中心軸28A,28Cと直角方向になつ
ている。各レンズ系23A,23B,23Cのレ
ンズの面(レンズの主軸に対し直角な面)及び受
光面24A,24B,24Cは全て検査面である
ICチツプ20の表面と平行になるよう保持され
ている。即ち、平面41,42,43は平行とな
つている。
The low-magnification imaging device 14 includes lens systems 23A, 23B, and 23 each composed of one or more lenses.
C, light-receiving surfaces 24A, 24B, 24C equipped with a vidicon or solid-state image sensor, and an optical/electrical converter 25
A, 25B, 25C, lens barrel 26A, 26B, 26
C, an imaging unit 27A, 27B, 27C consisting of an aperture 45A, 45B, 45C, and a central axis 28 connecting the center of each light-receiving surface and the center of the lens.
A, 28B, and 28C coincide with and intersect with the low magnification inspection point 7 on the inspection surface of the IC chip 20 to be inspected, and in the plan view, the central axis 2 as shown in FIG.
8A and 28C are oriented in opposite directions (180° direction), and central axis 28B is perpendicular to central axes 28A and 28C. The lens surfaces of each lens system 23A, 23B, 23C (surfaces perpendicular to the main axis of the lens) and the light receiving surfaces 24A, 24B, 24C are all inspection surfaces.
It is held parallel to the surface of the IC chip 20. That is, the planes 41, 42, and 43 are parallel.

各撮像ユニツト27A,27B,27Cを上記
の如く配備して撮像すると中心軸28A,28
B,28CがICチツプ20の面に対して傾いて
いるにも拘らず、受光面24A,24B,24C
に結ばれる像は第2図の視野全体にピントが合
い、しかもあたかも直上から撮像した如く、例え
ばICチツプ20はレンズからの距離の遠近によ
る形の歪を生ずることなく矩形又は正方形のまま
の形で結像する。
When the respective imaging units 27A, 27B, 27C are arranged as described above and imaged, the central axes 28A, 28
Although B and 28C are tilted with respect to the surface of the IC chip 20, the light receiving surfaces 24A, 24B, and 24C are
The image formed is in focus over the entire field of view in Fig. 2, and it looks as if the image was taken from directly above.For example, the IC chip 20 remains in a rectangular or square shape without distortion due to the distance from the lens. to form an image.

しかし、斜から撮像しているのであるから高さ
の差のあるものは、各撮像ユニツト27A,27
B,27Cごとに異なる形状、寸法で撮像され、
そのうちの少なくとも二つの撮像ユニツトの撮像
信号をデジタル化して得られた各受光面での平面
的位置の信号を演算回路により演算して合成する
ことにより各部の立体的な位置を算出し、寸法、
形状のデジタル信号を得ることができる。
However, since images are taken from an oblique angle, objects with different heights are
B, 27C are imaged with different shapes and dimensions,
The three-dimensional position of each part is calculated by calculating and synthesizing the two-dimensional position signals on each light-receiving surface obtained by digitizing the imaging signals of at least two of the imaging units using an arithmetic circuit.
A digital signal of the shape can be obtained.

三つの撮像ユニツト27A,27B,27Cに
て第2図の如きICチツプ20の撮像を行つたと
き、例えばボンデイング部29の部分は、正常状
態ならば、各撮像ユニツトでそれぞれ第7図a,
b,cの如く撮像され、このうちの二つの撮像ユ
ニツトの像を走査して、得られた各部の平面的な
位置のデジタル量を用いて合成演算することによ
り、ワイヤ30の所定の任意の点P,Qなどの立
体的な位置を求めることができる。31はリー
ド、32はボール、33はステツチである。
When the three imaging units 27A, 27B, and 27C take images of the IC chip 20 as shown in FIG.
The images of the wire 30 are captured as shown in FIGS. The three-dimensional positions of points P, Q, etc. can be determined. 31 is a lead, 32 is a ball, and 33 is a stitch.

また例えば、ボンデイング部29′は正常状態
ならば、撮像ユニツト28A,28Cにおいては
第8図aの如く撮像され、撮像ユニツト28Bに
おいては第8図bの如く撮像され、両者の像を走
査してワイヤ30の各位置をデジタル処理して合
成演算することによりワイヤ30の任意の点の立
体的位置を求めることができる。
For example, if the bonding section 29' is in a normal state, the imaging units 28A and 28C take an image as shown in FIG. 8a, and the imaging unit 28B takes an image as shown in FIG. 8b, and both images are scanned. By digitally processing each position of the wire 30 and performing a composite calculation, the three-dimensional position of any point on the wire 30 can be determined.

このようにして求められた実物に関するデジタ
ル入力データ信号を、既にメモリ回路に記憶され
ているデジタル標準データ信号と比較して、低倍
率撮像装置14により、ICチツプ20の位置の
ズレや、各部のワイヤの欠如、ワイヤ切れ、ミス
ボンド(他の正しくない場所にボンド)、ワイヤ
高さの不適寸法、ワイヤカール(横ずれ、隣のワ
イヤとの接触)、リフトボンド(ボール32又は
ステツチ33がパツド22又はリード31から浮
き上がり接触していないこと)などの不良の有無
を検査することができる。
The digital input data signal regarding the actual object obtained in this way is compared with the digital standard data signal already stored in the memory circuit, and the low magnification imaging device 14 detects the positional deviation of the IC chip 20 and the Missing wires, broken wires, misbonds (bonds in other incorrect locations), incorrect wire heights, wire curls (lateral deviation, contact with adjacent wires), lift bonds (ball 32 or stitch 33 bonding to pad 22 or It is possible to inspect the presence or absence of a defect such as the lead 31 floating up from the lead 31 and not making contact.

この際、各ワイヤ1本ごとに検査する必要はな
く、数本づつまとめて全体を数ブロツクごとに走
査して数度のフレームに分けるか、或いは全体を
1フレームの走査によりデジタル処理して検査す
ることができ、検査時間が極めて短くなる。また
許容限度が数値化されることにより検査にばらつ
きがなく、さらに検査面全体にピントが合い、ま
た、遠近による形の歪がなく、誤差が少なくなり
精度が向上する。
At this time, it is not necessary to inspect each wire individually; instead, it is possible to inspect several wires at a time and scan the entire wire in blocks and divide it into several frames, or scan the entire wire in one frame and digitally process it. The inspection time can be extremely shortened. Furthermore, by quantifying the allowable limit, there is no variation in inspection, the entire inspection surface is in focus, there is no shape distortion due to distance, errors are reduced, and accuracy is improved.

撮像ユニツトは2組のみでもよい。2組、或い
は3組の撮像ユニツトの中心軸の方向は任意に選
ぶことができる。例えば第4〜6図において撮像
ユニツト27Aのみを垂直としてもよい。
There may be only two sets of imaging units. The directions of the central axes of the two or three sets of imaging units can be arbitrarily selected. For example, in FIGS. 4 to 6, only the imaging unit 27A may be vertical.

第4〜6図の撮像ユニツトのほかに、さらに別
の認識用その他のユニツトを中央に、低倍率検査
点7の真上に垂直に設けてもよい。
In addition to the imaging unit shown in FIGS. 4 to 6, another recognition unit or other unit may be provided vertically in the center directly above the low magnification inspection point 7.

レンズ系23A,23B,23Cのレンズ面は
必ずしも検査面と平行でなく、例えば、中心軸2
8A,28B,28Cに直角でもよい。このとき
視野全体に正確にはピントが合わせないが、焦点
深度が深ければ、これを補つて視野全体に実用的
にほぼピントを合わせることができる。
The lens surfaces of the lens systems 23A, 23B, and 23C are not necessarily parallel to the inspection surface, for example, the central axis 2
It may be perpendicular to 8A, 28B, and 28C. At this time, the entire field of view cannot be brought into focus accurately, but if the depth of focus is deep, this can be compensated for and practically the entire field of view can be brought into focus.

高倍率撮像装置16においては、第3図の如き
狭い視野において拡大された画像により、パター
ン認識を行い、デジタル処理によつて得られたボ
ール32(又はステツチ33)がパツド22(又
はリード31)に対する位置ズレ、ボール32
(又はステツチ33)の形状、寸法を、予め記憶
された標準データと比較して、不良の有無を検査
することができる。
In the high-magnification imaging device 16, pattern recognition is performed using an image magnified in a narrow field of view as shown in FIG. Misalignment, ball 32
The shape and dimensions of the stitch 33 (or the stitch 33) can be compared with pre-stored standard data to check for defects.

第9図は信号系路の説明図であり、35はカメ
ラコントロールユニツト、36は画像処理装置と
してのパターン認識ユニツト、37はインターフ
エース制御系、38はCPU、39はメモリ回路、
40はステージドライバ、41は他のドライバで
ある。
FIG. 9 is an explanatory diagram of the signal path, where 35 is a camera control unit, 36 is a pattern recognition unit as an image processing device, 37 is an interface control system, 38 is a CPU, 39 is a memory circuit,
40 is a stage driver, and 41 is another driver.

メモリ回路39には、検査各項目に関する標準
データ、或いは、二つの撮像ユニツトからの平面
位置データを合成して立体位置を演算して求める
演算プログラムなどが記憶されている。
The memory circuit 39 stores standard data regarding each inspection item, a calculation program for calculating a three-dimensional position by combining two-dimensional position data from two imaging units, and the like.

カメラコントロールユニツト35においては、
視野全体を、或いは視野を複数個のブロツクに分
けて、1回又は数回のフレームの走査を行いデジ
タル撮像信号を出力し、パターン認識ユニツト3
6においては、その入力信号とメモリ回路39か
らの標準データに基づく標準データ信号とを比較
して、入力データ信号の正常、非正常を判定し、
不良の場合はマーキング装置18に信号を送り、
該当するICの付近にマークを付す。
In the camera control unit 35,
The entire field of view or the field of view is divided into a plurality of blocks, one or several frames are scanned, a digital imaging signal is output, and the pattern recognition unit 3
6, the input signal is compared with a standard data signal based on the standard data from the memory circuit 39 to determine whether the input data signal is normal or abnormal;
If it is defective, it sends a signal to the marking device 18,
Add a mark near the applicable IC.

モニタ17には検査情報として撮像画面のほか
に、検査数値、不良個所、不良分析などをリアル
タイムで表示できるようになつているので、状況
により直ちにボンデイングマシンにフイードバツ
クしてボンデイング条件の設定などのアクシヨン
を速やかに行うことができる。
In addition to the imaging screen as inspection information, the monitor 17 is designed to display inspection values, defective locations, defect analysis, etc. in real time, so depending on the situation, feedback can be immediately sent to the bonding machine for actions such as setting bonding conditions. can be done promptly.

また、検査データを集計することにより前工程
での不良発生個所への敏速な対応が可能となり、
生産の歩留向上がはかれる。
In addition, by aggregating inspection data, it is possible to quickly respond to defects occurring in the previous process.
Production yield can be improved.

第10図,第11図は低倍率検査点7における
照明具の例を示す。低倍率検査点7におけるIC
チツプ20を取囲むように、かつ検査面に接近し
て低い位置に、環状の光源を持つ照明灯46が設
けられる。周囲から、かつ低い位置から照明され
ることにより、ボンデイングワイヤ30の立体的
な形状を誤りなく、明瞭に撮像することができ
る。
10 and 11 show examples of lighting equipment at the low magnification inspection point 7. IC at low magnification inspection point 7
An illumination lamp 46 having an annular light source is provided so as to surround the chip 20 and at a low position close to the inspection surface. By being illuminated from the periphery and from a low position, the three-dimensional shape of the bonding wire 30 can be clearly imaged without error.

〔発明の効果〕〔Effect of the invention〕

本発明は、受光面を半導体装置の検査面と平行
に配備した複数の撮像ユニツトを、その中心軸が
検査面にて交差するように配備したので、ボンデ
イング形状、寸法を立体的に把握するのに低倍率
レンズを用いることが可能となり、視野が広く、
しかも斜めから撮像しているにも拘らず遠近によ
る形の歪がなく、深い焦点深度を有するレンズを
用いることができるので視野全体にピントが合い
易く、撮像装置を上下方向、水平方向に移動する
要なく、移動に要する時間を省くことができ、ま
た、撮像データをデジタル処理して標準データと
比較してボンデイング状態の良否の判定を行うよ
うにしたので、広い視野の全領域の多くの部位の
多くの種類の信号を短時間に標準データと比較し
て判定することができ、検査時間の短縮がはから
れて検査効率が向上し、また入力データの正常、
非正常の判断が定量化されて検査員の個人差によ
るばらつきがなくなり、さらに、ピントぼけや遠
近の歪による誤差がなくなり、検査精度が向上す
る半導体装置の撮像検査装置を提供することがで
き、実用上極めて大なる効果を奏する。
In the present invention, a plurality of imaging units whose light-receiving surfaces are arranged parallel to the inspection surface of the semiconductor device are arranged so that their central axes intersect with the inspection surface, making it possible to grasp the bonding shape and dimensions three-dimensionally. It is now possible to use a low magnification lens, which provides a wide field of view.
Moreover, even though the image is taken from an angle, there is no distortion due to distance, and a lens with a deep depth of focus can be used, making it easy to focus on the entire field of view, and the imaging device can be moved vertically and horizontally. In addition, since the imaging data is digitally processed and compared with standard data to determine whether the bonding condition is good or bad, many parts of the entire area with a wide field of view can be inspected. Many types of signals can be compared and judged with standard data in a short time, reducing inspection time and improving inspection efficiency.
It is possible to provide an imaging inspection apparatus for semiconductor devices in which abnormality determination is quantified, variations due to individual differences among inspectors are eliminated, and errors due to defocus and perspective distortion are eliminated, and inspection accuracy is improved. It has a great practical effect.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の実施例に関するものであり、第
1図は全体の斜視図、第2図は低倍率撮像装置の
視野、第3図は高倍率撮像装置の視野、第4図は
低倍率撮像装置の、低倍率検査点7を通り半導体
装置6の移送方向に平行な垂直面による断面正面
図、第5図はその−線断面側面図、第6図は
その平面的配置図、第7図a,b,cは一つのボ
ンデイング部を異なる撮像ユニツトで撮像した場
合の像の見え方の説明図、第8図a,bは他の一
つのボンデイングを異なる撮像ユニツトで撮像し
た場合の像の見え方の説明図、第9図は信号系路
の説明図、第10図は照明具の実施例の平面図、
第11図はその−線断面正面図である。 1……ベースフレーム、2……供給用マガジ
ン、3……供給用エレベータ、4……検査ステー
ジ、5……押し出し装置、6……半導体装置、7
……低倍率検査点、8……高倍率検査点、9……
マーキング点、10……移送装置、11……収納
用マガジン、12……収納用エレベータ、13…
…XYテーブル、14……低倍率撮像装置、15
……XYテーブル、16……高倍率撮像装置、1
7……モニター、18……マーキング装置、19
……視野、20……ICチツプ、21……視野、
22……パツド、23A,23B,23C……レ
ンズ系、24A,24B,24C……受光面、2
5A,25B,25C……光・電気変換器、26
A,26B,26C……鋭筒、27A,27B,
27C……撮像ユニツト、28A,28B,28
C……中心軸、29,29′……ボンデイング部、
30……ワイヤ、31……リード、32……ボー
ル、33……ステツチ、34……透光体、35…
…カメラコントロールユニツト、36……パター
ン認識ユニツト、37……インターフエース制御
系、38……CPU、39……メモリ回路、40
……ステージドライバ、41……他のドライバ、
42,43,44……平面、45A,45B,4
5C……絞り、46……照明灯。
The drawings relate to embodiments of the present invention, and FIG. 1 is an overall perspective view, FIG. 2 is a field of view of a low-magnification imaging device, FIG. 3 is a field of view of a high-magnification imaging device, and FIG. 4 is a low-magnification imaging device. 5 is a cross-sectional front view of the device taken along a vertical plane passing through the low magnification inspection point 7 and parallel to the transport direction of the semiconductor device 6; FIG. 5 is a side view of the cross-section along the - line; FIG. Figures a, b, and c are explanatory diagrams of how images appear when one bonding part is imaged with different imaging units, and Figures 8a and b are illustrations of images when another bonding part is imaged with different imaging units. An explanatory diagram of how it looks, Fig. 9 is an explanatory diagram of the signal path, Fig. 10 is a plan view of an embodiment of the lighting device,
FIG. 11 is a sectional front view taken along the line --. DESCRIPTION OF SYMBOLS 1... Base frame, 2... Supply magazine, 3... Supply elevator, 4... Inspection stage, 5... Extrusion device, 6... Semiconductor device, 7
...Low magnification inspection point, 8...High magnification inspection point, 9...
Marking points, 10...transfer device, 11...storage magazine, 12...storage elevator, 13...
...XY table, 14...Low magnification imaging device, 15
...XY table, 16...High magnification imaging device, 1
7...Monitor, 18...Marking device, 19
...Field of view, 20...IC chip, 21...Field of view,
22... Pad, 23A, 23B, 23C... Lens system, 24A, 24B, 24C... Light receiving surface, 2
5A, 25B, 25C...Optical/electrical converter, 26
A, 26B, 26C...sharp tube, 27A, 27B,
27C...imaging unit, 28A, 28B, 28
C... Central axis, 29, 29'... Bonding part,
30... Wire, 31... Lead, 32... Ball, 33... Stitch, 34... Transparent body, 35...
...Camera control unit, 36...Pattern recognition unit, 37...Interface control system, 38...CPU, 39...Memory circuit, 40
...Stage driver, 41...Other drivers,
42, 43, 44...plane, 45A, 45B, 4
5C...Aperture, 46...Illuminating light.

Claims (1)

【特許請求の範囲】 1 ワイヤボンドを行つた後の半導体装置の外観
検査を撮像により行う半導体装置の撮像検査装置
において、 単数または複数のレンズより成るレンズ系と、
該レンズ系による像を結像せしめる受光面とを有
する複数組の撮像ユニツトと、 該撮像ユニツトの前記受光面における画像信号
を電気信号に変える光・電気信号変換器と、 該電気信号をデジタル化し、各撮像ユニツトの
うち少なくとも二つの撮像ユニツトからのデジタ
ル信号を合成演算して対象物の立体位置のデータ
を得る演算回路と、 検査項目に関するデジタル化された標準データ
を記憶するメモリ回路と、 前記光・電気信号から変換した電気信号に基づ
きデジタル化された入力データ信号と前記標準デ
ータに基づく標準データ信号とを比較して該入力
データの正常、非正常を判定する画像処理装置と
を備え、 前記撮像ユニツトは、それぞれの受光面が検査
されるべき半導体装置の検査面に対し平行に配備
され、かつ、それぞれの撮像ユニツトの受光面中
心とレンズ系中心とを結ぶ中心軸が、前記検査面
にて交差するよう配備されている ことを特徴とする半導体装置の撮像検査装置。 2 前記レンズ系の、レンズ主軸に対して垂直な
レンズ面が、前記検査面に対して平行に配備され
ている特許請求の範囲第1項記載の装置。
[Scope of Claims] 1. An imaging inspection apparatus for a semiconductor device that performs an external appearance inspection of a semiconductor device after wire bonding by imaging, comprising: a lens system comprising one or more lenses;
a plurality of imaging units each having a light receiving surface for forming an image by the lens system; an optical/electrical signal converter for converting an image signal on the light receiving surface of the imaging unit into an electrical signal; and a light/electrical signal converter for converting the electrical signal into an electrical signal. , an arithmetic circuit that synthesizes digital signals from at least two of the imaging units to obtain data on the three-dimensional position of the object; and a memory circuit that stores digitized standard data regarding inspection items; an image processing device that compares an input data signal digitized based on an electrical signal converted from an optical/electrical signal with a standard data signal based on the standard data to determine whether the input data is normal or abnormal; The imaging units are arranged so that their respective light receiving surfaces are parallel to the inspection surface of the semiconductor device to be inspected, and the central axis connecting the center of the light receiving surface of each imaging unit and the center of the lens system is parallel to the inspection surface. 1. An imaging inspection apparatus for semiconductor devices, characterized in that the apparatus is arranged so as to intersect with each other. 2. The apparatus according to claim 1, wherein a lens surface of the lens system perpendicular to the lens principal axis is arranged parallel to the inspection surface.
JP61286882A 1986-12-03 1986-12-03 Semiconductor device image pickup tester Granted JPS63144531A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61286882A JPS63144531A (en) 1986-12-03 1986-12-03 Semiconductor device image pickup tester
US07/128,329 US4872052A (en) 1986-12-03 1987-12-03 Semiconductor device inspection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61286882A JPS63144531A (en) 1986-12-03 1986-12-03 Semiconductor device image pickup tester

Publications (2)

Publication Number Publication Date
JPS63144531A JPS63144531A (en) 1988-06-16
JPH0569304B2 true JPH0569304B2 (en) 1993-09-30

Family

ID=17710219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61286882A Granted JPS63144531A (en) 1986-12-03 1986-12-03 Semiconductor device image pickup tester

Country Status (1)

Country Link
JP (1) JPS63144531A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4547330B2 (en) * 2005-12-28 2010-09-22 株式会社新川 Wire bonding apparatus, bonding control program, and bonding method
JP7285988B2 (en) * 2018-04-03 2023-06-02 キヤノンマシナリー株式会社 Inspection device and inspection method
JP7068897B2 (en) * 2018-04-03 2022-05-17 キヤノンマシナリー株式会社 Inspection equipment and inspection method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59139639A (en) * 1983-01-31 1984-08-10 Hitachi Ltd Manufacturing device for semiconductor
JPS59144140A (en) * 1983-02-07 1984-08-18 Hitachi Ltd Inspecting method of wire bonding portion

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59139639A (en) * 1983-01-31 1984-08-10 Hitachi Ltd Manufacturing device for semiconductor
JPS59144140A (en) * 1983-02-07 1984-08-18 Hitachi Ltd Inspecting method of wire bonding portion

Also Published As

Publication number Publication date
JPS63144531A (en) 1988-06-16

Similar Documents

Publication Publication Date Title
US4872052A (en) Semiconductor device inspection system
JP3522280B2 (en) Method and apparatus for a ball bond inspection system
US8503758B2 (en) Image measurement device, method for image measurement, and computer readable medium storing a program for image measurement
WO2010090605A1 (en) Methods for examining a bonding structure of a substrate and bonding structure inspection devices
JPS62173731A (en) Inspection device for surface of article to be inspected
JPH0376137A (en) Wire bonding testing device
CN110487189B (en) Flatness detection method, flatness detection device, and storage medium
JP2851151B2 (en) Wire bonding inspection equipment
JP6461555B2 (en) Bump inspection device
JP2011222636A (en) Inspection apparatus, inspection method, and defect coordinate correction method
KR20000016975A (en) Grid Array Inspection System and Method
CN112834528A (en) 3D defect detection system and method
JPH0569304B2 (en)
CN109219730B (en) System and method for pin angle inspection using multi-view stereo vision
JP7450272B2 (en) Measuring the loop height of overlapping bond wires
US20120128229A1 (en) Imaging operations for a wire bonding system
JPH0732188B2 (en) Semiconductor device inspection equipment
JP3215871B2 (en) Wire bonding visual inspection device
JP2008209420A (en) Non-contact three-dimensional measurement method
JP2005274309A (en) Inspection method and inspection device for three-dimensional object
JPH05175312A (en) Wire bonding inspecting apparatus
JP4048096B2 (en) Method for measuring the height of an object to be detected
JPH01140048A (en) Inspection of shape of object
JPS6336543A (en) Method and apparatus for automatic inspection of semiconductor device
JPS62274205A (en) Method and device for inspecting lead flatness