JPS584937A - Inspecting system for semiconductor chip - Google Patents
Inspecting system for semiconductor chipInfo
- Publication number
- JPS584937A JPS584937A JP56102908A JP10290881A JPS584937A JP S584937 A JPS584937 A JP S584937A JP 56102908 A JP56102908 A JP 56102908A JP 10290881 A JP10290881 A JP 10290881A JP S584937 A JPS584937 A JP S584937A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wire
- scanning line
- circuit
- setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体チップの検査装置に係)峙に半導体チッ
プにワイヤボンデングされえワイヤ断線やワイヤ圧着位
置づれを検出するための牛導体チップの検査装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor chip testing device, and more particularly to a testing device for a conductor chip that is wire-bonded to a semiconductor chip and is used to detect wire breakage or misalignment of wire crimping.
従来、半導体チップにワイヤボンデングを行ったワイヤ
の結線状態の検査は人手による目視検査によっていたた
めに多くの人手と時間を必要とし、完全にすべての断線
個所を見出すこともすこぶる困難である欠点を有して−
え・本発明は上述の如き従来の欠点を除去しえ半導体チ
ップの検査装置を提供するものでその目的とするところ
は半導体チップにワイヤボンデングを行つ九9イヤの#
線状態を読みとるためにワイヤ圧着部の周囲を走査する
特定の走査線を設定し、ワイヤ断線の中でも発生頻度の
高iネツタ部分のワイヤ断線やワイヤ圧着位置づれを検
出し得る半導体チップの検査装置を得ようとするもので
ある。Conventionally, inspection of the connection status of wires bonded to semiconductor chips has been done manually and visually, which requires a lot of manpower and time, and it is extremely difficult to find all the broken wires. with -
E. The present invention provides a semiconductor chip inspection device that eliminates the above-mentioned conventional drawbacks, and its purpose is to provide a 99-year inspection device that performs wire bonding on semiconductor chips.
A semiconductor chip inspection device that can detect wire breaks in the i-net area where wire breaks occur most frequently and misalignment of wire crimps by setting a specific scanning line to scan around the wire crimping part in order to read the wire condition. It is an attempt to obtain.
以下1本発明の1実施例を#E1図乃至第911につ−
て詳記する・
第1IIは本発明の半導体チップの検査装置の系統間を
示すものであ)1は載置台で鋏装置台上に半導体チップ
2vt有し、該半導体チップの周辺には第2図に示す如
く100μ口11度の複数のパッド3を有し、該パッド
と同じく400〜500μ口程度の2次パッド4聞1c
30jφ程度の全線のワイヤ5を1熱融着5鳳5bする
。One embodiment of the present invention will be described below with reference to Figures #E1 to #911.
1II shows the system of the semiconductor chip inspection apparatus of the present invention. 1 is a mounting table with 2vt semiconductor chips on the scissor device table, and around the semiconductor chip there are 2vt. As shown in the figure, it has a plurality of pads 3 with 100μ openings and 11 degrees, and like the above pads, secondary pads with about 400 to 500μ openings 4 times 1c.
The entire wire 5 of about 30jφ is heat-sealed 5b.
圧着部5麿はsomIIm度の大きさで通常は圧着部分
S−のネック部分の断線が電も多−〇本発明ではこの部
分の新替状態を検出する九めに撮像装置7のレンズ系6
を通して餉JIIS鳳闘略9と制御回・路10に撮像装
置7の駆動回路st通じて映像出力が与えられる。前処
理回路9では撮倫俟置フで撮會された半導体チップ2の
普ww&物えるパッド3近傍を2値化処理し2値化映俸
メモリIIK記憶する。The crimp part 5 has a size of somIIm degree, and normally, disconnection at the neck part of the crimp part S- causes a lot of electricity.In the present invention, the lens system 6 of the imaging device 7 detects the replacement state of this part.
A video output is given to the control circuit 9 and the control circuit 10 through the drive circuit st of the imaging device 7. The preprocessing circuit 9 binarizes the vicinity of the normal and visible pads 3 of the semiconductor chip 2 photographed in the camera position, and stores it in the binarized video memory IIK.
この2値化映像メ4”j#i例えば、第R@の如く構成
され、半導体チップ!のパット3近傍がメモリされて−
る。尚、同図で12は後述する走査線部分のメモリー状
態を示している。This binarized video image 4"j#i is configured, for example, as shown in R@, and the vicinity of pad 3 of the semiconductor chip! is stored in memory.
Ru. In the figure, reference numeral 12 indicates the memory state of the scanning line portion, which will be described later.
2値化映像メモ911よ〉の出力は走査線設定回路13
に、加えられる・諌走査曽設定回路13は制御回路10
とパッド中心位置又は圧着部中心位置等のアドレス14
よりの信号が与えられて半導体パッド3の圧着1115
m近傍管走査する走査!1121設定する。1112図
で12はこの走査−を示す。走査線を設定する基準点と
してはパッド3勢の中心点を求めて、該中心点を基準に
走査する。この場合、パッド3の中心点を求める工11
はワイヤボンデング前にパッドの位置決めを行って−る
のでパッドの中心位置にパッド中心位置アドレスに記憶
されてiる・走査線12の設定方法としてはパッド中心
位置アドレス14よ−のアドレス(a、b)から所定距
離2離れた喬直方向の走査@12m、12bと水平方向
の走査線126.12dを設定する。走査線は始点12
会より走査を開始し終点121で終了し、走査線12a
、12bは(a −” sb)、(a+・、−)点を通
勤走査線12c。The output of the binarized video memo 911 is sent to the scanning line setting circuit 13.
, the scanning setting circuit 13 added to the control circuit 10
and the address 14 of the pad center position or crimp part center position, etc.
A signal is given to press the semiconductor pad 3 1115.
Scanning to scan m nearby tubes! 1121 setting. In Figure 1112, 12 indicates this scanning. The center point of the three pads is determined as a reference point for setting a scanning line, and scanning is performed using this center point as a reference. In this case, step 11 for finding the center point of pad 3
Since the pad position is determined before wire bonding, the pad center position address is stored at the center position of the pad.The method for setting the scanning line 12 is to set the pad center position address 14 to the address (a). , b), and a horizontal scanning line 126.12d is set at a predetermined distance 2 from the horizontal scanning line 12m, 12b. The scan line starts at 12
The scanning starts from the end point 121 and ends at the scanning line 12a.
, 12b is the (a-''sb), (a+.,-) point of the commuting scanning line 12c.
12s1は(a 、b + ’ ) −(a a b
+ s )点を通るように設定される・走査線設定回路
13よ勢の出力は1次段のワイヤ断線検出回路15によ
って2値化映倫メモリーにより記憶された2値化メモリ
第3図を上記走査線設定回路!3で設定した走査線12
で走査する。この走査線12で走査し九領域の内容を読
み出すと第3図のメモリ図の如くワイヤのある部分Fi
2値化信号″1.。12s1 is (a, b + ') - (a a b
The output from the scanning line setting circuit 13 is set to pass through the +s) point, and the output from the scanning line setting circuit 13 is converted into a binary memory stored in the binary memory by the wire breakage detection circuit 15 in the first stage. Scan line setting circuit! Scan line 12 set in step 3
Scan with . When scanning with this scanning line 12 and reading out the contents of nine areas, the part Fi where the wire is located as shown in the memory diagram of FIG.
Binarized signal ``1.''
となり、ワイヤのなi部分#12値化信号10となる。Therefore, the i part #1 of the wire becomes the binary signal 10.
そこで第4図の走査線開始点12eからの信号を第5図
に示すワイヤ断線検知回路15のデータ入力端子1ss
ecl[次加える。走査終点は12f点になる。データ
ー入力端子15mに加えられたデータはnビットのシフ
トレジスタ15bを通してデータ出力端子15cKJi
k)出されると共に例えば8ビツトのプライオリティ・
エンコー〆ISdからは基準ビツシかも連続して現われ
る2値化信号“14の数を比較回路156に与える。鋏
比較−路15eKはワイヤ(全65)の太さに相轟する
ビット数を基準値とし良2値化信号が基1*回路ISf
よ勤与見られるために基準ビットから連続して現われる
2値化信号と基準値が比較されてワイヤ5の有無が検出
される。上記ワイヤ断曽検出回路15よりの出力は出力
装置16に与えて表示装置勢に表示するか、制御回路勢
を作動させるようにすればよい。Therefore, the signal from the scanning line starting point 12e in FIG. 4 is transmitted to the data input terminal 1ss of the wire breakage detection circuit 15 shown in FIG.
ecl [Add next. The scanning end point is the 12f point. The data applied to the data input terminal 15m passes through the n-bit shift register 15b to the data output terminal 15cKJi.
k) For example, an 8-bit priority
The encoder ISd gives the comparator circuit 156 the number of binary signals "14" that appear continuously in the reference bits. The scissors comparison circuit 15eK sets the number of bits that correspond to the thickness of the wire (65 in total) as the reference value. Toshiyoshi binary signal is based on 1*circuit ISf
The presence or absence of the wire 5 is detected by comparing the binary signal successively appearing from the reference bit with the reference value in order to be clearly observed. The output from the wire breakage detection circuit 15 may be supplied to the output device 16 to be displayed on a display device or to operate a control circuit.
上記実施例に於ては、パッド3の中心位置(ab)を中
心に正方形状の走査線12t−設定したが、![6図に
示すように走査線をパッド3を中心とする円形走査線と
すること、あるirj多角形状の走査線12旭選択して
もワイヤ5の断線を検出し得る。又第7図(A)(B)
K示すようにワイヤ5のネック部分が確認されるべき方
向にのみ特定の走査線12を設定すれば第7図(B)K
示す如く、変則的にパッド3に圧着部5畠が圧着される
場合KFi走査線12に沿って2値化信号11.が読み
出されな−ため断線した半導体チップとして判断されて
変則的な圧着のなされた製品を除外することが出来る。In the above embodiment, a square scanning line 12t was set centered around the center position (ab) of the pad 3, but! [As shown in FIG. 6, if the scanning line is a circular scanning line centered on the pad 3, or if a certain irj polygonal scanning line 12 is selected, a break in the wire 5 can be detected. Also, Figure 7 (A) (B)
If a specific scanning line 12 is set only in the direction in which the neck portion of the wire 5 is to be confirmed as shown in FIG.
As shown, when the crimping portion 5 is irregularly crimped to the pad 3, the binarized signal 11 . Since this is not read out, it is determined that the semiconductor chip has a disconnection, and products that have been irregularly crimped can be excluded.
上記実施例ではパッド3の中心点(Jl、b)を基単に
走査線12を設定したが第8図に示すようにワイヤ5の
圧着状態を検出する工程でワイヤ圧着位置ずれ量を検知
するためにパッド3を中心に十字形の走査線17を設定
し、この走査l5KJよって設定され九検知領域18に
沿って走査線12を走査させてもよ−。このようにする
とワイヤ圧着位置づれとワイヤの断線を同時に効率よく
検査することが出来る。In the above embodiment, the scanning line 12 was set based on the center point (Jl, b) of the pad 3, but as shown in FIG. A cross-shaped scanning line 17 may be set centering on the pad 3, and the scanning line 12 may be scanned along the nine detection areas 18 set by this scanning l5KJ. In this way, wire crimping positional deviation and wire breakage can be efficiently inspected at the same time.
又第9図に示すように圧着位置ずれ量検知を行な−、ワ
イヤの断線を検知する走査線の設定を行なうための基準
点をパッド3の中心点(17b)の代)に圧着部5麿の
中心19を基準として走査線21を設定して4よ−。か
くすればパッド3の中心を基準として走査した走査線2
0に於ては圧着部5aが、づれ良位置にあるために圧着
部5mのボールを横切る走査線部分20aで生ずるz値
化信号lを生ずることはなく。Further, as shown in FIG. 9, the crimp portion 5 is set at the center point (17b) of the pad 3 as a reference point for detecting the amount of crimp position deviation and setting the scanning line for detecting wire breakage. Set the scanning line 21 using the center 19 of Maro as a reference and move to step 4. In this way, the scanning line 2 scanned with the center of the pad 3 as a reference
0, the crimping part 5a is in a position with good deviation, so that the z-valued signal l that occurs in the scanning line portion 20a that crosses the ball of the crimping part 5m is not generated.
ワイヤ5をよぎる走査1I21部分のみで信号を発生さ
せることが出来る。A signal can be generated only in the scan 1I21 portion that crosses the wire 5.
上記、第8図及び第9111の各実施例に於ては圧着部
の中心及び圧着位置ずれ領域を正方形状走査−で説明し
良が第6図に示すように円形又は多角形状の走査線を設
定し得る仁とは明らかである。In each of the embodiments shown in FIGS. 8 and 9111 above, the center of the crimping part and the crimping position deviation area are explained using a square scanning line, but circular or polygonal scanning lines are used as shown in FIG. 6. It is clear what kind of benevolence can be established.
ボンデング直後に生ずるワイヤの断線を目視検査によら
ず自動的に検知することが出来て信頼性の向上か検査工
程時間の短縮が可能となる特徴を有する。It has the feature that wire breakage that occurs immediately after bonding can be automatically detected without visual inspection, thereby improving reliability and shortening the inspection process time.
第1図は本発明の半導体チップ検査装置の系統図、第2
図は半導体チップのパッド部分の拡大平面図、第3図は
ワイヤ圧着部近傍の2値化メモリの説明図、114図は
本発明に用−る走査線の設定方法を示す線図、第5図は
ワイヤ断線検出回路、第6図は本発明の走査線設定方法
を示す他の説明用平面図、第7図(&)(B)t!本発
明の走査線設定方法を示す更に他の実施例で第7@(ム
)は正常な場合、第7図(B)は変則的な場合を示すチ
ップ部分の平面図第8図はワイヤの圧着ずれ検知領域で
の走査線設定方法を示す本発明の詳細な説明図、119
図はワイヤ圧着部を中心に走査線を施す場合の本発明の
詳細な説明−である。FIG. 1 is a system diagram of the semiconductor chip inspection apparatus of the present invention, and FIG.
114 is an enlarged plan view of the pad portion of the semiconductor chip, FIG. 3 is an explanatory diagram of the binarized memory near the wire crimping part, FIG. The figure shows a wire breakage detection circuit, FIG. 6 is another explanatory plan view showing the scanning line setting method of the present invention, and FIG. 7 (&) (B) t! In still another embodiment showing the scanning line setting method of the present invention, Fig. 7(B) is a plan view of the chip portion showing a normal case and Fig. 7(B) an irregular case. Fig. 8 is a plan view of the wire. Detailed explanatory diagram of the present invention showing a scanning line setting method in the crimping deviation detection area, 119
The figure is a detailed explanation of the present invention in the case where a scanning line is applied centering on a wire crimping part.
Claims (1)
2値化処理した出力を記憶する2値化映倫メモリとパッ
ド等の被lI−物の中心位置アドレスメ毫すと上記映像
メモリと中心位置アドレスメモリに基づ≠て上記被認識
物の周辺に41定の走査線を設定するための走査線設定
回路と、咳走査線設定回路による走査線に基づ−て2値
化映像メモψを走査しワイヤの断線を検出するワイヤ断
線検出回路とよりなる半導体チップの検査装置 (2)被認識物の周辺に41定の走査線tQ定する時に
被認識物の中心点を中心に多角形状に走査mを設定して
なる特許請求の範囲第1項lea!の半導体チップの検
査装置 (3)被認識物の周辺に#定の走査−を設定する時に被
認識物の中心点を中心に円形走査線を設定してなる特許
請求の範囲第1項記載の半導体チップの検査装置 (4)被認識物がバットであ)骸パットの中心を中心点
に走査111IYt設定してなる特許請求の範S第1項
記載の半導体チップの検査装置 (5)被認識物がワイヤ圧着部であり該ワイヤ圧着部の
中心を中心点として走査線を設定して麿る特許請求の範
囲第1項記載の半導体チップの検査装置 (@)被認識物の周辺に走査Isを設定する時にワイヤ
の引出方向と確認されるべき方向にのみ特定の走査線を
設定してなる特許請求の範囲第1項記載の半導体チップ
の検査装置 (7)ワイヤの圧着部の位置づれ検知時の検査領域に沿
って走査1aの設定をしてなる特許請求の範!21第1
項記載の半導体チップの検査装置[Claims] (1) A binarization memory that captures an image of a semiconductor chip, binarizes it, and stores the binarized output, and the center position of objects such as pads. When the address is entered, a scanning line setting circuit for setting 41 constant scanning lines around the object to be recognized based on the image memory and the center position address memory and a cough scanning line setting circuit are used to set the scanning lines. (2) Semiconductor chip inspection device comprising a wire breakage detection circuit that scans the binary video memo ψ and detects wire breaks (2) When setting 41 constant scanning lines tQ around the object Claim 1 lea! is formed by setting the scan m in a polygonal shape centered on the center point of the recognized object! Semiconductor chip inspection device (3) according to claim 1, wherein a circular scanning line is set around the center point of the object to be recognized when a constant scan is set around the object to be recognized. Semiconductor chip inspection device (4) Semiconductor chip inspection device (5) Semiconductor chip inspection device according to claim S (1), in which the object to be recognized is a bat) scanning is set at 111IYt with the center of the skeleton pad as the center point The semiconductor chip inspection apparatus (@) according to claim 1, wherein the object is a wire crimping part and the scanning line is set around the center of the wire crimping part as a center point. (7) Detection of positional deviation of the crimped portion of the wire The claim is made by setting the scan 1a along the inspection area at the time! 21 1st
Semiconductor chip inspection equipment described in section
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56102908A JPS584937A (en) | 1981-06-30 | 1981-06-30 | Inspecting system for semiconductor chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56102908A JPS584937A (en) | 1981-06-30 | 1981-06-30 | Inspecting system for semiconductor chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS584937A true JPS584937A (en) | 1983-01-12 |
Family
ID=14339952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56102908A Pending JPS584937A (en) | 1981-06-30 | 1981-06-30 | Inspecting system for semiconductor chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS584937A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432268B1 (en) | 2000-09-29 | 2002-08-13 | Kimberly-Clark Worldwide, Inc. | Increased hydrophobic stability of a softening compound |
KR20020088269A (en) * | 2001-05-21 | 2002-11-27 | 삼성전자 주식회사 | Wire bonding method for ball grid array package skipping reject unit |
JP2008032255A (en) * | 2006-07-26 | 2008-02-14 | Taisei Corp | Under-floor air-conditioning system |
-
1981
- 1981-06-30 JP JP56102908A patent/JPS584937A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432268B1 (en) | 2000-09-29 | 2002-08-13 | Kimberly-Clark Worldwide, Inc. | Increased hydrophobic stability of a softening compound |
KR20020088269A (en) * | 2001-05-21 | 2002-11-27 | 삼성전자 주식회사 | Wire bonding method for ball grid array package skipping reject unit |
JP2008032255A (en) * | 2006-07-26 | 2008-02-14 | Taisei Corp | Under-floor air-conditioning system |
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