JPS584937A - Inspecting system for semiconductor chip - Google Patents

Abstract

PURPOSE:To improve detecting accuracy and to shorten inspection time without resorting to visual inspection by a method wherein a scanning line, set up near the place of wire pressure attaching, senses wire bonding conditions, and monitors specifically the neck shaped sections, frequented by line disconnections, and the deviation of wire attaching locations, when wires are bonded to a semiconductor chip. CONSTITUTION:A semiconductor chip 2 is stuck on a platform 1 provided with pads 3 and 4 which in turn are connected to a terminal installed on said chip 2 with a very thin wire 5. Next, an image pickup device 7 with a lens system 6 is arranged facing the bonding position and is activated by a driving circuit 8 for the monitoring of the bonding work. That is to say, the image signal outputted by the circuit 8 is displayed on the output unit 16 after passing an image signal binarizing pre-processing circuit 9, a memory 11, a scanning line setting circuit 13, and a wire disconnection detecting circuit 15. During this period, a controlling circuit 10 connected to the driving circuit 8 monitors and regulates the circuits 8, the output unit 16, and the each unit connected thereto. This provides automatic monitoring of the bonding process.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor chip testing device, and more particularly to a testing device for a conductor chip that is wire-bonded to a semiconductor chip and is used to detect wire breakage or misalignment of wire crimping.

Conventionally, inspection of the connection status of wires bonded to semiconductor chips has been done manually and visually, which requires a lot of manpower and time, and it is extremely difficult to find all the broken wires. with -
E. The present invention provides a semiconductor chip inspection device that eliminates the above-mentioned conventional drawbacks, and its purpose is to provide a 99-year inspection device that performs wire bonding on semiconductor chips.
A semiconductor chip inspection device that can detect wire breaks in the i-net area where wire breaks occur most frequently and misalignment of wire crimps by setting a specific scanning line to scan around the wire crimping part in order to read the wire condition. It is an attempt to obtain.

One embodiment of the present invention will be described below with reference to Figures #E1 to #911.
1II shows the system of the semiconductor chip inspection apparatus of the present invention. 1 is a mounting table with 2vt semiconductor chips on the scissor device table, and around the semiconductor chip there are 2vt. As shown in the figure, it has a plurality of pads 3 with 100μ openings and 11 degrees, and like the above pads, secondary pads with about 400 to 500μ openings 4 times 1c.
The entire wire 5 of about 30jφ is heat-sealed 5b.

The crimp part 5 has a size of somIIm degree, and normally, disconnection at the neck part of the crimp part S- causes a lot of electricity.In the present invention, the lens system 6 of the imaging device 7 detects the replacement state of this part.
A video output is given to the control circuit 9 and the control circuit 10 through the drive circuit st of the imaging device 7. The preprocessing circuit 9 binarizes the vicinity of the normal and visible pads 3 of the semiconductor chip 2 photographed in the camera position, and stores it in the binarized video memory IIK.

This binarized video image 4"j#i is configured, for example, as shown in R@, and the vicinity of pad 3 of the semiconductor chip! is stored in memory.
Ru. In the figure, reference numeral 12 indicates the memory state of the scanning line portion, which will be described later.

The output of the binarized video memo 911 is sent to the scanning line setting circuit 13.
, the scanning setting circuit 13 added to the control circuit 10
and the address 14 of the pad center position or crimp part center position, etc.
A signal is given to press the semiconductor pad 3 1115.
Scanning to scan m nearby tubes! 1121 setting. In Figure 1112, 12 indicates this scanning. The center point of the three pads is determined as a reference point for setting a scanning line, and scanning is performed using this center point as a reference. In this case, step 11 for finding the center point of pad 3
Since the pad position is determined before wire bonding, the pad center position address is stored at the center position of the pad.The method for setting the scanning line 12 is to set the pad center position address 14 to the address (a). , b), and a horizontal scanning line 126.12d is set at a predetermined distance 2 from the horizontal scanning line 12m, 12b. The scan line starts at 12
The scanning starts from the end point 121 and ends at the scanning line 12a.
, 12b is the (a-''sb), (a+.,-) point of the commuting scanning line 12c.

12s1 is (a, b + ') - (a a b
The output from the scanning line setting circuit 13 is set to pass through the +s) point, and the output from the scanning line setting circuit 13 is converted into a binary memory stored in the binary memory by the wire breakage detection circuit 15 in the first stage. Scan line setting circuit! Scan line 12 set in step 3
Scan with . When scanning with this scanning line 12 and reading out the contents of nine areas, the part Fi where the wire is located as shown in the memory diagram of FIG.
Binarized signal ``1.''

Therefore, the i part #1 of the wire becomes the binary signal 10.

Therefore, the signal from the scanning line starting point 12e in FIG. 4 is transmitted to the data input terminal 1ss of the wire breakage detection circuit 15 shown in FIG.
ecl [Add next. The scanning end point is the 12f point. The data applied to the data input terminal 15m passes through the n-bit shift register 15b to the data output terminal 15cKJi.
k) For example, an 8-bit priority
The encoder ISd gives the comparator circuit 156 the number of binary signals "14" that appear continuously in the reference bits. The scissors comparison circuit 15eK sets the number of bits that correspond to the thickness of the wire (65 in total) as the reference value. Toshiyoshi binary signal is based on 1*circuit ISf
The presence or absence of the wire 5 is detected by comparing the binary signal successively appearing from the reference bit with the reference value in order to be clearly observed. The output from the wire breakage detection circuit 15 may be supplied to the output device 16 to be displayed on a display device or to operate a control circuit.

In the above embodiment, a square scanning line 12t was set centered around the center position (ab) of the pad 3, but! [As shown in FIG. 6, if the scanning line is a circular scanning line centered on the pad 3, or if a certain irj polygonal scanning line 12 is selected, a break in the wire 5 can be detected. Also, Figure 7 (A) (B)
If a specific scanning line 12 is set only in the direction in which the neck portion of the wire 5 is to be confirmed as shown in FIG.
As shown, when the crimping portion 5 is irregularly crimped to the pad 3, the binarized signal 11 . Since this is not read out, it is determined that the semiconductor chip has a disconnection, and products that have been irregularly crimped can be excluded.

In the above embodiment, the scanning line 12 was set based on the center point (Jl, b) of the pad 3, but as shown in FIG. A cross-shaped scanning line 17 may be set centering on the pad 3, and the scanning line 12 may be scanned along the nine detection areas 18 set by this scanning l5KJ. In this way, wire crimping positional deviation and wire breakage can be efficiently inspected at the same time.

Further, as shown in FIG. 9, the crimp portion 5 is set at the center point (17b) of the pad 3 as a reference point for detecting the amount of crimp position deviation and setting the scanning line for detecting wire breakage. Set the scanning line 21 using the center 19 of Maro as a reference and move to step 4. In this way, the scanning line 2 scanned with the center of the pad 3 as a reference
0, the crimping part 5a is in a position with good deviation, so that the z-valued signal l that occurs in the scanning line portion 20a that crosses the ball of the crimping part 5m is not generated.

A signal can be generated only in the scan 1I21 portion that crosses the wire 5.

In each of the embodiments shown in FIGS. 8 and 9111 above, the center of the crimping part and the crimping position deviation area are explained using a square scanning line, but circular or polygonal scanning lines are used as shown in FIG. 6. It is clear what kind of benevolence can be established.

It has the feature that wire breakage that occurs immediately after bonding can be automatically detected without visual inspection, thereby improving reliability and shortening the inspection process time.

[Brief explanation of drawings]

FIG. 1 is a system diagram of the semiconductor chip inspection apparatus of the present invention, and FIG.
114 is an enlarged plan view of the pad portion of the semiconductor chip, FIG. 3 is an explanatory diagram of the binarized memory near the wire crimping part, FIG. The figure shows a wire breakage detection circuit, FIG. 6 is another explanatory plan view showing the scanning line setting method of the present invention, and FIG. 7 (&) (B) t! In still another embodiment showing the scanning line setting method of the present invention, Fig. 7(B) is a plan view of the chip portion showing a normal case and Fig. 7(B) an irregular case. Fig. 8 is a plan view of the wire. Detailed explanatory diagram of the present invention showing a scanning line setting method in the crimping deviation detection area, 119
The figure is a detailed explanation of the present invention in the case where a scanning line is applied centering on a wire crimping part.

Claims (1)

[Claims] (1) A binarization memory that captures an image of a semiconductor chip, binarizes it, and stores the binarized output, and the center position of objects such as pads. When the address is entered, a scanning line setting circuit for setting 41 constant scanning lines around the object to be recognized based on the image memory and the center position address memory and a cough scanning line setting circuit are used to set the scanning lines. (2) Semiconductor chip inspection device comprising a wire breakage detection circuit that scans the binary video memo ψ and detects wire breaks (2) When setting 41 constant scanning lines tQ around the object Claim 1 lea! is formed by setting the scan m in a polygonal shape centered on the center point of the recognized object! Semiconductor chip inspection device (3) according to claim 1, wherein a circular scanning line is set around the center point of the object to be recognized when a constant scan is set around the object to be recognized. Semiconductor chip inspection device (4) Semiconductor chip inspection device (5) Semiconductor chip inspection device according to claim S (1), in which the object to be recognized is a bat) scanning is set at 111IYt with the center of the skeleton pad as the center point The semiconductor chip inspection apparatus (@) according to claim 1, wherein the object is a wire crimping part and the scanning line is set around the center of the wire crimping part as a center point. (7) Detection of positional deviation of the crimped portion of the wire The claim is made by setting the scan 1a along the inspection area at the time! 21 1st
Semiconductor chip inspection equipment described in section