JPS584938A - Wire bonding system - Google Patents

Wire bonding system

Info

Publication number
JPS584938A
JPS584938A JP56102912A JP10291281A JPS584938A JP S584938 A JPS584938 A JP S584938A JP 56102912 A JP56102912 A JP 56102912A JP 10291281 A JP10291281 A JP 10291281A JP S584938 A JPS584938 A JP S584938A
Authority
JP
Japan
Prior art keywords
pad
wire
scanning line
scanning
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56102912A
Other languages
Japanese (ja)
Inventor
Masato Miyamura
宮村 正人
Masahito Nakajima
雅人 中島
Tetsuo Hizuka
哲男 肥塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56102912A priority Critical patent/JPS584938A/en
Publication of JPS584938A publication Critical patent/JPS584938A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]

Abstract

PURPOSE:To detect deviation from right fixing positions and to compensate therefor, when a wire bonding is performed wherein a wire connection is established by means of a pressure fixing ball between the pad of a semiconductor chip stuck on a mounting platform and a pad belonging in the mounting platform, by a method wherein an image pickup device located immediately above them monitors the connecting work and the output therefrom is displayed after binarization. CONSTITUTION:A semiconductor pellet 1 with a pad 2 is stuck on a platform 10 and is connected to a pad 5 installed on the platform 10 with a wire 4 by means of a pressure fixing ball. Under this construction, an image pickup unit 12 with a lens system 11 is positioned opposing the pressure fixing ball. The unit 12 is driven by a driving circuit 13 and yields an output that is binarized in a pre- processing unit 14 and then is stored in an image memory 15. Next, signals read out of the memory 15 are supplied to a scanning line setting circuits 17A and 17B, X-Y scanning circuits 20A and 20B, etc. The detecting circuit 21 detects if the pressure fixing ball is located at the central position and, if not, an output unit 23 is activated and adjusts the ball position.

Description

【発明の詳細な説明】 本発Wi4は、ワイヤlンデンダ装置に係ヤ、特に半導
体チップのパッドに熱融着書せゐワイヤの圧着位置ずれ
を検出してワイヤボンディング時の圧着位置を補正する
ようにし麺自動ワイヤボンデング装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention Wi4 is connected to a wire bending device, in particular, detects the displacement of the crimping position of a wire thermally bonded to a pad of a semiconductor chip and corrects the crimping position during wire bonding. This invention relates to an automatic wire bonding device for noodles.

半導体チップのパッド部分に圧着プールで金線を融着さ
せる場合に1lllliに示すように半導体チップlの
周:MJに配置された複数のパッド2の中心位置a、b
を基準点として検査領域を正方形6でWIすれた領域内
と限定し、ζO正方形で11重れた外周に沿りて、*査
線$を設定すると金線よIlなるワイヤ4t−走査線が
よ「る点9を検出することが出来る・更に圧着ボール3
と2次パッド5t−ptぐワイヤ40圧着位置ずれ量を
検知するえめに中手IIO走査總7.7 Kよって圧着
l−ル巾Wを針欄するようにしたものが知られている。
When gold wire is fused to the pad portion of a semiconductor chip using a pressure bonding pool, the center positions a and b of the plurality of pads 2 arranged at the circumference of the semiconductor chip l: MJ as shown in 1lllli.
With the reference point as the reference point, the inspection area is limited to the area crossed by WI in square 6, and along the outer periphery overlapped by 11 in ζO square, *scanning line $ is set, and the wire 4t-scanning line, which is the gold wire Il, is set. It is possible to detect the point 9 where the ball is pressed.
In order to detect the amount of displacement of the crimping position of the wire 40 between the secondary pad 5t and the secondary pad 5t-pt, a device is known in which the width W of the crimping lug is determined by scanning the central hand IIO at a distance of 7.7 K.

このよう1に@来の圧着位置ずれ検知手段はlンデンダ
Aット部分の映像を114堆るための撮像装置よりの映
像信号を2値化処理回路に加えて2値化し、半導体チッ
プ2の被認識物たるパッド3近傍を2値化映倫メモリに
記憶する。
In this way, the crimping position deviation detection means of 1 adds the video signal from the imaging device to the binarization processing circuit to capture the video of the 114 part of the semiconductor chip 2, and binarizes the video signal of the semiconductor chip 2. The vicinity of pad 3, which is the object to be recognized, is stored in the binarized memory.

2値化映像メモリの出力は、走査線設定回路やパッド中
心位置アドレスに基づiて、パッド上の圧着部、即ち圧
着が一ル巾Wを検出する。
The output of the binarized video memory detects the crimp portion on the pad, that is, the width W of the crimp, based on the scanning line setting circuit and the pad center position address i.

従来の上述の如き構成による圧着部30ポール巾Wを走
査線7に沿って走査すると圧1ボール中をWlとmat
、、誤った針側結果を出力する欠点を生ずる。
When the pole width W of the crimping part 30 with the conventional configuration as described above is scanned along the scanning line 7, Wl and mat are found in the crimping part 1 ball.
, , giving rise to the drawback of outputting erroneous needle side results.

本発明は上述の如き欠点を除いた圧着巾検出装置を提供
すると共に正しi圧着中を検出して圧着部のパッドに対
するずれを補正し九全自動ワイヤボンデング装置を提供
せんとするものである。
The present invention provides a crimping width detection device that eliminates the above-mentioned drawbacks, and also provides a fully automatic wire bonding device that detects when crimping is in progress and corrects the misalignment of the crimping part with respect to the pad. be.

以下1本発明の詳細を第31@l乃至第9図につ−で説
明する。
The details of the present invention will be explained below with reference to FIGS. 31@1 to 9.

嬉5ellは1本発明の全自動ワイヤボンデング装置の
系統図を示すものであり、載量台1G上に半導体チップ
等の被認識物lが載置され、半導体チップ1の周辺Kr
jlOOμ口S度の複数パッド2を有し、 400〜5
00710mmの2次パッド5間に30#ψ@度の金−
のワイヤ4を熱融着する。このため圧着ボール3を介し
てパッド2にワイヤ4を圧着固定する。このようなワイ
ヤボンデング前寝に於て圧着ポール3を正しく、パッド
2の中心位置にボンデングする必要がある。こpため本
発明では半導体チップ1のパッド2部分を撮像装置12
のレンズ系lit介して前処理回路14にチップ1のパ
ッド2近傍の映像信号を加えて2値化廼置する。尚13
は織傷装置12の駆動回路である0前処理回路14よ抄
の映倫出力は2値化映像メモリ15に記憶する。
5ell shows a system diagram of the fully automatic wire bonding apparatus of the present invention, in which an object to be recognized such as a semiconductor chip is placed on a loading stage 1G, and the surrounding area of the semiconductor chip 1 is
It has multiple pads 2 of 400 to 5 degrees
00710mm secondary pad 5 between 30#ψ@degree gold-
The wire 4 is heat-sealed. For this purpose, the wire 4 is crimped and fixed to the pad 2 via the crimping ball 3. Before such wire bonding, it is necessary to properly bond the crimp pole 3 to the center position of the pad 2. Therefore, in the present invention, the pad 2 portion of the semiconductor chip 1 is connected to the imaging device 12.
The video signal near the pad 2 of the chip 1 is applied to the preprocessing circuit 14 through the lens system lit, and is binarized. Sho 13
The output of the 0 preprocessing circuit 14, which is a drive circuit for the weaving device 12, is stored in a binarized video memory 15.

この鴬、値化映倫メモリ15は例えば114図に示され
て−るように半導体チップlのバッド意近傍の検査領域
6がメモリされて−る。
For example, as shown in FIG. 114, the value conversion memory 15 stores the inspection area 6 in the vicinity of the bad part of the semiconductor chip l.

尚7.8は十字状の走査線と検査領域の外周に沿つえ走
査線部分のメ49状態のlf4を示して−る。tSF1
制御回路で各ブロックを制御する。
Note that 7.8 shows lf4 in the state of 49 of the cross-shaped scanning line and the scanning line portion along the outer periphery of the inspection area. tSF1
Each block is controlled by a control circuit.

2値化映倫メモリ15の出力は第1及び第2の走査線設
定回路17ム、17Bに加えられる〇該第1及び第2の
走査線設定回路はパッド中心位置アドレス18よりの信
号が与えられて半導体パッド2の検査領域に沿って走査
線を設定する。走査Imを設定する場合定められた検査
領域の外周に沿って走査線の設定を行なうことを説明し
九がパッド2の中心a、bを求める工程はワイヤボンデ
ング前にパッド2の位置決めを行なっているので、パッ
ド中心位置a、bはパッド中心位置アドレス18に配憶
されており、このアドレスを利用してパッド20周辺に
適宜設定してもよい。
The output of the binarized video memory 15 is applied to the first and second scanning line setting circuits 17M and 17B. The first and second scanning line setting circuits are given a signal from the pad center position address 18. A scanning line is set along the inspection area of the semiconductor pad 2. When setting the scan Im, it is explained that the scanning line is set along the outer periphery of the defined inspection area. Therefore, the pad center positions a and b are stored in the pad center position address 18, and may be appropriately set around the pad 20 using this address.

本発明では第5図に示す如き走査線8ムで(実線で示す
領域)を第1の走査線設定回路174で走査し、第6図
に示す如き実線で示すコーナの領域8B1に@2の走査
線設定回路17Bで走査させる。走査@8ム又は8Bで
ワイヤ4が有るかな−かの検出は次段の1ml及第2の
ワイヤ信号検出回路19&、19Bで行なわれる。ワイ
ヤ信号検出回路19A、19Bでは第4図に示す2値化
映像メモリの走査IsBを走査する走査ライン8ムを第
1の走査線設定回路17Aで定められた通りに走査する
。同じく第2の走査線設定回路17Bで定められた通)
の走査ライン8Bを2値化映像メモリの走査線8部分に
行なう。ここで走査ライン8A、8Bとワイヤ4とが交
叉す多点9ム又tj9Bがなければ第4図に示す2値化
映倫メモリの2値化信号は0□でありワイヤ4が有れば
2値化信号は“1%を表示する。
In the present invention, the first scanning line setting circuit 174 scans the scanning line 8 as shown in FIG. Scanning is performed by the scanning line setting circuit 17B. Detection of the presence or absence of the wire 4 during scanning @8m or 8B is performed by the next stage 1ml and second wire signal detection circuits 19&, 19B. The wire signal detection circuits 19A and 19B scan the scanning line 8 which scans the scanning IsB of the binary video memory shown in FIG. 4 as determined by the first scanning line setting circuit 17A. (Same as determined by the second scanning line setting circuit 17B)
The scanning line 8B is applied to the scanning line 8 portion of the binarized video memory. If the scanning lines 8A, 8B and the wire 4 intersect at multiple points 9m or tj9B, the binarized signal of the binarized video memory shown in FIG. The value signal displays "1%".

このように、ワイヤ信号を検出するための具体的な回路
としては、第7図に示す如くデータ入力端子19cに加
えられ九走査ライン8A、8Bの続出データがnビット
のシフトレジスタ19dt−通じてデータ出力端子19
aに取9出されると共に例えば、8ピツトのプライオリ
ティエンコーダ19fからは基準ビットから連続して現
われるz値化信号It、の数を比較回路19hK与える
。鋏比較回路19hKはワイヤ4の太さに相当するビッ
ト数を基準値とした2値化信号が基準回路19gより与
えられるために基準ビットから連続して現われる2値化
信号と基準値が比較されてワイヤ4の有無が出力端子1
9JK取り出される。上述の如を出力端子19Jよシの
信号があれば圧着ボール3の巾Wを計測するための第1
又は第2の十字走査回路20A又F120Bが作動する
As shown in FIG. 7, a specific circuit for detecting a wire signal is such that the successive data of nine scanning lines 8A and 8B are input to the data input terminal 19c and passed through an n-bit shift register 19dt. Data output terminal 19
The comparison circuit 19hK receives the number of z-valued signals It extracted from the reference bits and successively appears from the 8-pit priority encoder 19f, for example. Since the scissors comparison circuit 19hK is given a binary signal from the reference circuit 19g with the number of bits corresponding to the thickness of the wire 4 as a reference value, the binary signal continuously appearing from the reference bits is compared with the reference value. The presence or absence of wire 4 is the output terminal 1.
9JK is taken out. If there is a signal from the output terminal 19J as described above, the first
Alternatively, the second cross scanning circuit 20A or F120B is activated.

即ち、走査ライン9Aでワイヤ4の有ることが確認され
た場合は第8図に示すようにパッド2の中心点(a、b
)を中心に検査領域6の対角線に走査7をなし走査ライ
ン9Bでワイヤ4の有ることが確認された場合は第9図
に示すようにパッド2の中心点(a、b)を中心に検査
領域60対向する辺間に直交する走査7を行なうように
する。かくすれば圧着ボール3の巾Wを正確に計測する
ことが出来る。
That is, when it is confirmed that the wire 4 is present on the scanning line 9A, the center point (a, b) of the pad 2 as shown in FIG.
), and if it is confirmed that there is a wire 4 on the scanning line 9B, then the inspection is performed centering on the center point (a, b) of the pad 2 as shown in Figure 9. Orthogonal scanning 7 is performed between opposing sides of region 60. In this way, the width W of the crimp ball 3 can be accurately measured.

即ちこのような計測手段によれば第2図に示すよう表誤
り針#1を避けることが出来る。
That is, by using such a measuring means, it is possible to avoid the front error needle #1 as shown in FIG.

十字走査回路20ム、20Bの出力は圧着ボール3の巾
wt圧着ボール中心検出回路21で中心検出が成されパ
ット2の中心(a、b)より圧着ボール3の中心迄のず
れ量が演算回路22で演算が行なわれて出力装置23に
与えられる。
The outputs of the cross scanning circuits 20 and 20B are the width of the crimp ball 3.The crimp ball center detection circuit 21 detects the center and calculates the amount of deviation from the center of the pad 2 (a, b) to the center of the crimp ball 3. A calculation is performed at 22 and the result is provided to an output device 23.

このずれ量をワイヤボンデング装置に加えて載置台゛1
0等iXY方向に移動させてタイヤボンデング位置を補
正する。
Add this amount of deviation to the wire bonding equipment and place it on the mounting table 1.
The tire bonding position is corrected by moving it in the iXY direction such as 0.

上記実施例では走査ライン8ム、8Bは走査線8の一辺
の比を第5図の如<1:2:1の割合に分割したがこれ
らの値は適宜の分割比に選択出来る。
In the above embodiment, the scanning lines 8M and 8B are divided at a ratio of <1:2:1 on one side of the scanning line 8 as shown in FIG. 5, but these values can be selected as appropriate division ratios.

本発明は上述の如く構成し九ので圧着ボール3の巾Wf
誤りなく検出出来ると共にワイヤボンデング装置を誤動
作なく自動化出来る4I像を有する。
The present invention is constructed as described above, and since the width Wf of the crimp ball 3 is
It has a 4I image that can be detected without error and can automate the wire bonding equipment without malfunction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の半導体パッド近傍と圧着ボールの関係
を示す平面図、第2図は、圧着ポール巾の計測時の弊害
を説明するためのパッド部分の平面図。第3図は1本発
明のワイヤボンデング装置の系統図。第4図は、第3図
に用いる2値化映像メモリの図、第5図及び第6図は本
発明の走査方法を示すパッド近傍の平面図、第7図はワ
イヤ信号検出回路例、第8図及び!9図は、本発明の走
査方法を説明するための・(ラド近傍の平面図である。 l・・・・・・半導体チップ 2.・・・・・・パッド
 3.・・・・・・圧着ボール 4.・・・・・ワイヤ
 5.・−・・・・2次J(ラド6・・・・・・検査領
域 7.8.・・・・・・走査線 10.・・−・・・
載置台 11.・−・・・−レンズ系 12.・・・・
・・撮像装置14、・・・・・・前処理回路 3s、−
・・・・2値化映像メモQ  17A、17B・・・・
・・第1及び第2の走査線設定回路 18.・・・・・
・パッド中心位置アドレス19、A 、 19.B−、
・・III及び第2ワイヤ信号検出回路 20ム、20
B・・・・・・十字走査回路21、・・・・・・圧着ボ
ール検出回路 2λ・・・−・・演算回路 23.・・
・・・・出力装置 實1 図 實2図 實4図 實5図    實6閃 偉7図 實8図   青9・図
FIG. 1 is a plan view showing the relationship between the vicinity of a conventional semiconductor pad and a crimp ball, and FIG. 2 is a plan view of a pad portion for explaining the disadvantages when measuring the width of a crimp pole. FIG. 3 is a system diagram of a wire bonding apparatus according to the present invention. 4 is a diagram of the binarized video memory used in FIG. 3; FIGS. 5 and 6 are plan views of the vicinity of the pad showing the scanning method of the present invention; FIG. 7 is an example of a wire signal detection circuit; 8 figures and! FIG. 9 is a plan view of the vicinity of the rad for explaining the scanning method of the present invention. l...Semiconductor chip 2. Pad 3. Crimp ball 4. Wire 5. Secondary J (rad 6 Inspection area 7.8 Scanning line 10.・・・
Mounting table 11.・−・− Lens system 12.・・・・・・
. . . Imaging device 14, . . . Preprocessing circuit 3s, -
...Binarized video memo Q 17A, 17B...
...First and second scanning line setting circuits 18.・・・・・・
- Pad center position address 19, A, 19. B-,
...III and second wire signal detection circuit 20m, 20
B...Cross scanning circuit 21,...Crimped ball detection circuit 2λ...--Arithmetic circuit 23.・・・
...Output device Fact 1 Figure 2 Figure 4 Figure 5 Figure 6 Flash 7 Figure 8 Blue 9.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップのワイヤボンデンダすべIs分を撮會して
皺2値化鵡履しえ出力を記憶する2値化映像メモリとパ
ッドの中心位置アドレスメモリと、上記2値化映儂メ毫
すと中心位置アドレスメモ9に基づ−て、上記パッドO
jI:i11の検査領域に走査線を設定するための走査
線設定手段と諌走査線設定手段の走査−に基づ−で、上
記2値化映像メモIJを走査してワイヤの有無を検出す
る手段と鍍ワイヤの有無を検出する手段よ伽の出力に基
づ−て検査領域内でパッド中心位置を通る走査線を設定
する手段とパッド中心位置を通る走査線設定によってワ
イヤー圧着部の中を求めてワイヤ圧着部中心を求める手
段とパッドの中心位置とワイヤ圧着部中心のずれを求め
る手段と上記圧着部のずれ量をワイヤぽンデンダ装置K
jlえてワイヤの圧着位置を補正すゐ手段とよりなるワ
イヤIンデング装置
A binarized video memory that records the entire wire bonder portion of the semiconductor chip and stores the crease binarized output, a pad center position address memory, and the binarized video image. Based on the center position address memo 9, the above pad O
The presence or absence of a wire is detected by scanning the binarized video memo IJ based on the scanning of the scanning line setting means and the cross scanning line setting means for setting a scanning line in the inspection area of jI:i11. a means for detecting the presence or absence of a wire; a means for setting a scanning line that passes through the center position of the pad within the inspection area based on the output of the sensor; means for determining the center of the wire crimping part; means for determining the deviation between the center position of the pad and the center of the wire crimping part; and the amount of deviation of the crimping part.
Wire bending device comprising means for correcting the crimp position of the wire
JP56102912A 1981-06-30 1981-06-30 Wire bonding system Pending JPS584938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56102912A JPS584938A (en) 1981-06-30 1981-06-30 Wire bonding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56102912A JPS584938A (en) 1981-06-30 1981-06-30 Wire bonding system

Publications (1)

Publication Number Publication Date
JPS584938A true JPS584938A (en) 1983-01-12

Family

ID=14340061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56102912A Pending JPS584938A (en) 1981-06-30 1981-06-30 Wire bonding system

Country Status (1)

Country Link
JP (1) JPS584938A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114678282A (en) * 2022-05-27 2022-06-28 湖北三维半导体集成创新中心有限责任公司 Bonding compensation method and device, chip rewiring method and bonding structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114678282A (en) * 2022-05-27 2022-06-28 湖北三维半导体集成创新中心有限责任公司 Bonding compensation method and device, chip rewiring method and bonding structure
CN114678282B (en) * 2022-05-27 2022-08-02 湖北三维半导体集成创新中心有限责任公司 Bonding compensation method and device, chip rewiring method and bonding structure

Similar Documents

Publication Publication Date Title
US5119436A (en) Method of centering bond positions
US5138180A (en) Wire bonding inspecting apparatus utilizing a controlling means for shifting from one inspected area to another
JP2851151B2 (en) Wire bonding inspection equipment
JP3235008B2 (en) Method and apparatus for detecting ball in wire bonding section
JPS584938A (en) Wire bonding system
KR100231274B1 (en) Pattern recognition system and recognition method of ground bonding location thereof
JPS6215909B2 (en)
JPS584937A (en) Inspecting system for semiconductor chip
JP3385916B2 (en) Wire detection method in wire bonding
JPH0576185B2 (en)
JP2648974B2 (en) Wire bonding apparatus and method capable of wiring inspection and automatic wiring inspection apparatus
JP4447101B2 (en) Inspection method of bonding state by image processing and wire bonding apparatus with inspection function using the same
JP4467176B2 (en) Bonding data setting device and method
JPS59144140A (en) Inspecting method of wire bonding portion
JPH01140737A (en) Wire bonding apparatus
JPH0897241A (en) Lead bonding position locating order determining method and its device
JPS60242627A (en) Wire-bonding method and apparatus therefor
JP3171949B2 (en) Wire bonding inspection method
JP3356259B2 (en) Wire-bonding method
JPS5867033A (en) Wire bonding method
JPH0864629A (en) Wire bonding method
JPH08316259A (en) Method and apparatus for wire bonding of semiconductor product
JPH11297747A (en) Wire bonding apparatus and visual inspection using the same
JPH0220144B2 (en)
JPS5848431A (en) Detecting device for wire bonding state