JPS6339751U - - Google Patents
Info
- Publication number
- JPS6339751U JPS6339751U JP13178286U JP13178286U JPS6339751U JP S6339751 U JPS6339751 U JP S6339751U JP 13178286 U JP13178286 U JP 13178286U JP 13178286 U JP13178286 U JP 13178286U JP S6339751 U JPS6339751 U JP S6339751U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- display
- input
- output
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は、本考案の一実施例を示したブロツク
図である。
１…アドレスバス、２…データバス、３…デイ
スプレイメモリ入出力装置、４…入出力処理装置
、５…デイスプレイ表示用メモリ、６…メインメ
モリ。
FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...address bus, 2...data bus, 3...display memory input/output device, 4...input/output processing device, 5...memory for display, 6...main memory.
Claims (1)
イ表示用のメモリに対する情報の入出力を高速に
処理する入出力処理装置と、前記デイスプレイ表
示用のメモリと別個独力したメインメモリとで成
る情報処理装置において、 前記デイスプレイ表示用のメモリとメインメモ
リとの各メモリアドレス等の格納条件を指定する
格納指定手段を設け、前記入出力処理装置からの
情報を該格納指定手段の指定に応じて前記デイス
プレイ表示用のメモリ又はメインメモリの高速に
入出力させることを特徴とする情報処理装置のメ
モリ入出力装置。[Claims for Utility Model Registration] A memory for display display, an input/output processing device that processes information input and output to and from the memory for display display at high speed, and a main memory that is independent of the memory for display display. In the information processing device, a storage specification means is provided for specifying storage conditions such as memory addresses of the display memory and the main memory, and information from the input/output processing device is specified by the storage specification device. A memory input/output device for an information processing apparatus, characterized in that the memory for displaying the display or the main memory can be input/output at high speed according to the request.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13178286U JPS6339751U (en) | 1986-08-27 | 1986-08-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13178286U JPS6339751U (en) | 1986-08-27 | 1986-08-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6339751U true JPS6339751U (en) | 1988-03-15 |
Family
ID=31030552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13178286U Pending JPS6339751U (en) | 1986-08-27 | 1986-08-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6339751U (en) |
-
1986
- 1986-08-27 JP JP13178286U patent/JPS6339751U/ja active Pending
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