JPS6339199A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To avoid malfunction of a memory even if a control input detection circuit is operated in error at a conventional readout by enabling a control signal to read a signature code at data erasure state and disabling a control signal to read after and during write of data to the memory cell array. CONSTITUTION:An output potential of a write storage circuit 6 is at a low level at the erasure state, and a logic circuit 11 applies the readout control of a signature code storage section 5. In starting the data writing to give the initial access to a specific word line of a memory cell array 3, since the writing is applied to the write storage circuit 6, the output potential of the circuit 6 goes to a high level during and after the writing, after the selection of the specific word line is finished. Thus, a noise signal is overlapped on a specific address terminal to cause an instantaneous high voltage in this state, and even if a high voltage detection circuit 6 generates in error a detection voltage, the logic condition of a logic circuit 11 is not satisfied, then no signature code is read in error.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory having a signature code, such as an EPROM (ultraviolet edge erasable electrically programmable bladder extraction only memory). In particular, the present invention relates to a means for controlling reading of a signature code.

(Conventional technology) EPROMs have a signature that includes the embedding method, manufacturer code, and device code (memory capacity, etc.).
A code is stored therein, and the signature code is read out when writing is performed by the FROM writer.

FIG. 2 schematically shows a part of a conventional EFROM, where 21 is an address buffer, 22 is a predecoder,
23 is a memory cell array, 24 is a high voltage detection circuit that detects when a high voltage is applied to one specific external terminal (for example, an address terminal), and 25 is a signature code storage unit that stores a signature code. The signature code is read out by the detection output of the high voltage detection circuit 24 and is controlled to be output from the data output buffer.

Incidentally, the signature code needs to be read before writing to the lPROM by the FROM writer, but it is not necessary to read the signature code during normal read operation of the gPROM. However, during the above-mentioned normal read operation, even though no high voltage is applied from the outside to the one specific address terminal, when a 1% voltage due to a noise signal is momentarily applied to the above-mentioned terminal, the high voltage The voltage detection circuit is activated. In this way, when the signature code is read by the operation of the high voltage detection circuit during a normal read operation, the internal control of the memory is performed so that it is impossible to read the memory data, and as a result, the memory is damaged. There was a problem that malfunctions occurred.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problem in which memory malfunctions occur due to the high voltage detection circuit being erroneously activated during normal read operations. Because of the book,
It is an object of the present invention to provide a semi-integrated memory capable of inhibiting the output of a signature code so as to prevent malfunction of the memory even if a signature code read control human power detection circuit is erroneously operated during normal aid output operation. do.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a writable semiconductor memory for storing a signature code that is exclusively used for bladder extraction, in which a predetermined control is applied to an external terminal in a data erased state of a memory cell array. The present invention is characterized in that a control means is provided that enables the signature code to be read by applying a signal, and disables the signature φ code to be read during and after writing data to the memory cell array.

(Function) Even if a control signal is erroneously generated at an external terminal due to the influence of noise, reading of the signature code is prohibited during and after writing data to the memory cell array. Memory malfunctions due to signature code reading are prevented.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 schematically shows a part of lil:FROM, where 1 is an address buffer, 2 is a predecoder, 3 is a memory cell array, and 4 is a high voltage applied to one specific external terminal (for example, an address terminal). (for example, 12 V) is applied, and 5 is a signature code storage section that stores a signature code.

On the other hand, 6 is a write memory circuit that stores whether or not data has been written to the memory cell array 3, and includes a memory cell transistor (for example, a floating gate transistor) 7 similar to that used in the memory cell array 3; A load circuit similar to that used in the memory peripheral circuit (a diode-connected MOS for pit line potential clamping) is inserted and connected to the control dart input path. It consists of a diode-connected MOS) Lanzostar 10, and the normal power supply voltages vae and vI! ls power supply (ground potential) is used. The drain (output end) of the memory cell transistor 7 is connected to a control terminal (r-), and the control gate includes a row that is accessed first when writing to the memory cell array 3 (for example, a row with address "0"). word m voltage (e.g. 5v when reading)
cc1! (a higher program voltage appears during writing than during reading). Therefore, when writing is performed on the memory cell 3, writing is performed on the memory cell in the row to be accessed first, and at the same time, writing is also performed on the memory cell transistor 7. The threshold voltage VTR of this memory cell transistor 7 becomes higher than VTIi in the erased state due to writing, so the output terminal potential is at a high level (v
ce potential). On the other hand, when the ≠n memory cell transistor is in the erased state, its VTR is low, so its output terminal potential is at a low level. Note that the memory cell transistor 7 is erased in the same way as the memory cell transistor of the memory cell array 3 when erasing the memory with ultraviolet rays.

Further, 11 is a logic circuit that controls whether or not the reading operation of the signature code storage unit 5 is possible, and a low level is manually input from the output terminal of the write storage circuit 6, and a high level detection output is output from the high voltage detection circuit 4. A signature code read control output is generated when the logical condition that the input signal is manually input is satisfied.

Next, the operation related to reading the signature code of the EPROM will be explained. For example, when a user writes data into an erased EPROM using a PROM writer, the user first performs a read check to see if the EPROM is in an erased state (all memory cell data in the memory cell array is at the 11" level), and then writes the data. A signature code, which is information necessary for writing, is read out. In order to explain this signature code, a high voltage is applied to one specific address terminal and a detection voltage is generated from the high voltage detection circuit 4. At this time, the write memory circuit 6 is in the erase state and the output potential is at a low level.
Logic circuit 11 controls reading of signature code storage section 5.

Next, write data. In this case, when data writing is started and a specific word line of the memory cell array 3 is accessed for the first time, writing is performed in the write memory circuit 6. (during data writing and after completion of data writing), the output potential of write memory circuit 6 is at a high level. therefore.

In this state, a noise signal is superimposed on the specific one address terminal, resulting in an instantaneous high voltage, and the high voltage detection circuit 4
Even if the detection voltage is erroneously generated, the logic condition of the logic circuit 11 will not be satisfied and the signature code will not be erroneously read.

In other words, the signature code will not be read by mistake when data is read for a verify operation during the data write or during a normal read operation after data write. , memory malfunctions are prevented.

Note that the present invention is not limited to the above-mentioned embodiments, and the specific configuration of the circuit 6 can be modified in various ways.
In addition to PIIOM, the present invention can be applied to writable read-only memories having signature codes. In addition, the signature code reading control manual control is not limited to the high voltage input as in the above embodiment, but various signals such as human power at a predetermined timing can be used. All you have to do is configure.

[Effects of the Invention] As described above, according to the semiconductor memory of the present invention, 1. Even if the signature code read control input detection circuit is accidentally activated during a normal read operation, the memory does not malfunction, so there are no troubles during use. decreases, EPROM
It is extremely effective when applied to, etc.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a part of a gPROM according to an embodiment of the present invention, and FIG. 2 is a configuration explanatory diagram showing a part of a conventional EFROM. 3...Memory cell array, 4...High voltage detection circuit. 5... Signature code storage section, 6... Write storage circuit, 7... Memory cell transistor, 11...
・Logic circuit.

Claims (3)

[Claims] (1) In a writable read-only semiconductor memory that stores a signature code, when the data of the memory cell array is erased, the signature code can be read by applying a predetermined control signal to an external terminal, and the signature code can be read out from the memory cell array. A semiconductor memory comprising control means for disabling readout of the signature code during and after data writing. (2) The control means includes a write storage circuit whose output potential level differs from the output potential level before writing due to writing performed at the start of data writing to the memory cell array, and a predetermined control signal present at the external terminal. a detection circuit for detecting whether or not the signature code is to be written, and control to read the signature code when both a control signal detection output from the detection circuit and an output potential level before writing from the write storage circuit are applied. Claim 1 characterized in that it consists of a logic circuit.
Semiconductor memory described in Section 1. (3) The semiconductor memory according to claim 2, wherein the write storage circuit uses the same memory cells as the memory cells of the memory cell array.