JPS6338731B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device that transfers serial data between a peripheral device and a storage device (hereinafter referred to as direct, memory, access: DMA transfer).

Conventional data processing devices include a central processing unit (CPU) 100 that processes data according to programs;
Storage (memory) device 102, peripheral device 103 and
It has a DMA control device 101, and each device is interconnected by a data bus 105, an address bus 104, and a control bus 106 for transferring control signals. Here, the memory device 102 consists of a plurality of memory chips, of which a predetermined memory chip is
It is configured to be used for DMA transfer.

In such a conventional data processing device, normal program processing is executed while transferring data between the CPU 100, memory 102, and peripheral device 103 using each connection bus. At this time, the DMA control device 101 is not involved in the processing and is disconnected from the bus. On the other hand, when the peripheral device 103 directly transfers data to and from the memory, the peripheral device 103 issues a DMA request signal to the CPU 100, and in response, the CPU 100 sends a DMA permission signal to the DMA request signal.
Output to control device. As a result, the right to use the data bus, address bus, and control bus is granted to the DMA control device 1.
Passed to 01. After this, the DMA control device 100
generates addresses sequentially from a predetermined start address and supplies them to the DMA memory chip via address bus 104. As a result, if the data write signal is input to the memory chip, peripheral device 1
The data sent from 03 via the data bus 105 is written to the memory address specified by the DMA control device 101, and if a data read signal is input, the data stored at that address is Read out to peripheral device.
In this way, during DMA transfer, data can be transferred directly between the DMA memory chip and the peripheral device 103 without the control of the CPU 100. However, recently, dynamic memory chips with low cost and large capacity functions have been widely used as memory chips. Writing (refreshing) must be performed. Such a refresh operation is performed when the CPU 100 uses the address bus 104.
The refresh address is set to be output sequentially at a constant cycle time, but the above
Since the CPU cannot use the address bus during DMA transfer, conventionally the DMA transfer has been forcibly interrupted to refresh the memory. Therefore, DMA transfer processing becomes extremely long, and processing efficiency is significantly reduced. This drawback becomes more significant as the memory capacity increases. Furthermore, since the DMA control device is provided as a single chip, an economical problem arises in that the cost of the entire processing device becomes high.

An object of the present invention is to provide a storage device that is low in cost and has a short DMA transfer processing time.

The storage device of the present invention has a DMA transfer address generation circuit in the memory chip used for DMA transfer, and does not use the address output from the CPU during DMA transfer.
It is designed to generate a DMA transfer address and perform DMA transfer. Therefore CPU and DMA
Since the address bus connecting memory chips other than the transfer memory chip is not monopolized for DMA transfer, other memory chips can be refreshed in parallel with DMA transfer.
This makes it possible to perform DAM transfers at high speed and eliminates the need for the DMA control device to consist of a separate chip, making the overall cost of the device extremely low.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows circuit blocks within the DMA transfer memory chip of this embodiment.

The DMA memory chip of this embodiment is 15
Bit A Terminal 15 for inputting external address _{0 to 14}
and an external address bus 13 that introduces external addresses.
and an internal address bus 14 for introducing DMA addresses generated inside the chip, both of which are selected by the gate 2 and applied to the memory block 4 via the address decoder 3. Data written to and read from memory 4 is transferred to 8-bit internal data bus 1 via gate 6.
6. Input/output to ID _0-7 . This internal data bus 16 is connected to an external data bus lead-out path 18 via a data buffer 5, and data is guided to an external data bus terminal 17. Alternatively, it is input from this terminal 17. Data on internal data bus 16 is supplied via gate 8 to first register 9 and also directly to second register 11 .
The data set in the first register is passed through the latch circuit 10 to gate 2 and +1 (increment).
Alternatively, it is input to an logic operation unit (ALU) 7 having a -1 (decrement) function. + with ALU7
The data on which the 1 or -1 operation was performed is sent to gate 8.
The data is stored in the first register 9 again via the . Further, the data stored in the first register 9 and the second register 11 are compared by a comparator 12. Control of each of these circuits is performed by a control circuit 1.

The operation of a data processing device including a DMA memory chip having such a circuit configuration will be described below with reference to the timing diagram of FIG.

Each control signal input to the control circuit chip 1 in FIG. 2 is output from the CPU or other control mechanism, and includes a reset signal RST, control signal I/M, data read control signal, data write control signal, and chip Contains a selection signal.

Now “1” level from CPU (timing A)
When the reset signal RST is input to the control circuit 1, the control signal G3 goes to the "1" level, and the external addresses _A14-0 are output from the selection gate 2. The output of this gate 2 is input to an address decoder 3 and is connected to designate a part of the memory group 4. Here, if the I/M signal is "0" and the signal and signal are "0" (timing B), the control circuit 1 sets the control signal G1 to the "1" level, and thereby the data buffer 5 is connected to the external data bus 18. information
Take in D7 _~0 to internal bus 16, ID7 _~0 . Further, the control signal G2 of the control circuit 1 becomes "1", and the gate 6 outputs the information ID _{7 to 0} on the internal bus 16 to be written to the address specified by the external address A _{14 to 0} in the memory group 4. Store it in that address. As a result, information is written from the data bus to the storage element designated by the external address _A14-0 . On the other hand, when the I/M signal is "0", the signal is "0", and the signal is "0" (timing C), the control signal G2 becomes "1" and the gate 6 is specified by the external address _A14-0 . Outputs the information of the stored memory elements to internal bus IDs _{7 to 0} .
Furthermore, the data buffer 5 is opened by the control signal G1 "0" and the signal "0", and the information IDs _{7 to 0} on the internal bus 16 are output to the external data bus 18. That is, information is read from the storage element designated by the external address _A14-0 onto the external data bus _D7-0 .

After resetting like this, this memory chip is
It is associated with the CPU and operates as a read/write memory device in normal data processing.

Next, at timing D, the I/O signal becomes "1" level and when the signal is "0" level, when the first signal ₁ of "0" level is input, the control signal G1 becomes "1" and the data The bus buffer 5 is opened and 8-bit first data D _{7 -0} is input from the external data terminal 17 to the internal data bus 16 .
This first data is input to the control circuit 1 and sets the control signal G3, which controls outputting the contents of the latch 10 to the gate 2, to the "0" level. Furthermore, ALU
A control signal C is generated that specifies whether to increment or decrement 7 (in this embodiment, it is set to increment). Initial settings for DMA transfer processing are executed through this series of operations. At this time, the memory group 4 and the internal data bus 16 are separated from each other by the gate 6 because the control signal G2 is at the "0" level. Next, when the second signal ₂ at the "0" level is input, the second data is taken into the internal data bus 16 from the external data terminal 17. At this time, since the control signal G4 of the control circuit 1 is at "0" due to the reset signal at the "1" level, the gate 8 outputs the second data on the internal bus 16 to the register 9. Further, when the second signal ₂ is "0", the control signal R1L of the control circuit 1 becomes "1", and the output of the gate 8 is stored in the lower eight digits of the register 9.
Furthermore, the third data is sent to the data buffer 5, internal bus 16, and gate 8 by the third signal ₃ “0”.
The data is stored in the upper seven digits of register 9 via . Here, the data (second data + third data) set in the upper and lower digits of register 9, totaling 15 digits, is used as the start address of memory 4. Third
At the rising edge of the signal ₃ , the start address set in the register 9 is taken into the latch 10, and further inputted to the address decoder 3 via the gate 2, where it is decoded and specifies a part of the memory group 4. When the fourth signal ₄ "0" is generated, the control signal R2L of the control circuit 1 becomes "1" and the fourth data is transferred to the data bus buffer 5 and the internal bus.
It is stored in the lower eight digits of the register 11 via IDs _{7 to 0} . Subsequently, when the fifth signal ₅ becomes "0", the control signal R2H of the control circuit 1 becomes "1", and the fifth signal R2H becomes "1".
data is transferred to data bus buffer 5, internal bus
It is stored in the upper seven digits of the register 11 via IDs _{6 to 0} . The data set in register 11 here is used as an end address. Furthermore, ALU7
control signal G to make the output from gate 8 the output from gate 8.
4 becomes “1” at the rising edge of the fifth signal ₅ .
Initialization for DMA operation is completed.

Next, at timing E, the signal becomes “0”, and when the signal becomes “0”, the control signals G1 and G2 each become “1”.
Information is input from the external data bus to the address of the memory 4 designated by the start address of the latch 10 via the data bus buffer 5, internal buses _ID7-0 , and gate 6 and is stored therein. Further, the start address of the latch 10 is compared with the end address of the register 11 by the comparator 12, and if the two do not match, the output of the comparator 12 becomes "0" and the control circuit 1 is notified. Further, the ALU 7 set to increment (+1) by the control signal C of the control circuit 1 increments the address of the latch 10 by +1 and inputs it to the register 9 via the gate 8. At this time, since the control signal L is "0", the latch 10 is still storing and outputting the start address. After this
At the rising edge of the WR signal, the control signal L becomes “1”,
The address newly set in register 9 is read out to memory 4 via latch 10. Further next
By inputting the CS signal "0" and the signal "0", the control signals G1 and G2 are set to "1", and the external data bus is transferred to the memory 4 address specified by the new address.
_D7-0 information is input and stored. Further, the new address of the latch 10 is compared with the end address of the register 11 by the comparator 12, and if they do not match, the output of the comparator 12 becomes "0" and is notified to the control circuit 1. Furthermore, in the same way as described above, ALU7 increments (+1) the address of latch 10.
Then, the incremented address, that is, the start address +2, is set in the register 9 via the gate 8. This address is input to latch 10 at the rising edge of the signal, and latch 10 outputs the start address +2. As mentioned above, the address of the register 9 is sequentially incremented by the generation of the signal "0" to sequentially address the memory 4,
Peripheral circuit information sent from the external data bus 18 is stored at each address. These incremented addresses are successively compared with the end address stored in the register 11, and if they do not match, the above operation is repeated, and if they match, the output of the comparator 12 becomes "1", and the next
The last information is stored in the address of the memory 4 designated by the WR signal "0", that is, the address that matches the end address. Further, at the rising edge of this signal due to the output "1" of the comparator 12, the control signal G3 of the control circuit 1 is set to "1" and the internal address bus 14 is disconnected from the gate 2 (timing F). Upon completion of this operation, the DMA transfer process ends.

Note that in this embodiment, after the initial setting for DMA operation, the signal “0” is changed instead of the signal “0”.
It is of course possible to read out information from the memory 4 to the external data bus 18 via the gate 6, internal bus 16, and data buffer 5 by inputting .

As described above, according to this embodiment, since the DMA address for DMA transfer can be generated within the DMA transfer memory chip, the refresh operation of other dynamic memories can be performed in parallel using the external address bus during DMA transfer. and can be executed. Therefore, DMA transfer can be executed at high speed without interruption. In addition, since the DMA transfer address is generated internally on the chip, no DMA transfer address is generated externally.
Since a transfer address bus and a DMA control device are not required, it is very economically advantageous and the device itself is simplified.

It is clear that when the memory chip of this embodiment is used for DMA transfer, the CPU and other control equipment can perform data processing other than refresh processing using the external address bus. In this case, the use of a data bus that connects the CPU, memory, and peripheral circuits becomes a problem, but it is sufficient to form a separate bus that connects the memory and peripheral circuits used for DMA transfer, or in the case of a common bus. A time-shu Linda method (time division method) may be used. Further, even if the function of the ALU 7 is set to decrement (-1), the effects of the present invention can be sufficiently obtained by simply changing the address designation order. Furthermore, although this embodiment has presented an example in which the CPU, memory, peripheral circuits, etc. are each constructed from independent chips, the present invention may be applied to the DMA memory section by integrating these into one chip. Furthermore, if the address space of the memory for DMA transfer is determined in advance, it is not necessarily necessary to compare with the end address as in this embodiment. In this case, comparator 1
2. Instead of the register 11, a counting circuit or a timer may be provided and set to generate a predetermined number of addresses. Furthermore, the DMA of this example
Although the memory chip is formed of static memory in the example shown, even if this memory chip is formed of dynamic memory, if the internal address is used as the refresh address, it can be refreshed very easily via the internal data bus. can be executed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional data processing device having a DMA control function, Fig. 2 is a circuit block diagram of a memory chip for DMA transfer showing an embodiment of the present invention, and Fig. 3 is an operation timing diagram thereof. be. 100... central processing unit, 101... DMA control device, 102... memory device, 103... peripheral device, 104... address bus, 105... data bus, 106... control bus, 1... control circuit,
2...Gate, 3...Address decoder, 4...
Memory circuit, 5...Data bus buffer, 6...Gate, 7...Logic operation circuit, 8...Gate, 9...
...Register, 10...Latch, 11...Register, 12...Comparator, 13...External address introduction bus, 14...Internal address bus, 15...External address bus terminal, 16...Internal data bus, 1
7...External data bus terminal, 18...External data input/output bus.

Claims (1)

[Claims] 1 A storage device that can directly transfer data to and from a peripheral device without the intervention of a central processing unit, the storage device being composed of a plurality of semiconductor chips, each chip being connected to an external address bus. It consists of an external address input section, a dynamic memory that requires refresh, an internal address generation section, a data input/output section, a switching gate, and a control section.
During the direct data transfer, under the control of the control section, the internal address generation section takes in external data from the data input/output section as an initial setting value, sequentially generates internal addresses based on it, and generates the internal address via the switching gate. The internal address generation section and the dynamic memory are connected, and during non-direct data transfer, the external address input section and the dynamic memory are connected via the switching gate under the control of the control section. A storage device characterized in that when one chip is performing the direct data transfer, other chips can perform other operations.