JPS6338262A - Power mos field-effect transistor - Google Patents
Power mos field-effect transistorInfo
- Publication number
- JPS6338262A JPS6338262A JP61182228A JP18222886A JPS6338262A JP S6338262 A JPS6338262 A JP S6338262A JP 61182228 A JP61182228 A JP 61182228A JP 18222886 A JP18222886 A JP 18222886A JP S6338262 A JPS6338262 A JP S6338262A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- source
- region
- gate
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 5
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 3
- 229920005591 polysilicon Polymers 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 230000007547 defect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241000220317 Rosa Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、スイッチング機器等に利用される電力用ＭＯ
３型電界効果トランジスタ（以下パワーＭＯＳＦＥＴと
記す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to power MOs used in switching equipment, etc.
The present invention relates to a type 3 field effect transistor (hereinafter referred to as a power MOSFET).
従来の技術
パワーＭＯ３ＦＥＴは、従来から電力用素子として幅広
く用いられているバイポーラトランジスタに比べ、高速
でかつ破壊耐量が大きいこと等で、理想的なスイッチン
グ素子として幅広い分野で利用されている。Conventional technology Power MO3FETs are used in a wide range of fields as ideal switching elements because they are faster and have greater breakdown resistance than bipolar transistors, which have traditionally been widely used as power devices.
従来のパワーＭＯＳＦＥＴの基本セルは、第３図に示す
ような断面構造であり、図示するパワーＭＯＳＦＥＴが
Ｎチャンネル形であるものとじて以下に詳しく説明する
。A basic cell of a conventional power MOSFET has a cross-sectional structure as shown in FIG. 3, and will be described in detail below assuming that the power MOSFET shown in the figure is an N-channel type.
このパワーＭＯＳＦＥＴは、１・ｌ／イン領域となる低
不純物濃度のＮ形シリコン基板１の中の多数箇所にチャ
ンネル領域形成用の１）形拡散領域２が分離されて形成
され、このＰ形拡散領域２の中の一部分にＮ形のソース
領域３が形成され、シリコン基板１部分を挟んで相対す
るソース領域３間のシリコン基板１表面にｌｉ ｌ、
酸化膜４が１１ツ成され、このゲート酸化膜４の−１に
／、？ −ト電極５が形成され、さらに）、’ ｌ、
電極５のＬに層間絶縁膜６が形成され、ソース領域３お
よびｐ ＋に拡散領域２の双方に接続される関係でソー
ス電４４ｉ７が（テ［ぽ表面全域に形成され、シリ：ｒ
７ＪＩ！、１反１の外面にドレイン電極８が形成された
構造となっていイ）。This power MOSFET is formed by separating 1)-type diffusion regions 2 for forming a channel region at multiple locations in a low impurity concentration N-type silicon substrate 1, which serves as a 1.l/in region. An N-type source region 3 is formed in a part of the region 2, and li, l,
Eleven oxide films 4 are formed, and on -1 of this gate oxide film 4 /, ? - electrode 5 is formed, and further),' l,
An interlayer insulating film 6 is formed on the L of the electrode 5, and a source electrode 44i7 is formed over the entire surface of the electrode 5, connected to both the source region 3 and the p+ diffusion region 2.
7JI! , has a structure in which a drain electrode 8 is formed on the outer surface of a 1×1).
この構造のパ［ノーＭ ＯＳ Ｆｒ・：′Ｉ゛ではツノ
゛−ｈ ｉｆ電極にプ’）Ｘの電圧が印加され、Ｐ形拡
散領域２とゲート酸化Ｉｆ！ ４との界面に＝ｆｌ−ン
ネルができると、電子はソース領域３からこのヂ・トン
ネルを通ってトレイン領域の表面部分に達し、ここから
裏面に設けたドレイン電極８に向かって流れる。In this structure, a voltage of P')X is applied to the horn-hif electrode in the P-type diffusion region 2 and the gate oxidation If! When a =fl- tunnel is formed at the interface with the source region 3, electrons pass through this di-tunnel from the source region 3, reach the surface portion of the train region, and flow from there toward the drain electrode 8 provided on the back surface.
第４図にパワーＭＯ３ＦＥＴをチップ表面から見た概略
図を示す。実際のチップは第３図に示した微細な基本セ
ルが数千側集積された構造となっている。FIG. 4 shows a schematic diagram of the power MO3FET viewed from the chip surface. An actual chip has a structure in which several thousand fine basic cells are integrated as shown in FIG.
このパワーＭＯＳＦＥＴでは、ゲート電極５が点線で示
すストライブ形状部分とこれらの一端を共通接続する共
通接続部分とからなり、さらに、共通接続部分の一部分
にゲート電極用のワイヤーポンディングパッド領域９が
形成された櫛形の形状をなし、また、ソース電極７がシ
リコン基板上のＩＡぼ表面全域ｌこ形成され、その一部
分にソース電極用のポンディングパッド領域１０を有す
る形状となっている。なお、ソース電極７とゲート電極
５との間には層間絶縁膜が形成されている。In this power MOSFET, the gate electrode 5 consists of a striped portion shown by a dotted line and a common connection portion that commonly connects one end of these portions, and a wire bonding pad region 9 for the gate electrode is further provided in a part of the common connection portion. A source electrode 7 is formed over the entire surface of the IA on the silicon substrate, and a part thereof has a bonding pad region 10 for the source electrode. Note that an interlayer insulating film is formed between the source electrode 7 and the gate electrode 5.
以１−説明してきた様に、従来のパワーＭＯＳＦＥＴで
はチップの大部分にわたって、ソース電極とデー１−電
極が層間絶縁膜を介してオーバーラツプした構造となっ
ている。As described above, a conventional power MOSFET has a structure in which the source electrode and the data electrode overlap with each other via an interlayer insulating film over most of the chip.
発明が解決しようとする問題点
この様な構造のパワーＭＯ３ＦＥＴでは、ソース電極と
ゲート電極およびその間に挟Ｊ、れた層間絶縁膜ｌこよ
りコンデンサが形成され、ゲート・ソース間の容量が増
大する。このため、人力電力の増大やスイッグーングス
ピードの低下をらたらず問題があった。Problems to be Solved by the Invention In a power MO3FET having such a structure, a capacitor is formed from the source electrode, the gate electrode, and the interlayer insulating film sandwiched between them, and the capacitance between the gate and source increases. For this reason, there were problems with an increase in human power and a decrease in swiggling speed.
本発明はこのような問題を解決するらので、ゲート・ソ
ース間の容量を低減し、入力電力の低減やスイッヂング
スビ−１・の向上を図ることをＩｊｌ的本完本発明ワー
Ｍ ＯＳ Ｆ Ｅ Ｔは上記の問題を排除するものであ
って、ドレイン領域を形成するー・導電形の半導体基板
の多数箇所に前記半導体基板とは逆導電形のチャンネル
領域形成用の拡散領域が形成され、同拡散領域内の一部
分に一導電形のソース領域が形成され、前記ドレイン領
域を挟んで相対するソース間の前記半導体基板表面上に
ゲート絶縁膜が形成され、同グート絶縁膜上にゲート電
極がストライブ形状に形成され、同ゲート電極上に層間
絶縁膜が形成され、前記ソース領域お＝ ５−
よび前記拡散領域の双方に接続される関係でソース電極
がストライブ形状に形成され、前記半導体基板の裏面に
ドレイン電極が形成されるとともに、前記ゲート電極と
前記ソース電極がストライブ形状の領域では互いにオー
バーラツプせず、前記ソース電極のストライプ形状の一
端を共通接続する共通接続部分で前記ソース電極を前記
層間絶縁膜を挟んで前記ゲート電極とオーバーラツプさ
せてこの部分でソース電極の面積を広げた構造のもので
ある。Since the present invention solves these problems, the present invention aims to reduce the capacitance between the gate and the source, thereby reducing the input power and improving the switching performance. This method eliminates the above problem, and forms a drain region. Diffusion regions for forming a channel region of a conductivity type opposite to that of the semiconductor substrate are formed at multiple locations on a semiconductor substrate of a conductivity type, and A source region of one conductivity type is formed in a part of the region, a gate insulating film is formed on the surface of the semiconductor substrate between the opposing sources with the drain region in between, and a gate electrode is striped on the gate insulating film. An interlayer insulating film is formed on the gate electrode, and a source electrode is formed in a stripe shape so as to be connected to both the source region and the diffusion region. A drain electrode is formed on the back surface, and the gate electrode and the source electrode do not overlap each other in the striped region, and the source electrode is connected to the source electrode at a common connection portion where one end of the striped shape of the source electrode is commonly connected. This structure has a structure in which the source electrode overlaps the gate electrode with an interlayer insulating film in between, and the area of the source electrode is increased in this area.
作用
この構造によれば、ゲート電極とソース電極とのオーバ
ーラツプ部分の面積を大幅に減少させるため、ゲート・
ソース間容量を大幅に低減させることができるとともに
、層間絶縁膜のピンホール等によるゲート・ソース間の
短絡不良を減少させることができる。しかも大きな電流
が流れるソース電極の共通接続部分ではソース電極の面
積が広いため、ソース電極の電気抵抗の増大を緩和させ
ることができる。Function: This structure greatly reduces the area of the overlap between the gate electrode and the source electrode.
The source-to-source capacitance can be significantly reduced, and short-circuit defects between the gate and source due to pinholes in the interlayer insulating film can be reduced. Moreover, since the area of the source electrodes is large in the common connection portion of the source electrodes through which a large current flows, an increase in the electrical resistance of the source electrodes can be alleviated.
実施例
本発明のパワーＭ ＯＳ Ｆ Ｅ Ｔの実施例について
、第１図に示した基本セルの構造断面斜視図および第２
図に示したチップの概略の平面図を参照して説明する。Embodiment Regarding an embodiment of the power MOSFET of the present invention, a structural cross-sectional perspective view of the basic cell shown in FIG.
Description will be given with reference to a schematic plan view of the chip shown in the figure.
第１図に示したＮチャンネルパワーＭ ＯＳ Ｆ Ｅ
Ｔは、ドレイン領域を形成する低不純物濃度のＮ形シリ
コン基板１の中の多数箇所にチャンネル領域形成用のＰ
形拡散領域２が公刊されて形成され、このＰ形拡散領域
２の中の二部分にＮ形のソース領域３が形成されている
。そして、シリコン基板１部分を挟んで相対するソース
領域３間のシリコン基板表面にゲート酸化膜４が形成さ
れている。N-channel power MOSFE shown in Figure 1
T is P for forming a channel region at many locations in the N-type silicon substrate 1 with a low impurity concentration that forms the drain region.
A P-type diffusion region 2 is formed, and an N-type source region 3 is formed in two parts of the P-type diffusion region 2. A gate oxide film 4 is formed on the surface of the silicon substrate between the source regions 3 facing each other with the silicon substrate 1 portion in between.
このゲート酸化膜４の−１−にポリシリ二丁１ンのゲー
ト電極５がストライプ状に形成され、この７１′−１・
電極５の−１１に層間絶縁膜６が形成されている。さら
に、ソース領域３およびＩ）形拡ｆｔ、領域２の双方に
接続される関係でソース電極７がスｌ−ｆｉイブ状に形
成され、シリコンＷ板１の裏面にドレイン電極８が形成
された構造である。Two gate electrodes 5 made of polysilicon are formed in stripes on -1- of this gate oxide film 4, and these gate electrodes 71'-1,
An interlayer insulating film 6 is formed at -11 of the electrode 5. Furthermore, a source electrode 7 is formed in a sl-fi shape so as to be connected to both the source region 3 and the I) type expansion region 2, and a drain electrode 8 is formed on the back surface of the silicon W plate 1. It is a structure.
チップ表面から見たゲート電極５とソース電極７の形状
は、第２図に示すようにストライプ形状部分とこれらの
一端を共通接続する共通接続部分とからなるくし形の形
状をなし、共通接続部分は互いに反対側に位置し、ゲー
ト電極５とソース電極７のストライプ形状部分、ゲート
電極の共通接続部分、ゲート電極用のポンディングパッ
ド領域９およびソース電極用のポンディングパッド領域
１０ではゲート電極５とソース電極７とをオーバーラツ
プさせず、ソース電極７の共通接続部分でのみ層間絶縁
膜を挟んでゲート電極のストライプ状部分をオーバーラ
ツプさせた形である。As shown in FIG. 2, the gate electrode 5 and source electrode 7 have a comb-like shape when viewed from the chip surface, consisting of a stripe-shaped portion and a common connection portion that commonly connects one end of these portions. are located on opposite sides of each other, and the striped portion of the gate electrode 5 and the source electrode 7, the common connection portion of the gate electrodes, the gate electrode bonding pad region 9, and the source electrode bonding pad region 10 are located on opposite sides of the gate electrode 5. In this configuration, the gate electrode 7 and the source electrode 7 do not overlap, but the striped portions of the gate electrode overlap only at the common connection portion of the source electrode 7 with an interlayer insulating film in between.
なお、ゲート電極５は層間絶縁膜の下にあって、ゲート
電極用のポンディングパッド領域９の上のみ層間絶縁膜
を除去してゲート電極５が露出した構造となっている。Note that the gate electrode 5 is located under the interlayer insulating film, and the interlayer insulating film is removed only on the gate electrode bonding pad region 9 to expose the gate electrode 5.
すなわち、ゲート電極５とソース電極７とがオーバーラ
ツプしない領域を大部分とし、分割された各ソース電極
を流れた電流が集まってくるソース電極の共通接続部分
でのみソース電極７をゲート電極５にオーバーラツプさ
せた構造とし、この領域でソース電極の面積を広（して
、ソース電極の抵抗の低減化を図っている。In other words, most of the area is where the gate electrode 5 and the source electrode 7 do not overlap, and the source electrode 7 overlaps the gate electrode 5 only at the common connection part of the source electrodes where the current flowing through each divided source electrode collects. The area of the source electrode is increased in this region to reduce the resistance of the source electrode.
なお、実施例ではソース電極もゲート電極も（し形の形
状で説明したが、これに限られたわけでなく両者が魚骨
形状のものであってもよいし、くし形と魚骨形状を組み
合わせたものであってもよい。In the embodiment, the source electrode and the gate electrode are explained in the shape of a diamond (although the shape is not limited to this, both may be shaped like a fishbone, or a combination of the shape of a wedge and a fishbone). It may be something like that.
発明の効果
本発明では、パワーＭＯＳＦＥＴのゲート電極とソース
電極とのオーバーラツプ面積を大幅に減少させることに
より、ゲート・ソース間の容量および入力電力を従来よ
りも大幅に低減させることができる。この結果、ゲート
電極の充放電時間が短縮化されパワーＭＯＳＦＥＴのス
イッヂングスピードを早める効果が奏される。また、層
間絶縁膜のピンホール等で発生していたゲート・ソース
間のショート不良が大幅に低減し、歩留りが向上すると
いう効果も得られる。Effects of the Invention In the present invention, by significantly reducing the overlapping area between the gate electrode and source electrode of a power MOSFET, the capacitance between the gate and source and the input power can be significantly reduced compared to conventional methods. As a result, the charging/discharging time of the gate electrode is shortened and the switching speed of the power MOSFET is increased. In addition, short-circuit defects between the gate and source, which occur due to pinholes in the interlayer insulating film, are significantly reduced, and yields are improved.
第１図は本発明のパワーＭＯ３ＦＥＴの基本セルの実施
例を示す構造断面斜視図、第２図は本発明のパワーＭＯ
ＳＦＥＴの実施例を示すチップの概略の平面図、第３図
は従来のパワーＭＯＳＦＥＴの基本セルの構造断面斜視
図、第４図は従来のパワーＭＯＳＦＥＴのチップの概略
の平面図である。
１・・・・・・シリコン基板、２・・・・・・チャンネ
ル形成用Ｐ形拡散領域、３・・・・・・ソース領域、４
・・・・・・ゲート酸化膜、５・・・・・・ゲート電極
、６・・・・・・層間絶縁膜、７・・・・・・ソース電
極、８・・・・・・ドレイン電極、９・・・・・・ゲー
ト電極用のワイヤーポンディングパッド領域、１０・・
・・・・ソース電極用のワイヤーポンディングパッド領
域。
代理人の氏名 弁理士 中尾敏男 ほか１名／−−−シ
１ノコン基板
乙一層間多芭縁腺
第３図
１θ−ソースｊ才亙用のツイヤ−
ボンデインク“バラ）″領域
第２図
１θFIG. 1 is a structural cross-sectional perspective view showing an embodiment of the basic cell of the power MO3FET of the present invention, and FIG.
FIG. 3 is a schematic cross-sectional perspective view of a basic cell of a conventional power MOSFET; FIG. 4 is a schematic plan view of a conventional power MOSFET chip. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... P-type diffusion region for channel formation, 3... Source region, 4
...Gate oxide film, 5 ... Gate electrode, 6 ... Interlayer insulating film, 7 ... Source electrode, 8 ... Drain electrode , 9... Wire bonding pad area for gate electrode, 10...
...Wire bonding pad area for source electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person / ---S1 No. board B1 interlayer multi-layered gland Fig. 3 1θ - Source j Saito's Tsuya - Bonde ink "Rose)" area Fig. 2 1θ
Claims (2)
多数箇所に前記半導体基板とは逆導電形のチャンネル領
域形成用の拡散領域が形成され、同拡散領域内の二部分
に一導電形のソース領域が形成され、前記ドレイン領域
を挟んで相対するソース間の前記半導体基板表面上にゲ
ート絶縁膜が形成され、同ゲート絶縁膜上にゲート電極
がストライプ形状に形成され、同ゲート電極上に層間絶
縁膜が形成され、前記ソース領域および前記拡散領域の
双方に接続される関係でソース電極がストライプ形状に
形成され、前記半導体基板の裏面にドレイン電極が形成
されるとともに、前記ゲート電極と前記ソース電極がス
トライプ形状の領域では互いにオーバーラップせず、前
記ソース電極のストライプ形状の一端を共通接続する共
通接続部分で前記ソース電極を前記層間絶縁膜を挟んで
前記ゲート電極とオーバーラップさせていることを特徴
とする電力用ＭＯＳ型電界効果トランジスタ。(1) Diffusion regions for forming a channel region of a conductivity type opposite to that of the semiconductor substrate are formed at multiple locations on a semiconductor substrate of one conductivity type forming a drain region, and diffusion regions of a conductivity type of one conductivity type are formed in two parts within the same diffusion region. A source region is formed, a gate insulating film is formed on the surface of the semiconductor substrate between sources facing each other with the drain region in between, a gate electrode is formed in a stripe shape on the gate insulating film, and a gate electrode is formed in a stripe shape on the gate insulating film. An interlayer insulating film is formed, a source electrode is formed in a stripe shape so as to be connected to both the source region and the diffusion region, a drain electrode is formed on the back surface of the semiconductor substrate, and a source electrode is formed in a stripe shape to be connected to both the source region and the diffusion region. The source electrodes do not overlap each other in the striped region, and the source electrode overlaps the gate electrode with the interlayer insulating film in between at a common connection portion where one end of the striped shape of the source electrode is commonly connected. A power MOS type field effect transistor characterized by the following.
を特徴とする特許請求の範囲第（１）項に記載の電力用
ＭＯＳ型電界効果トランジスタ。(2) The power MOS type field effect transistor according to claim (1), wherein the gate electrode is formed of polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61182228A JPH07118541B2 (en) | 1986-08-01 | 1986-08-01 | Power MOS type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61182228A JPH07118541B2 (en) | 1986-08-01 | 1986-08-01 | Power MOS type field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6338262A true JPS6338262A (en) | 1988-02-18 |
| JPH07118541B2 JPH07118541B2 (en) | 1995-12-18 |
Family
ID=16114584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61182228A Expired - Fee Related JPH07118541B2 (en) | 1986-08-01 | 1986-08-01 | Power MOS type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118541B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04322471A (en) * | 1991-04-23 | 1992-11-12 | Mitsubishi Electric Corp | Mos semiconductor device and manufacture thereof |
| JP2000156383A (en) * | 1998-11-09 | 2000-06-06 | Internatl Rectifier Corp | Low voltage mosfet and its manufacture and its circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS545674A (en) * | 1977-06-15 | 1979-01-17 | Sony Corp | Semiconductor device |
-
1986
- 1986-08-01 JP JP61182228A patent/JPH07118541B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS545674A (en) * | 1977-06-15 | 1979-01-17 | Sony Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04322471A (en) * | 1991-04-23 | 1992-11-12 | Mitsubishi Electric Corp | Mos semiconductor device and manufacture thereof |
| JP2000156383A (en) * | 1998-11-09 | 2000-06-06 | Internatl Rectifier Corp | Low voltage mosfet and its manufacture and its circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07118541B2 (en) | 1995-12-18 |
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