JPS6336599B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that allows input from a key matrix and other auxiliary control inputs to be input to an integrated circuit element, and which allows the number of input/output terminals to be minimized. The present invention is intended to provide a device that is advantageous for integrated circuit devices.

In television receivers, channel switching, power supply, volume, and other controls are controlled by key matrix operations, and more and more television receivers are also capable of remote control. A device that performs discrimination processing using an integrated circuit element is being considered.

First, a control input device conventionally used in such cases will be explained with reference to FIG. Here, 1 is an integrated circuit element for discrimination processing,
2 is a key matrix for main input connected to the outside, and 3 is a remote control receiving circuit as an auxiliary control signal generation circuit for auxiliary input also connected to the outside. The integrated circuit element 1 for discrimination processing includes a basic clock generating circuit 4 and a multi-phase clock generating circuit 4, which generates four multiphase clocks with different phases as key input clocks by dividing the basic clock output from the basic clock generating circuit 4. A phase clock generation circuit 5, a key discrimination circuit 6, and a control circuit 7 that controls switching of channels, power supply, volume, etc. based on the key input clock input from the key matrix 2 and the input from the remote control receiving circuit 3. We are prepared.
8 is an output terminal of a key input clock, 9 is an input terminal of a key input clock selected by operation from the key matrix 2, 10 is an input terminal of a control signal from the remote control receiving circuit 3, 1
1 is an output terminal for switching control output.

The key discrimination circuit 6 uses a four-phase key input clock and determines whether an input signal is input to one of the three input terminals 9 when any one of the 12 key switches of the key matrix 2 is operated. It is determined which key switch has been operated by performing a logical product with the key input clock, and the determined output is supplied to the control circuit 7. Control circuit 7
is the discrimination output from the key discrimination circuit 6 and the input terminal 10 from the remote control receiving circuit 3.
According to the auxiliary control input inputted through the auxiliary control input, a control output for switching and controlling channels, power supply, volume, etc. is outputted to the switching control terminal 11 and added to the controlled circuit.

However, in such conventional devices,
In order to add control inputs from the two control input means of the key matrix 2 and the remote control receiving circuit 3, two sets of input terminals 9 and 10 are necessary, and the number of pins provided on the integrated circuit element 1 is large. Therefore, there was a problem that it was disadvantageous for making it into an integrated circuit element.

Therefore, the present invention solves such conventional drawbacks, and
It is an object of the present invention to provide a device that can input both an input from a key matrix and an auxiliary control input from an auxiliary control signal generation circuit using a minimum number of terminals, and is suitable for integrated circuit device implementation.

Hereinafter, a second embodiment of the present invention will be described.
This will be explained in detail with reference to FIGS.

In the figure, 12 is an integrated circuit element for control input discrimination processing, 13 is a key matrix for main input connected to the outside, and 14 is an auxiliary control signal generation circuit for auxiliary control input connected to the outside. This is a remote control receiving circuit. The integrated circuit element 12 includes a basic clock generation circuit 15.
, a multiphase clock generation circuit 16 , a gate circuit 17 for controlling the supply of a key input clock among the multiphase clocks, a key discrimination circuit 18 , an auxiliary input discrimination circuit 19 , and a control circuit 20 . , further includes a timer circuit 21 and gates 22 and 23 to control their operations. 24a
~24d is the output terminal of the key input clock, 25
x to 25z are input terminals into which both the key input clock selected by the key matrix 13 and the auxiliary control input generated by the remote control receiving circuit 14 are input, and 26x to 26z are gates for coupling these two inputs. , 27 are output terminals for switching control output.

Next, the operation in this configuration will be explained.

First, in the basic clock generation circuit 15, as shown in FIG.
The multiphase clock generating circuit 16 oscillates a basic clock such as A, and divides the basic clock A to generate five types of multiphase clocks such as Ba to Be, each having an easy phase. Of these, 4
The two multiphase clocks Ba to Bd are used as key input clocks, and the AND
It is taken out through gates 17a to 17d, outputted to key matrix 13 from output terminal 24, and AND gates 18ax to 18 of key discrimination circuit 18.
Also add to dz. On the other hand, the remaining one multiphase clock Be is applied to AND gates 19ex to 19ez of the auxiliary input discrimination circuit 19 via the OR gate 23. Furthermore, control inputs from the key matrix 13 and the remote control receiving circuit 14 are input to the input terminal 25x.
~25z to AND gate 1 of key discrimination circuit 18
8ax to 18dz and the AND gates 19ex to 19ez of the auxiliary input discrimination circuit 19.

Assume now that no auxiliary control input is applied from the remote control receiving circuit 14, and that a main control input is applied by operating any key in the key matrix 13. At that time, the key input clock added to the row to which the operated key belongs passes through that key, is taken out from the column to which the key belongs, is inputted to the input terminal 25 via the OR gate 26, and is input to the key discrimination circuit. Added to 18. Therefore, AND gate 1 of key discrimination circuit 18
For 8ax to 18dz, compare the input clock pulse for key input with the input pulse from key matrix 13 and find that both pulses match.
A determination output indicating which key has been operated is generated from the AND gates 18ax to 18dz. For example, if key 13cy of key matrix 13 is operated, key input clock Bc changes to key 1.
3cy is taken out and added to the input terminal 25y, and only the AND gate 18cy is connected to the key input clock Bc from the gate 17c and the input terminal 2.
It detects coincidence of input pulses from 5y and generates a discrimination output. When another key is operated, a key input determination output is similarly generated from the AND gates 26ax to 26dz corresponding to the operated key. Accordingly, the control circuit 7 generates a control output for controlling, for example, channel switching control, in accordance with the operated key, in accordance with the determined output.

Next, a case will be described in which a remote control signal such as a power supply switching signal is transmitted from a remote control transmitter (not shown), is received by a remote control receiver, and an auxiliary control input is applied. Here, as shown in FIG. 5C, the auxiliary control input consists of a leading pulse of a predetermined length T, followed by a pulse code modulated main pulse existing during a predetermined period t. do. The length T of the leading pulse must be longer than one period of the multiphase clock Be.

Now, assume that an auxiliary control input is generated from any of the output terminals x to y of the remote control receiver 14 and is input to the input terminals 25x to 25z via the OR gates 26x to 26z. At this time, AND gates 19ex to 19ez of the auxiliary input discrimination circuit 19 to which the multiphase clock Be is applied
, when the pulse of the multiphase clock Be and the leading pulse match, the discrimination output D of the auxiliary control input is
is generated. For example, when the auxiliary control input C is generated from the output terminal y of the remote control receiver 14, the input is input to the input terminal 25y.
, passes through the AND gate 19ey, and a discrimination output D is generated from time _t1 . This output D passes through the OR gate 29 of the timer circuit 21, and is applied to the AND gates 31 on one side as it is, and on the other side after being slightly delayed by (2n+1) (n is a natural number) inverting amplifiers 30. As a result, a set pulse E is generated from the AND gate 31 at the rising edge of the output D, which sets the flip-flop 32 so that the gate pulse F at the output of its Q terminal goes high from _t1 onwards. This passes through OR gate 23 to AND gate 1
Since it is added to 9ex~19ez, AND gate 1
9ex to 19ez continue to be conductive after time _t1 , and the auxiliary control input from the remote control receiving circuit 14 is applied to the control circuit 7 through the AND gates 19ex to 19ez. Therefore, the control circuit 7 uses a microcomputer or the like to identify the code of the auxiliary control input, and generates a control output for controlling, for example, channel switching control, in accordance with the code.

On the other hand, when the flip-flop 32 is set at time _t1 , the gate pulse output from its terminal is at time _t1.
After that, the level becomes low, and as a result, gate circuit 1
After _t1 , the AND gates 17a to 17d of 7 are shut off to stop supplying the key input clocks Ba to Bd. As a result, all the AND gates 18ax to 18dx of the key discrimination circuit 18 are also shut off, and the auxiliary control input from the remote control receiving circuit 14 is transmitted from the input terminals 25a to 25c to the AND gates 18ax to 18dx.
Even if they are added to 18dx, it is ensured that no erroneous discrimination output is generated from them.

Furthermore, the timer counter 3 is activated by the gate pulse F output from the Q terminal of the flip-flop 32.
3 is brought into operation after time _t1 . Furthermore, at the rising edge of the gate pulse, a clear pulse G is created by (2n+1) inverting amplifiers 34 and an AND gate 35, and is applied to the clear terminal of the counter 33 via an OR gate 36, thereby clearing it to the initial state. . This counter 33 counts the basic clock A from the basic clock generating circuit 15 and generates a time measurement output I when a predetermined time τ has elapsed, which is output to the flip-flop 3 via an OR gate 37.
2 is reset. However, if the previous auxiliary control input D and its inverted and delayed version are
By applying it to the NAND gate 38, a clear pulse H is generated at the rising edge of the auxiliary control input D, and the counter 33 is cleared via the OR gate 36. By setting the length to be longer than the pulse width or inter-pulse interval of any pulse in the auxiliary control input D, the counter 33 is reset while the auxiliary control input D continues to be input. The pulse I is not generated, and the reset pulse I is generated to reset the flip-flop 32 only at time _t2 , after a time τ has elapsed after the auxiliary control input D is terminated. As a result, after time _t2 , AND gates 17a to 17
d, 18ax to 18dz are conductive, AND gate 19
ex~19ez shuts off and returns to standby state.

In addition, 39 is the flip-flop 3 when the power is turned on.
This is a power-on reset circuit that generates a reset pulse to forcibly set the device to the reset state.

In this way, according to this circuit, only one set of input terminals 25x to 25y is connected to the key matrix 13.
It can be used both for inputting the main control input from the remote control receiving circuit 14 and for inputting the auxiliary control input from the remote control receiving circuit 14, and the number of pins provided on the integrated circuit element 12 can be reduced. This makes it possible to obtain a device suitable for elementalization.

The above description includes means for generating a multiphase clock, means for controlling its supply, means for determining main control input from a key matrix, means for determining auxiliary control input from a remote control receiving circuit, etc. Although the case has been described in which both the means for generating control output and the means for performing timer operation are configured using hard logic circuits, it is also possible to configure these means using a microprocessor unit such as a microcomputer and execute the program. It goes without saying that this may be achieved by.

As detailed above, according to the present invention, the number of input terminals for inputting the main control input from the key matrix and the other auxiliary control inputs can be minimized, and the integrated circuit element This makes it possible to obtain a control input device suitable for

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional control input device, Fig. 2 is a block diagram of a control input device according to an embodiment of the present invention, Figs. 3 and 4 are specific circuit diagrams of a part thereof, and Fig. 5 is a waveform diagram of each part. 12... integrated circuit element, 13... key matrix, 14... remote control receiving circuit, 1
5...Basic clock generation circuit, 16...Multiphase clock generation circuit, 17...Gate circuit, 18...Key discrimination circuit, 19...Auxiliary input discrimination circuit, 20...
...Control circuit, 21...Timer circuit, 22, 23
...OR gate, 24...output terminal, 25...input terminal, 26...OR gate, 27...output terminal.

Claims (1)

[Claims] 1. A multiphase clock generating means that generates a plurality of multiphase clocks each having a different phase by frequency dividing a basic clock, and an integrated circuit element that uses only a portion of the multiphase clocks as a key input clock. an output terminal for outputting to an external key matrix; and an input terminal to which a selected key input clock from the key matrix and auxiliary control inputs from a control signal generation circuit external to the integrated circuit element are applied. , key determining means for determining which key in the key matrix has been operated based on a key input clock applied to the output terminal and a key input clock input from the input terminal, and supplying the determined key to the control means; Detection means for detecting that the auxiliary control input is applied by a clock other than the one outputted as a key input clock among the multiphase clocks and an auxiliary control input applied from the input terminal; and timer means for stopping the output of the key input clock for a certain period of time by force and supplying the auxiliary control input to the control means, and each of the above means is provided in an integrated circuit element. control input device.